mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 19:21:31 -04:00
Merge branch 'master' into for-2.6.31
Conflicts: drivers/block/hd.c drivers/block/mg_disk.c Signed-off-by: Jens Axboe <[email protected]>
This commit is contained in:
Jens Axboe
commit
e4b636366c
976 changed files with 23650 additions and 19430 deletions
|
|
@ -72,6 +72,7 @@
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|||
* ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
|
||||
* and must be dword aligned
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||||
* ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
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||||
* ICH7 errata #16 - MWDMA1 timings are incorrect
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||||
*
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* Should have been BIOS fixed:
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* 450NX: errata #19 - DMA hangs on old 450NX
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|
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@ -94,7 +95,7 @@
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|||
#include <linux/dmi.h>
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#define DRV_NAME "ata_piix"
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#define DRV_VERSION "2.12"
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#define DRV_VERSION "2.13"
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enum {
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PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
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|
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@ -136,6 +137,7 @@ enum piix_controller_ids {
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ich_pata_33, /* ICH up to UDMA 33 only */
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ich_pata_66, /* ICH up to 66 Mhz */
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ich_pata_100, /* ICH up to UDMA 100 */
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ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
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ich5_sata,
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ich6_sata,
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ich6m_sata,
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@ -216,8 +218,8 @@ static const struct pci_device_id piix_pci_tbl[] = {
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/* ICH6 (and 6) (i915) UDMA 100 */
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{ 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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/* ICH7/7-R (i945, i975) UDMA 100*/
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{ 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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{ 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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{ 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
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{ 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
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/* ICH8 Mobile PATA Controller */
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{ 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
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@ -487,6 +489,15 @@ static struct ata_port_info piix_port_info[] = {
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.port_ops = &ich_pata_ops,
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},
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[ich_pata_100_nomwdma1] =
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{
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.flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2_ONLY,
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.udma_mask = ATA_UDMA5,
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.port_ops = &ich_pata_ops,
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},
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[ich5_sata] =
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{
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.flags = PIIX_SATA_FLAGS,
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|
|
@ -594,6 +605,7 @@ static const struct ich_laptop ich_laptop[] = {
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{ 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
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{ 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
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{ 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
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{ 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
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/* end marker */
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{ 0, }
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};
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|
|
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|||
|
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@ -4091,7 +4091,9 @@ int ata_dev_revalidate(struct ata_device *dev, unsigned int new_class,
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/* fail early if !ATA && !ATAPI to avoid issuing [P]IDENTIFY to PMP */
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if (ata_class_enabled(new_class) &&
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new_class != ATA_DEV_ATA && new_class != ATA_DEV_ATAPI) {
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new_class != ATA_DEV_ATA &&
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new_class != ATA_DEV_ATAPI &&
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new_class != ATA_DEV_SEMB) {
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ata_dev_printk(dev, KERN_INFO, "class mismatch %u != %u\n",
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dev->class, new_class);
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rc = -ENODEV;
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|
|
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|||
|
|
@ -2783,6 +2783,12 @@ static int ata_eh_revalidate_and_attach(struct ata_link *link,
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} else if (dev->class == ATA_DEV_UNKNOWN &&
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ehc->tries[dev->devno] &&
|
||||
ata_class_enabled(ehc->classes[dev->devno])) {
|
||||
/* Temporarily set dev->class, it will be
|
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* permanently set once all configurations are
|
||||
* complete. This is necessary because new
|
||||
* device configuration is done in two
|
||||
* separate loops.
|
||||
*/
|
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dev->class = ehc->classes[dev->devno];
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|
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if (dev->class == ATA_DEV_PMP)
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|
|
@ -2790,6 +2796,11 @@ static int ata_eh_revalidate_and_attach(struct ata_link *link,
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else
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rc = ata_dev_read_id(dev, &dev->class,
|
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readid_flags, dev->id);
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|
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/* read_id might have changed class, store and reset */
|
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ehc->classes[dev->devno] = dev->class;
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dev->class = ATA_DEV_UNKNOWN;
|
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|
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switch (rc) {
|
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case 0:
|
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/* clear error info accumulated during probe */
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|
|
@ -2799,13 +2810,11 @@ static int ata_eh_revalidate_and_attach(struct ata_link *link,
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case -ENOENT:
|
||||
/* IDENTIFY was issued to non-existent
|
||||
* device. No need to reset. Just
|
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* thaw and kill the device.
|
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* thaw and ignore the device.
|
||||
*/
|
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ata_eh_thaw_port(ap);
|
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dev->class = ATA_DEV_UNKNOWN;
|
||||
break;
|
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default:
|
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dev->class = ATA_DEV_UNKNOWN;
|
||||
goto err;
|
||||
}
|
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}
|
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|
|
@ -2826,11 +2835,15 @@ static int ata_eh_revalidate_and_attach(struct ata_link *link,
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dev->class == ATA_DEV_PMP)
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continue;
|
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dev->class = ehc->classes[dev->devno];
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|
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ehc->i.flags |= ATA_EHI_PRINTINFO;
|
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rc = ata_dev_configure(dev);
|
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ehc->i.flags &= ~ATA_EHI_PRINTINFO;
|
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if (rc)
|
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if (rc) {
|
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dev->class = ATA_DEV_UNKNOWN;
|
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goto err;
|
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}
|
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|
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spin_lock_irqsave(ap->lock, flags);
|
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ap->pflags |= ATA_PFLAG_SCSI_HOTPLUG;
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|
|
@ -3494,6 +3507,8 @@ static void ata_eh_handle_port_suspend(struct ata_port *ap)
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*/
|
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static void ata_eh_handle_port_resume(struct ata_port *ap)
|
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{
|
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struct ata_link *link;
|
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struct ata_device *dev;
|
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unsigned long flags;
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int rc = 0;
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|
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|
|
@ -3508,6 +3523,17 @@ static void ata_eh_handle_port_resume(struct ata_port *ap)
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|
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WARN_ON(!(ap->pflags & ATA_PFLAG_SUSPENDED));
|
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|
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/*
|
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* Error timestamps are in jiffies which doesn't run while
|
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* suspended and PHY events during resume isn't too uncommon.
|
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* When the two are combined, it can lead to unnecessary speed
|
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* downs if the machine is suspended and resumed repeatedly.
|
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* Clear error history.
|
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*/
|
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ata_for_each_link(link, ap, HOST_FIRST)
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ata_for_each_dev(dev, link, ALL)
|
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ata_ering_clear(&dev->ering);
|
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|
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ata_acpi_set_state(ap, PMSG_ON);
|
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|
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if (ap->ops->port_resume)
|
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|
|
|
|||
|
|
@ -313,7 +313,7 @@ ata_scsi_em_message_show(struct device *dev, struct device_attribute *attr,
|
|||
return ap->ops->em_show(ap, buf);
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return -EINVAL;
|
||||
}
|
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DEVICE_ATTR(em_message, S_IRUGO | S_IWUGO,
|
||||
DEVICE_ATTR(em_message, S_IRUGO | S_IWUSR,
|
||||
ata_scsi_em_message_show, ata_scsi_em_message_store);
|
||||
EXPORT_SYMBOL_GPL(dev_attr_em_message);
|
||||
|
||||
|
|
@ -366,7 +366,7 @@ ata_scsi_activity_store(struct device *dev, struct device_attribute *attr,
|
|||
}
|
||||
return -EINVAL;
|
||||
}
|
||||
DEVICE_ATTR(sw_activity, S_IWUGO | S_IRUGO, ata_scsi_activity_show,
|
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DEVICE_ATTR(sw_activity, S_IWUSR | S_IRUGO, ata_scsi_activity_show,
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ata_scsi_activity_store);
|
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EXPORT_SYMBOL_GPL(dev_attr_sw_activity);
|
||||
|
||||
|
|
@ -2142,13 +2142,14 @@ static unsigned int ata_scsiop_inq_89(struct ata_scsi_args *args, u8 *rbuf)
|
|||
|
||||
static unsigned int ata_scsiop_inq_b1(struct ata_scsi_args *args, u8 *rbuf)
|
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{
|
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int form_factor = ata_id_form_factor(args->id);
|
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int media_rotation_rate = ata_id_rotation_rate(args->id);
|
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|
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rbuf[1] = 0xb1;
|
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rbuf[3] = 0x3c;
|
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if (ata_id_major_version(args->id) > 7) {
|
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rbuf[4] = args->id[217] >> 8;
|
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rbuf[5] = args->id[217];
|
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rbuf[7] = args->id[168] & 0xf;
|
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}
|
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rbuf[4] = media_rotation_rate >> 8;
|
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rbuf[5] = media_rotation_rate;
|
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rbuf[7] = form_factor;
|
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|
||||
return 0;
|
||||
}
|
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|
|
@ -2376,7 +2377,23 @@ saving_not_supp:
|
|||
*/
|
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static unsigned int ata_scsiop_read_cap(struct ata_scsi_args *args, u8 *rbuf)
|
||||
{
|
||||
u64 last_lba = args->dev->n_sectors - 1; /* LBA of the last block */
|
||||
struct ata_device *dev = args->dev;
|
||||
u64 last_lba = dev->n_sectors - 1; /* LBA of the last block */
|
||||
u8 log_per_phys = 0;
|
||||
u16 lowest_aligned = 0;
|
||||
u16 word_106 = dev->id[106];
|
||||
u16 word_209 = dev->id[209];
|
||||
|
||||
if ((word_106 & 0xc000) == 0x4000) {
|
||||
/* Number and offset of logical sectors per physical sector */
|
||||
if (word_106 & (1 << 13))
|
||||
log_per_phys = word_106 & 0xf;
|
||||
if ((word_209 & 0xc000) == 0x4000) {
|
||||
u16 first = dev->id[209] & 0x3fff;
|
||||
if (first > 0)
|
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lowest_aligned = (1 << log_per_phys) - first;
|
||||
}
|
||||
}
|
||||
|
||||
VPRINTK("ENTER\n");
|
||||
|
||||
|
|
@ -2407,6 +2424,11 @@ static unsigned int ata_scsiop_read_cap(struct ata_scsi_args *args, u8 *rbuf)
|
|||
/* sector size */
|
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rbuf[10] = ATA_SECT_SIZE >> 8;
|
||||
rbuf[11] = ATA_SECT_SIZE & 0xff;
|
||||
|
||||
rbuf[12] = 0;
|
||||
rbuf[13] = log_per_phys;
|
||||
rbuf[14] = (lowest_aligned >> 8) & 0x3f;
|
||||
rbuf[15] = lowest_aligned;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
* pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
|
||||
* (C) 2005 Red Hat Inc
|
||||
* Alan Cox <alan@lxorguk.ukuu.org.uk>
|
||||
* (C) 2007 Bartlomiej Zolnierkiewicz
|
||||
* (C) 2007,2009 Bartlomiej Zolnierkiewicz
|
||||
*
|
||||
* Based in part on linux/drivers/ide/pci/pdc202xx_old.c
|
||||
*
|
||||
|
|
@ -158,7 +158,7 @@ static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
|
|||
u32 len;
|
||||
|
||||
/* Check we keep host level locking here */
|
||||
if (adev->dma_mode >= XFER_UDMA_2)
|
||||
if (adev->dma_mode > XFER_UDMA_2)
|
||||
iowrite8(ioread8(clock) | sel66, clock);
|
||||
else
|
||||
iowrite8(ioread8(clock) & ~sel66, clock);
|
||||
|
|
@ -212,7 +212,7 @@ static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
|
|||
iowrite8(ioread8(clock) & ~sel66, clock);
|
||||
}
|
||||
/* Flip back to 33Mhz for PIO */
|
||||
if (adev->dma_mode >= XFER_UDMA_2)
|
||||
if (adev->dma_mode > XFER_UDMA_2)
|
||||
iowrite8(ioread8(clock) & ~sel66, clock);
|
||||
ata_bmdma_stop(qc);
|
||||
pdc202xx_set_piomode(ap, adev);
|
||||
|
|
|
|||
|
|
@ -205,6 +205,7 @@ struct cmdhdr_tbl_entry {
|
|||
* Description information bitdefs
|
||||
*/
|
||||
enum {
|
||||
CMD_DESC_RES = (1 << 11),
|
||||
VENDOR_SPECIFIC_BIST = (1 << 10),
|
||||
CMD_DESC_SNOOP_ENABLE = (1 << 9),
|
||||
FPDMA_QUEUED_CMD = (1 << 8),
|
||||
|
|
@ -332,13 +333,14 @@ static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
|
|||
dma_addr_t sg_addr = sg_dma_address(sg);
|
||||
u32 sg_len = sg_dma_len(sg);
|
||||
|
||||
VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%x, sg_len = %d\n",
|
||||
sg_addr, sg_len);
|
||||
VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n",
|
||||
(unsigned long long)sg_addr, sg_len);
|
||||
|
||||
/* warn if each s/g element is not dword aligned */
|
||||
if (sg_addr & 0x03)
|
||||
ata_port_printk(qc->ap, KERN_ERR,
|
||||
"s/g addr unaligned : 0x%x\n", sg_addr);
|
||||
"s/g addr unaligned : 0x%llx\n",
|
||||
(unsigned long long)sg_addr);
|
||||
if (sg_len & 0x03)
|
||||
ata_port_printk(qc->ap, KERN_ERR,
|
||||
"s/g len unaligned : 0x%x\n", sg_len);
|
||||
|
|
@ -387,7 +389,7 @@ static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
|
|||
void __iomem *hcr_base = host_priv->hcr_base;
|
||||
unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
|
||||
struct command_desc *cd;
|
||||
u32 desc_info = CMD_DESC_SNOOP_ENABLE;
|
||||
u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
|
||||
u32 num_prde = 0;
|
||||
u32 ttl_dwords = 0;
|
||||
dma_addr_t cd_paddr;
|
||||
|
|
@ -840,7 +842,7 @@ issue_srst:
|
|||
|
||||
/* device reset/SRST is a control register update FIS, uses tag0 */
|
||||
sata_fsl_setup_cmd_hdr_entry(pp, 0,
|
||||
SRST_CMD | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
|
||||
SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
|
||||
|
||||
tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
|
||||
ata_tf_to_fis(&tf, pmp, 0, cfis);
|
||||
|
|
@ -886,7 +888,8 @@ issue_srst:
|
|||
* using ATA signature D2H register FIS to the host controller.
|
||||
*/
|
||||
|
||||
sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
|
||||
sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
|
||||
0, 0, 5);
|
||||
|
||||
tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
|
||||
ata_tf_to_fis(&tf, pmp, 0, cfis);
|
||||
|
|
|
|||
|
|
@ -293,6 +293,10 @@ enum {
|
|||
FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
|
||||
FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
|
||||
|
||||
PHY_MODE9_GEN2 = 0x398,
|
||||
PHY_MODE9_GEN1 = 0x39c,
|
||||
PHYCFG_OFS = 0x3a0, /* only in 65n devices */
|
||||
|
||||
MV5_PHY_MODE = 0x74,
|
||||
MV5_LTMODE = 0x30,
|
||||
MV5_PHY_CTL = 0x0C,
|
||||
|
|
@ -609,6 +613,8 @@ static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
|
|||
static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
|
||||
void __iomem *mmio);
|
||||
static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
|
||||
static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
|
||||
void __iomem *mmio, unsigned int port);
|
||||
static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
|
||||
static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
|
||||
unsigned int port_no);
|
||||
|
|
@ -807,6 +813,14 @@ static const struct mv_hw_ops mv_soc_ops = {
|
|||
.reset_bus = mv_soc_reset_bus,
|
||||
};
|
||||
|
||||
static const struct mv_hw_ops mv_soc_65n_ops = {
|
||||
.phy_errata = mv_soc_65n_phy_errata,
|
||||
.enable_leds = mv_soc_enable_leds,
|
||||
.reset_hc = mv_soc_reset_hc,
|
||||
.reset_flash = mv_soc_reset_flash,
|
||||
.reset_bus = mv_soc_reset_bus,
|
||||
};
|
||||
|
||||
/*
|
||||
* Functions
|
||||
*/
|
||||
|
|
@ -3397,6 +3411,53 @@ static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
|
|||
return;
|
||||
}
|
||||
|
||||
static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
|
||||
void __iomem *mmio, unsigned int port)
|
||||
{
|
||||
void __iomem *port_mmio = mv_port_base(mmio, port);
|
||||
u32 reg;
|
||||
|
||||
reg = readl(port_mmio + PHY_MODE3);
|
||||
reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
|
||||
reg |= (0x1 << 27);
|
||||
reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
|
||||
reg |= (0x1 << 29);
|
||||
writel(reg, port_mmio + PHY_MODE3);
|
||||
|
||||
reg = readl(port_mmio + PHY_MODE4);
|
||||
reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
|
||||
reg |= (0x1 << 16);
|
||||
writel(reg, port_mmio + PHY_MODE4);
|
||||
|
||||
reg = readl(port_mmio + PHY_MODE9_GEN2);
|
||||
reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
|
||||
reg |= 0x8;
|
||||
reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
|
||||
writel(reg, port_mmio + PHY_MODE9_GEN2);
|
||||
|
||||
reg = readl(port_mmio + PHY_MODE9_GEN1);
|
||||
reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
|
||||
reg |= 0x8;
|
||||
reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
|
||||
writel(reg, port_mmio + PHY_MODE9_GEN1);
|
||||
}
|
||||
|
||||
/**
|
||||
* soc_is_65 - check if the soc is 65 nano device
|
||||
*
|
||||
* Detect the type of the SoC, this is done by reading the PHYCFG_OFS
|
||||
* register, this register should contain non-zero value and it exists only
|
||||
* in the 65 nano devices, when reading it from older devices we get 0.
|
||||
*/
|
||||
static bool soc_is_65n(struct mv_host_priv *hpriv)
|
||||
{
|
||||
void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
|
||||
|
||||
if (readl(port0_mmio + PHYCFG_OFS))
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
|
||||
static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
|
||||
{
|
||||
u32 ifcfg = readl(port_mmio + SATA_IFCFG);
|
||||
|
|
@ -3737,7 +3798,10 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
|
|||
}
|
||||
break;
|
||||
case chip_soc:
|
||||
hpriv->ops = &mv_soc_ops;
|
||||
if (soc_is_65n(hpriv))
|
||||
hpriv->ops = &mv_soc_65n_ops;
|
||||
else
|
||||
hpriv->ops = &mv_soc_ops;
|
||||
hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
|
||||
MV_HP_ERRATA_60X1C0;
|
||||
break;
|
||||
|
|
@ -3800,7 +3864,8 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx)
|
|||
n_hc = mv_get_hc_count(host->ports[0]->flags);
|
||||
|
||||
for (port = 0; port < host->n_ports; port++)
|
||||
hpriv->ops->read_preamp(hpriv, port, mmio);
|
||||
if (hpriv->ops->read_preamp)
|
||||
hpriv->ops->read_preamp(hpriv, port, mmio);
|
||||
|
||||
rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
|
||||
if (rc)
|
||||
|
|
|
|||
|
|
@ -213,8 +213,9 @@ struct pdc_host_priv {
|
|||
|
||||
|
||||
static int pdc_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
|
||||
static void pdc_eng_timeout(struct ata_port *ap);
|
||||
static void pdc_20621_phy_reset(struct ata_port *ap);
|
||||
static void pdc_error_handler(struct ata_port *ap);
|
||||
static void pdc_freeze(struct ata_port *ap);
|
||||
static void pdc_thaw(struct ata_port *ap);
|
||||
static int pdc_port_start(struct ata_port *ap);
|
||||
static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
|
||||
static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
|
||||
|
|
@ -233,6 +234,10 @@ static void pdc20621_put_to_dimm(struct ata_host *host,
|
|||
void *psource, u32 offset, u32 size);
|
||||
static void pdc20621_irq_clear(struct ata_port *ap);
|
||||
static unsigned int pdc20621_qc_issue(struct ata_queued_cmd *qc);
|
||||
static int pdc_softreset(struct ata_link *link, unsigned int *class,
|
||||
unsigned long deadline);
|
||||
static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
|
||||
static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
|
||||
|
||||
|
||||
static struct scsi_host_template pdc_sata_sht = {
|
||||
|
|
@ -243,20 +248,24 @@ static struct scsi_host_template pdc_sata_sht = {
|
|||
|
||||
/* TODO: inherit from base port_ops after converting to new EH */
|
||||
static struct ata_port_operations pdc_20621_ops = {
|
||||
.sff_tf_load = pdc_tf_load_mmio,
|
||||
.sff_tf_read = ata_sff_tf_read,
|
||||
.sff_check_status = ata_sff_check_status,
|
||||
.sff_exec_command = pdc_exec_command_mmio,
|
||||
.sff_dev_select = ata_sff_dev_select,
|
||||
.phy_reset = pdc_20621_phy_reset,
|
||||
.inherits = &ata_sff_port_ops,
|
||||
|
||||
.check_atapi_dma = pdc_check_atapi_dma,
|
||||
.qc_prep = pdc20621_qc_prep,
|
||||
.qc_issue = pdc20621_qc_issue,
|
||||
.qc_fill_rtf = ata_sff_qc_fill_rtf,
|
||||
.sff_data_xfer = ata_sff_data_xfer,
|
||||
.eng_timeout = pdc_eng_timeout,
|
||||
.sff_irq_clear = pdc20621_irq_clear,
|
||||
.sff_irq_on = ata_sff_irq_on,
|
||||
|
||||
.freeze = pdc_freeze,
|
||||
.thaw = pdc_thaw,
|
||||
.softreset = pdc_softreset,
|
||||
.error_handler = pdc_error_handler,
|
||||
.lost_interrupt = ATA_OP_NULL,
|
||||
.post_internal_cmd = pdc_post_internal_cmd,
|
||||
|
||||
.port_start = pdc_port_start,
|
||||
|
||||
.sff_tf_load = pdc_tf_load_mmio,
|
||||
.sff_exec_command = pdc_exec_command_mmio,
|
||||
.sff_irq_clear = pdc20621_irq_clear,
|
||||
};
|
||||
|
||||
static const struct ata_port_info pdc_port_info[] = {
|
||||
|
|
@ -310,14 +319,6 @@ static int pdc_port_start(struct ata_port *ap)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void pdc_20621_phy_reset(struct ata_port *ap)
|
||||
{
|
||||
VPRINTK("ENTER\n");
|
||||
ap->cbl = ATA_CBL_SATA;
|
||||
ata_port_probe(ap);
|
||||
ata_bus_reset(ap);
|
||||
}
|
||||
|
||||
static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
|
||||
unsigned int portno,
|
||||
unsigned int total_len)
|
||||
|
|
@ -686,8 +687,11 @@ static void pdc20621_packet_start(struct ata_queued_cmd *qc)
|
|||
static unsigned int pdc20621_qc_issue(struct ata_queued_cmd *qc)
|
||||
{
|
||||
switch (qc->tf.protocol) {
|
||||
case ATA_PROT_DMA:
|
||||
case ATA_PROT_NODATA:
|
||||
if (qc->tf.flags & ATA_TFLAG_POLLING)
|
||||
break;
|
||||
/*FALLTHROUGH*/
|
||||
case ATA_PROT_DMA:
|
||||
pdc20621_packet_start(qc);
|
||||
return 0;
|
||||
|
||||
|
|
@ -786,12 +790,7 @@ static inline unsigned int pdc20621_host_intr(struct ata_port *ap,
|
|||
|
||||
static void pdc20621_irq_clear(struct ata_port *ap)
|
||||
{
|
||||
struct ata_host *host = ap->host;
|
||||
void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
|
||||
|
||||
mmio += PDC_CHIP0_OFS;
|
||||
|
||||
readl(mmio + PDC_20621_SEQMASK);
|
||||
ioread8(ap->ioaddr.status_addr);
|
||||
}
|
||||
|
||||
static irqreturn_t pdc20621_interrupt(int irq, void *dev_instance)
|
||||
|
|
@ -859,46 +858,119 @@ static irqreturn_t pdc20621_interrupt(int irq, void *dev_instance)
|
|||
return IRQ_RETVAL(handled);
|
||||
}
|
||||
|
||||
static void pdc_eng_timeout(struct ata_port *ap)
|
||||
static void pdc_freeze(struct ata_port *ap)
|
||||
{
|
||||
u8 drv_stat;
|
||||
struct ata_host *host = ap->host;
|
||||
struct ata_queued_cmd *qc;
|
||||
unsigned long flags;
|
||||
void __iomem *mmio = ap->ioaddr.cmd_addr;
|
||||
u32 tmp;
|
||||
|
||||
DPRINTK("ENTER\n");
|
||||
/* FIXME: if all 4 ATA engines are stopped, also stop HDMA engine */
|
||||
|
||||
spin_lock_irqsave(&host->lock, flags);
|
||||
tmp = readl(mmio + PDC_CTLSTAT);
|
||||
tmp |= PDC_MASK_INT;
|
||||
tmp &= ~PDC_DMA_ENABLE;
|
||||
writel(tmp, mmio + PDC_CTLSTAT);
|
||||
readl(mmio + PDC_CTLSTAT); /* flush */
|
||||
}
|
||||
|
||||
qc = ata_qc_from_tag(ap, ap->link.active_tag);
|
||||
static void pdc_thaw(struct ata_port *ap)
|
||||
{
|
||||
void __iomem *mmio = ap->ioaddr.cmd_addr;
|
||||
u32 tmp;
|
||||
|
||||
switch (qc->tf.protocol) {
|
||||
case ATA_PROT_DMA:
|
||||
case ATA_PROT_NODATA:
|
||||
ata_port_printk(ap, KERN_ERR, "command timeout\n");
|
||||
qc->err_mask |= __ac_err_mask(ata_wait_idle(ap));
|
||||
break;
|
||||
/* FIXME: start HDMA engine, if zero ATA engines running */
|
||||
|
||||
default:
|
||||
drv_stat = ata_sff_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
|
||||
/* clear IRQ */
|
||||
ioread8(ap->ioaddr.status_addr);
|
||||
|
||||
ata_port_printk(ap, KERN_ERR,
|
||||
"unknown timeout, cmd 0x%x stat 0x%x\n",
|
||||
qc->tf.command, drv_stat);
|
||||
/* turn IRQ back on */
|
||||
tmp = readl(mmio + PDC_CTLSTAT);
|
||||
tmp &= ~PDC_MASK_INT;
|
||||
writel(tmp, mmio + PDC_CTLSTAT);
|
||||
readl(mmio + PDC_CTLSTAT); /* flush */
|
||||
}
|
||||
|
||||
qc->err_mask |= ac_err_mask(drv_stat);
|
||||
break;
|
||||
static void pdc_reset_port(struct ata_port *ap)
|
||||
{
|
||||
void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
|
||||
unsigned int i;
|
||||
u32 tmp;
|
||||
|
||||
/* FIXME: handle HDMA copy engine */
|
||||
|
||||
for (i = 11; i > 0; i--) {
|
||||
tmp = readl(mmio);
|
||||
if (tmp & PDC_RESET)
|
||||
break;
|
||||
|
||||
udelay(100);
|
||||
|
||||
tmp |= PDC_RESET;
|
||||
writel(tmp, mmio);
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&host->lock, flags);
|
||||
ata_eh_qc_complete(qc);
|
||||
DPRINTK("EXIT\n");
|
||||
tmp &= ~PDC_RESET;
|
||||
writel(tmp, mmio);
|
||||
readl(mmio); /* flush */
|
||||
}
|
||||
|
||||
static int pdc_softreset(struct ata_link *link, unsigned int *class,
|
||||
unsigned long deadline)
|
||||
{
|
||||
pdc_reset_port(link->ap);
|
||||
return ata_sff_softreset(link, class, deadline);
|
||||
}
|
||||
|
||||
static void pdc_error_handler(struct ata_port *ap)
|
||||
{
|
||||
if (!(ap->pflags & ATA_PFLAG_FROZEN))
|
||||
pdc_reset_port(ap);
|
||||
|
||||
ata_std_error_handler(ap);
|
||||
}
|
||||
|
||||
static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
|
||||
{
|
||||
struct ata_port *ap = qc->ap;
|
||||
|
||||
/* make DMA engine forget about the failed command */
|
||||
if (qc->flags & ATA_QCFLAG_FAILED)
|
||||
pdc_reset_port(ap);
|
||||
}
|
||||
|
||||
static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
|
||||
{
|
||||
u8 *scsicmd = qc->scsicmd->cmnd;
|
||||
int pio = 1; /* atapi dma off by default */
|
||||
|
||||
/* Whitelist commands that may use DMA. */
|
||||
switch (scsicmd[0]) {
|
||||
case WRITE_12:
|
||||
case WRITE_10:
|
||||
case WRITE_6:
|
||||
case READ_12:
|
||||
case READ_10:
|
||||
case READ_6:
|
||||
case 0xad: /* READ_DVD_STRUCTURE */
|
||||
case 0xbe: /* READ_CD */
|
||||
pio = 0;
|
||||
}
|
||||
/* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
|
||||
if (scsicmd[0] == WRITE_10) {
|
||||
unsigned int lba =
|
||||
(scsicmd[2] << 24) |
|
||||
(scsicmd[3] << 16) |
|
||||
(scsicmd[4] << 8) |
|
||||
scsicmd[5];
|
||||
if (lba >= 0xFFFF4FA2)
|
||||
pio = 1;
|
||||
}
|
||||
return pio;
|
||||
}
|
||||
|
||||
static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
|
||||
{
|
||||
WARN_ON(tf->protocol == ATA_PROT_DMA ||
|
||||
tf->protocol == ATA_PROT_NODATA);
|
||||
tf->protocol == ATAPI_PROT_DMA);
|
||||
ata_sff_tf_load(ap, tf);
|
||||
}
|
||||
|
||||
|
|
@ -906,7 +978,7 @@ static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
|
|||
static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
|
||||
{
|
||||
WARN_ON(tf->protocol == ATA_PROT_DMA ||
|
||||
tf->protocol == ATA_PROT_NODATA);
|
||||
tf->protocol == ATAPI_PROT_DMA);
|
||||
ata_sff_exec_command(ap, tf);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue