mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 03:01:39 -04:00
USB driver patches for 3.16-rc1
Here is the big USB driver pull request for 3.16-rc1. Nothing huge here, but lots of little things in the USB core, and in lots of drivers. Hopefully the USB power management will be work better now that it has been reworked to do per-port power control dynamically. There's also a raft of gadget driver updates and fixes, CONFIG_USB_DEBUG is finally gone now that everything has been converted over to the dynamic debug inteface, the last hold-out drivers were cleaned up and the config option removed. There were also other minor things all through the drivers/usb/ tree, the shortlog shows this pretty well. All have been in linux-next, including the very last patch, which came from linux-next to fix a build issue on some platforms. Signed-off-by: Greg Kroah-Hartman <[email protected]> -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iEYEABECAAYFAlONYEMACgkQMUfUDdst+ynxvgCggMQBhN5icth8Y5hFglNNaISN c4AAoMHR2kb62U1plylLbPnboQTjfcl0 =fG6y -----END PGP SIGNATURE----- Merge tag 'usb-3.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb into next Pull USB driver updates from Greg KH: "Here is the big USB driver pull request for 3.16-rc1. Nothing huge here, but lots of little things in the USB core, and in lots of drivers. Hopefully the USB power management will be work better now that it has been reworked to do per-port power control dynamically. There's also a raft of gadget driver updates and fixes, CONFIG_USB_DEBUG is finally gone now that everything has been converted over to the dynamic debug inteface, the last hold-out drivers were cleaned up and the config option removed. There were also other minor things all through the drivers/usb/ tree, the shortlog shows this pretty well. All have been in linux-next, including the very last patch, which came from linux-next to fix a build issue on some platforms" * tag 'usb-3.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (314 commits) usb: hub_handle_remote_wakeup() only exists for CONFIG_PM=y USB: orinoco_usb: remove CONFIG_USB_DEBUG support USB: media: lirc: igorplugusb: remove CONFIG_USB_DEBUG support USB: media: streamzap: remove CONFIG_USB_DEBUG USB: media: redrat3: remove CONFIG_USB_DEBUG usage USB: media: redrat3: remove unneeded tracing macro usb: qcserial: add additional Sierra Wireless QMI devices usb: host: max3421-hcd: Use module_spi_driver usb: host: max3421-hcd: Allow platform-data to specify Vbus polarity usb: host: max3421-hcd: fix "spi_rd8" uses dynamic stack allocation warning usb: host: max3421-hcd: Fix missing unlock in max3421_urb_enqueue() usb: qcserial: add Netgear AirCard 341U Documentation: dt-bindings: update xhci-platform DT binding for R-Car H2 and M2 usb: host: xhci-plat: add xhci_plat_start() usb: host: max3421-hcd: Fix potential NULL urb dereference Revert "usb: gadget: net2280: Add support for PLX USB338X" USB: usbip: remove CONFIG_USB_DEBUG reference USB: remove CONFIG_USB_DEBUG from defconfig files usb: resume child device when port is powered on usb: hub_handle_remote_wakeup() depends on CONFIG_PM_RUNTIME=y ...
This commit is contained in:
Linus Torvalds
commit
e5c4ecdc55
291 changed files with 14364 additions and 6800 deletions
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@ -114,3 +114,50 @@ Example:
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compatible = "samsung,exynos-sataphy-i2c";
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reg = <0x38>;
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};
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Samsung Exynos5 SoC series USB DRD PHY controller
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--------------------------------------------------
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Required properties:
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- compatible : Should be set to one of the following supported values:
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- "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
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- "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
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- reg : Register offset and length of USB DRD PHY register set;
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- clocks: Clock IDs array as required by the controller
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- clock-names: names of clocks correseponding to IDs in the clock property;
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Required clocks:
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- phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),
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used for register access.
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- ref: PHY's reference clock (usually crystal clock), used for
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PHY operations, associated by phy name. It is used to
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determine bit values for clock settings register.
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For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
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- samsung,pmu-syscon: phandle for PMU system controller interface, used to
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control pmu registers for power isolation.
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- #phy-cells : from the generic PHY bindings, must be 1;
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For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy"
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compatible PHYs, the second cell in the PHY specifier identifies the
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PHY id, which is interpreted as follows:
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0 - UTMI+ type phy,
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1 - PIPE3 type phy,
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Example:
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usbdrd_phy: usbphy@12100000 {
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compatible = "samsung,exynos5250-usbdrd-phy";
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reg = <0x12100000 0x100>;
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clocks = <&clock 286>, <&clock 1>;
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clock-names = "phy", "ref";
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samsung,pmu-syscon = <&pmu_system_controller>;
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#phy-cells = <1>;
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};
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- aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
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'usbdrd_phy' nodes should have numbered alias in the aliases node,
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in the form of usbdrdphyN, N = 0, 1... (depending on number of
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controllers).
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Example:
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aliases {
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usbdrdphy0 = &usb3_phy0;
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usbdrdphy1 = &usb3_phy1;
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};
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@ -2,15 +2,26 @@ Allwinner sun4i USB PHY
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-----------------------
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Required properties:
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- compatible : should be one of "allwinner,sun4i-a10-usb-phy",
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"allwinner,sun5i-a13-usb-phy" or "allwinner,sun7i-a20-usb-phy"
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- compatible : should be one of
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* allwinner,sun4i-a10-usb-phy
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* allwinner,sun5i-a13-usb-phy
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* allwinner,sun6i-a31-usb-phy
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* allwinner,sun7i-a20-usb-phy
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- reg : a list of offset + length pairs
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- reg-names : "phy_ctrl", "pmu1" and for sun4i or sun7i "pmu2"
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- reg-names :
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* "phy_ctrl"
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* "pmu1"
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* "pmu2" for sun4i, sun6i or sun7i
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- #phy-cells : from the generic phy bindings, must be 1
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- clocks : phandle + clock specifier for the phy clock
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- clock-names : "usb_phy"
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- clocks : phandle + clock specifier for the phy clocks
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- clock-names :
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* "usb_phy" for sun4i, sun5i or sun7i
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* "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i
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- resets : a list of phandle + reset specifier pairs
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- reset-names : "usb0_reset", "usb1_reset" and for sun4i or sun7i "usb2_reset"
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- reset-names :
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* "usb0_reset"
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* "usb1_reset"
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* "usb2_reset" for sun4i, sun6i or sun7i
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Example:
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usbphy: phy@0x01c13400 {
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@ -32,6 +32,11 @@ Required properties:
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- reg : Address and length of the register set for the device.
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- #phy-cells: determine the number of cells that should be given in the
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phandle while referencing this phy.
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- clocks: a list of phandles and clock-specifier pairs, one for each entry in
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clock-names.
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- clock-names: should include:
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* "wkupclk" - wakeup clock.
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* "refclk" - reference clock (optional).
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Optional properties:
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- ctrl-module : phandle of the control module used by PHY driver to power on
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@ -44,6 +49,8 @@ usb2phy@4a0ad080 {
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reg = <0x4a0ad080 0x58>;
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ctrl-module = <&omap_control_usb>;
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#phy-cells = <0>;
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clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
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clock-names = "wkupclk", "refclk";
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};
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TI PIPE3 PHY
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17
Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt
Normal file
17
Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt
Normal file
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@ -0,0 +1,17 @@
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Qualcomm CI13xxx (Chipidea) USB controllers
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Required properties:
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- compatible: should contain "qcom,ci-hdrc"
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- reg: offset and length of the register set in the memory map
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- interrupts: interrupt-specifier for the controller interrupt.
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- usb-phy: phandle for the PHY device
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- dr_mode: Should be "peripheral"
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Examples:
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gadget@f9a55000 {
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compatible = "qcom,ci-hdrc";
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reg = <0xf9a55000 0x400>;
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dr_mode = "peripheral";
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interrupts = <0 134 0>;
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usb-phy = <&usbphy0>;
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};
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@ -6,6 +6,11 @@ Required properties:
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region.
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- interrupts: The EHCI interrupt
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Optional properties:
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- clocks: reference to the clock
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- phys: reference to the USB PHY
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- phy-names: name of the USB PHY, should be "usb"
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Example:
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ehci@50000 {
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@ -12,6 +12,13 @@ Required properties:
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- interrupts: interrupt number to the cpu.
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- clocks: from common clock binding: handle to usb clock.
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- clock-names: from common clock binding: Shall be "usbhost".
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- port: if in the SoC there are EHCI phys, they should be listed here.
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One phy per port. Each port should have following entries:
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- reg: port number on EHCI controller, e.g
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On Exynos5250, port 0 is USB2.0 otg phy
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port 1 is HSIC phy0
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port 2 is HSIC phy1
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- phys: from the *Generic PHY* bindings; specifying phy used by port.
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Optional properties:
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- samsung,vbus-gpio: if present, specifies the GPIO that
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@ -27,6 +34,14 @@ Example:
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clocks = <&clock 285>;
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clock-names = "usbhost";
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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phys = <&usb2phy 1>;
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status = "disabled";
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};
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};
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OHCI
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@ -38,6 +53,13 @@ Required properties:
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- interrupts: interrupt number to the cpu.
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- clocks: from common clock binding: handle to usb clock.
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- clock-names: from common clock binding: Shall be "usbhost".
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- port: if in the SoC there are OHCI phys, they should be listed here.
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One phy per port. Each port should have following entries:
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- reg: port number on OHCI controller, e.g
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On Exynos5250, port 0 is USB2.0 otg phy
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port 1 is HSIC phy0
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port 2 is HSIC phy1
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- phys: from the *Generic PHY* bindings, specifying phy used by port.
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Example:
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usb@12120000 {
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@ -47,6 +69,15 @@ Example:
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clocks = <&clock 285>;
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clock-names = "usbhost";
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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phys = <&usb2phy 1>;
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status = "disabled";
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};
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};
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DWC3
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@ -12,17 +12,23 @@ Required properties:
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- reg : Address and length of the register set for the device
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- interrupts : Interrupt numbers for this device
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- interrupts : Interrupt numbers for this device. Either one interrupt number
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for all interrupts, or one for status related interrupts, one for IN
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endpoint related interrupts and one for OUT endpoint related interrupts.
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Optional properties:
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- epobufsizes : An array of buffer sizes for OUT endpoints. If the property is
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not present, or for endpoints outside of the array, 1024 is assumed by
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the driver.
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- epobufsizes : Array of buffer sizes for OUT endpoints when they differ
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from the default size of 1024. The array is indexed by the OUT endpoint
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number. If the property is present it typically contains one entry for
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each OUT endpoint of the core. Fewer entries overrides the default sizes
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only for as many endpoints as the array contains.
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- epibufsizes : An array of buffer sizes for IN endpoints. If the property is
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not present, or for endpoints outside of the array, 1024 is assumed by
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the driver.
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- epibufsizes : Array of buffer sizes for IN endpoints when they differ
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from the default size of 1024. The array is indexed by the IN endpoint
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number. If the property is present it typically contains one entry for
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each IN endpoint of the core. Fewer entries overrides the default sizes
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only for as many endpoints as the array contains.
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For further information look in the documentation for the GLIB IP core library:
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http://www.gaisler.com/products/grlib/grip.pdf
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@ -15,3 +15,81 @@ Example EHCI controller device node:
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usb-phy = <&usb_otg>;
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};
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USB PHY with optional OTG:
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Required properties:
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- compatible: Should contain:
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"qcom,usb-otg-ci" for chipsets with ChipIdea 45nm PHY
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"qcom,usb-otg-snps" for chipsets with Synopsys 28nm PHY
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- regs: Offset and length of the register set in the memory map
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- interrupts: interrupt-specifier for the OTG interrupt.
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- clocks: A list of phandle + clock-specifier pairs for the
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clocks listed in clock-names
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- clock-names: Should contain the following:
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"phy" USB PHY reference clock
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"core" Protocol engine clock
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"iface" Interface bus clock
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"alt_core" Protocol engine clock for targets with asynchronous
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reset methodology. (optional)
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- vdccx-supply: phandle to the regulator for the vdd supply for
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digital circuit operation.
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- v1p8-supply: phandle to the regulator for the 1.8V supply
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- v3p3-supply: phandle to the regulator for the 3.3V supply
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- resets: A list of phandle + reset-specifier pairs for the
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resets listed in reset-names
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- reset-names: Should contain the following:
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"phy" USB PHY controller reset
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"link" USB LINK controller reset
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- qcom,otg-control: OTG control (VBUS and ID notifications) can be one of
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1 - PHY control
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2 - PMIC control
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Optional properties:
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- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
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- qcom,phy-init-sequence: PHY configuration sequence values. This is related to Device
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Mode Eye Diagram test. Start address at which these values will be
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written is ULPI_EXT_VENDOR_SPECIFIC. Value of -1 is reserved as
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"do not overwrite default value at this address".
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For example: qcom,phy-init-sequence = < -1 0x63 >;
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Will update only value at address ULPI_EXT_VENDOR_SPECIFIC + 1.
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- qcom,phy-num: Select number of pyco-phy to use, can be one of
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0 - PHY one, default
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1 - Second PHY
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Some platforms may have configuration to allow USB
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controller work with any of the two HSPHYs present.
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- qcom,vdd-levels: This property must be a list of three integer values
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(no, min, max) where each value represents either a voltage
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in microvolts or a value corresponding to voltage corner.
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Example HSUSB OTG controller device node:
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usb@f9a55000 {
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compatible = "qcom,usb-otg-snps";
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reg = <0xf9a55000 0x400>;
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interrupts = <0 134 0>;
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dr_mode = "peripheral";
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clocks = <&gcc GCC_XO_CLK>, <&gcc GCC_USB_HS_SYSTEM_CLK>,
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<&gcc GCC_USB_HS_AHB_CLK>;
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clock-names = "phy", "core", "iface";
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vddcx-supply = <&pm8841_s2_corner>;
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v1p8-supply = <&pm8941_l6>;
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v3p3-supply = <&pm8941_l24>;
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resets = <&gcc GCC_USB2A_PHY_BCR>, <&gcc GCC_USB_HS_BCR>;
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reset-names = "phy", "link";
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qcom,otg-control = <1>;
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qcom,phy-init-sequence = < -1 0x63 >;
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qcom,vdd-levels = <1 5 7>;
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};
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@ -15,6 +15,7 @@ Optional properties:
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- clocks : a list of phandle + clock specifier pairs
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- phys : phandle + phy specifier pair
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- phy-names : "usb"
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- resets : phandle + reset specifier pair
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Example (Sequoia 440EPx):
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ehci@e0000300 {
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|
|
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@ -12,6 +12,7 @@ Optional properties:
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- clocks : a list of phandle + clock specifier pairs
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- phys : phandle + phy specifier pair
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- phy-names : "usb"
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- resets : phandle + reset specifier pair
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||||
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Example:
|
||||
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||||
|
|
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@ -1,11 +1,17 @@
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USB xHCI controllers
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||||
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Required properties:
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||||
- compatible: should be "generic-xhci" (deprecated: "xhci-platform").
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- compatible: should be one of "generic-xhci",
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"marvell,armada-375-xhci", "marvell,armada-380-xhci",
|
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"renesas,xhci-r8a7790", "renesas,xhci-r8a7791" (deprecated:
|
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"xhci-platform").
|
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- reg: should contain address and length of the standard XHCI
|
||||
register set for the device.
|
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- interrupts: one XHCI interrupt should be described here.
|
||||
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||||
Optional property:
|
||||
- clocks: reference to a clock
|
||||
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||||
Example:
|
||||
usb@f0931000 {
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compatible = "generic-xhci";
|
||||
|
|
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|||
|
|
@ -15,6 +15,14 @@ Optional properties:
|
|||
- reset-gpios: Should specify GPIO for reset.
|
||||
- initial-mode: Should specify initial mode.
|
||||
(1 for HUB mode, 2 for STANDBY mode)
|
||||
- refclk: Clock used for driving REFCLK signal (optional, if not provided
|
||||
the driver assumes that clock signal is always available, its
|
||||
rate is specified by REF_SEL pins and a value from the primary
|
||||
reference clock frequencies table is used)
|
||||
- refclk-frequency: Frequency of the REFCLK signal as defined by REF_SEL
|
||||
pins (optional, if not provided, driver will not set rate of the
|
||||
REFCLK signal and assume that a value from the primary reference
|
||||
clock frequencies table is used)
|
||||
|
||||
Examples:
|
||||
usb3503@08 {
|
||||
|
|
|
|||
Loading…
Reference in a new issue