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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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i3c: i3c-master-msm-geni: Propagate tip changes from 4.19
Changes are to propagate the tip changes of 4.19 to 5.4 kernel
'commit 137b5f5720ba ("i3c: i3c-master-qcom-geni: Support for
OD,PUSH-PULL mode frequency switch")'.
'commit a7d29dd6723b ("i3c: i3c-master-qcom-geni: Support for
static address zero")'.
Change-Id: I40ed219bc9b099e095595e8a0f777bc0d3ae6df6
Signed-off-by: Subramanian Ananthanarayanan <skananth@codeaurora.org>
This commit is contained in:
Subramanian Ananthanarayanan
parent
0dbcf5d8eb
commit
e5e857aef6
1 changed files with 82 additions and 38 deletions
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk.h>
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@ -199,12 +199,18 @@ enum geni_i3c_err_code {
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#define TLMM_I3C_MODE 0x24
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#define IBI_SW_RESET_MIN_SLEEP 1000
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#define IBI_SW_RESET_MAX_SLEEP 2000
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#define I3C_OD_CLK_RATE 370000
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enum i3c_trans_dir {
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WRITE_TRANSACTION = 0,
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READ_TRANSACTION = 1
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};
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enum i3c_bus_phase {
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OPEN_DRAIN_MODE = 0,
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PUSH_PULL_MODE = 1
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};
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struct geni_se {
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void __iomem *base;
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void __iomem *ibi_base;
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@ -262,6 +268,7 @@ struct geni_i3c_dev {
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int cur_idx;
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unsigned long newaddrslots[(I3C_ADDR_MASK + 1) / BITS_PER_LONG];
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const struct geni_i3c_clk_fld *clk_fld;
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const struct geni_i3c_clk_fld *clk_od_fld;
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struct geni_ibi ibi;
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};
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@ -302,9 +309,9 @@ struct geni_i3c_clk_fld {
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u8 clk_div;
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u8 i2c_t_high_cnt;
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u8 i2c_t_low_cnt;
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u8 i2c_t_cycle_cnt;
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u8 i3c_t_high_cnt;
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u8 i3c_t_cycle_cnt;
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u32 i2c_t_cycle_cnt;
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};
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static struct geni_i3c_dev*
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@ -332,11 +339,12 @@ to_geni_i3c_master(struct i3c_master_controller *master)
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* clk_freq_out = t / t_cycle
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*/
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static const struct geni_i3c_clk_fld geni_i3c_clk_map[] = {
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{ KHZ(100), 19200, 7, 10, 11, 26, 0, 0 },
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{ KHZ(400), 19200, 2, 5, 12, 24, 0, 0 },
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{ KHZ(1000), 19200, 1, 3, 9, 18, 7, 0 },
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{ KHZ(1920), 19200, 1, 4, 9, 19, 7, 8 },
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{ KHZ(12500), 100000, 1, 60, 140, 250, 8, 16 },
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{ KHZ(100), 19200, 7, 10, 11, 0, 0, 26},
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{ KHZ(400), 19200, 2, 5, 12, 0, 0, 24},
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{ KHZ(1000), 19200, 1, 3, 9, 7, 0, 18},
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{ KHZ(1920), 19200, 1, 4, 9, 7, 8, 19},
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{ KHZ(370), 100000, 20, 4, 7, 8, 14, 14},
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{ KHZ(12500), 100000, 1, 72, 168, 6, 7, 300},
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};
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static int geni_i3c_clk_map_idx(struct geni_i3c_dev *gi3c)
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@ -351,11 +359,19 @@ static int geni_i3c_clk_map_idx(struct geni_i3c_dev *gi3c)
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itr->clk_freq_out == bus->scl_rate.i3c) &&
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KHZ(itr->clk_src_freq) == gi3c->clk_src_freq) {
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gi3c->clk_fld = itr;
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return 0;
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}
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if (itr->clk_freq_out == I3C_OD_CLK_RATE)
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gi3c->clk_od_fld = itr;
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}
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return -EINVAL;
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if ((!gi3c->clk_fld) || (!gi3c->clk_od_fld)) {
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GENI_SE_ERR(gi3c->ipcl, true, gi3c->se.dev,
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"%s : clk mapping failed", __func__);
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return -EINVAL;
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}
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return 0;
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}
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static void set_new_addr_slot(unsigned long *addrslot, u8 addr)
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@ -391,13 +407,17 @@ static bool is_new_addr_slot_set(unsigned long *addrslot, u8 addr)
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return ((*ptr & (1 << (addr % BITS_PER_LONG))) != 0);
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}
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static void qcom_geni_i3c_conf(struct geni_i3c_dev *gi3c)
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static void qcom_geni_i3c_conf(struct geni_i3c_dev *gi3c,
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enum i3c_bus_phase bus_phase)
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{
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const struct geni_i3c_clk_fld *itr = gi3c->clk_fld;
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u32 val;
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unsigned long freq;
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int ret = 0;
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if (bus_phase == OPEN_DRAIN_MODE)
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itr = gi3c->clk_od_fld;
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if (gi3c->dfs_idx > DFS_INDEX_MAX)
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ret = geni_se_clk_freq_match(&gi3c->se.i3c_rsc,
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KHZ(itr->clk_src_freq),
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@ -673,8 +693,6 @@ static int i3c_geni_runtime_get_mutex_lock(struct geni_i3c_dev *gi3c)
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return ret;
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}
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qcom_geni_i3c_conf(gi3c);
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return 0; /* return 0 to indicate SUCCESS */
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}
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@ -805,18 +823,14 @@ static int i3c_geni_execute_write_command(struct geni_i3c_dev *gi3c,
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static void geni_i3c_perform_daa(struct geni_i3c_dev *gi3c)
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{
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struct i3c_master_controller *m = &gi3c->ctrlr;
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struct i3c_bus *bus = i3c_master_get_bus(m);
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u8 last_dyn_addr = 0;
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int ret;
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while (1) {
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u8 rx_buf[8], tx_buf[8];
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struct i3c_xfer_params xfer = { FIFO_MODE };
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struct i3c_device_info info = { 0 };
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struct i3c_dev_desc *i3cdev;
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bool new_device = true;
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struct i3c_dev_boardinfo *i3cboardinfo;
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u64 pid;
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u8 bcr, dcr, addr;
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u8 bcr, dcr, init_dyn_addr = 0, addr = 0;
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GENI_SE_DBG(gi3c->ipcl, false, gi3c->se.dev,
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"i3c entdaa read\n");
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@ -838,31 +852,38 @@ static void geni_i3c_perform_daa(struct geni_i3c_dev *gi3c)
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((u64)rx_buf[4] << 8) |
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((u64)rx_buf[5]);
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i3c_bus_for_each_i3cdev(bus, i3cdev) {
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if (!i3cdev->dev)
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continue;
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i3c_device_get_info(i3cdev->dev, &info);
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if (pid == info.pid &&
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dcr == info.dcr &&
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bcr == info.bcr) {
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new_device = false;
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addr = (info.dyn_addr) ? info.dyn_addr :
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info.static_addr;
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list_for_each_entry(i3cboardinfo, &m->boardinfo.i3c, node) {
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if (pid == i3cboardinfo->pid) {
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GENI_SE_DBG(gi3c->ipcl, false, gi3c->se.dev,
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"PID %p matched with boardinfo\n", pid);
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break;
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}
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}
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if (new_device) {
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ret = i3c_master_get_free_addr(m,
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last_dyn_addr + 1);
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if (ret < 0)
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goto daa_err;
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addr = last_dyn_addr = (u8)ret;
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set_new_addr_slot(gi3c->newaddrslots, addr);
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if (i3cboardinfo)
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addr = init_dyn_addr = i3cboardinfo->init_dyn_addr;
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addr = ret = i3c_master_get_free_addr(m, addr);
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if (ret < 0) {
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GENI_SE_DBG(gi3c->ipcl, false, gi3c->se.dev,
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"error during get_free_addr ret:%d for pid:%p\n"
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, ret, pid);
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goto daa_err;
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} else if (ret == init_dyn_addr) {
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GENI_SE_DBG(gi3c->ipcl, false, gi3c->se.dev,
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"assigning requested addr:%p for pid:%p\n"
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, ret, pid);
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} else if (init_dyn_addr) {
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GENI_SE_DBG(gi3c->ipcl, false, gi3c->se.dev,
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"Can't assign req addr:%p for pid:%p assigning avl addr:%p\n"
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, init_dyn_addr, pid, addr);
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} else {
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GENI_SE_DBG(gi3c->ipcl, false, gi3c->se.dev,
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"assigning addr:%p for pid:%p\n", ret, pid);
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}
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set_new_addr_slot(gi3c->newaddrslots, addr);
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tx_buf[0] = (addr & I3C_ADDR_MASK) << 1;
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tx_buf[0] |= ~(hweight8(addr & I3C_ADDR_MASK) & 1);
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@ -907,6 +928,8 @@ static int geni_i3c_master_send_ccc_cmd(struct i3c_master_controller *m,
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if (ret)
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return ret;
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qcom_geni_i3c_conf(gi3c, OPEN_DRAIN_MODE);
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for (i = 0; i < cmd->ndests; i++) {
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int stall = (i < (cmd->ndests - 1)) ||
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(cmd->id == I3C_CCC_ENTDAA);
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@ -980,6 +1003,8 @@ static int geni_i3c_master_priv_xfers(struct i3c_dev_desc *dev,
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if (ret)
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return ret;
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qcom_geni_i3c_conf(gi3c, PUSH_PULL_MODE);
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for (i = 0; i < nxfers; i++) {
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bool stall = (i < (nxfers - 1));
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struct i3c_xfer_params xfer = { FIFO_MODE };
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@ -1027,6 +1052,8 @@ static int geni_i3c_master_i2c_xfers(struct i2c_dev_desc *dev,
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if (ret)
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return ret;
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qcom_geni_i3c_conf(gi3c, PUSH_PULL_MODE);
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GENI_SE_DBG(gi3c->ipcl, false, gi3c->se.dev,
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"i2c xfer:num:%d, msgs:len:%d,flg:%d\n",
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num, msgs[0].len, msgs[0].flags);
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@ -1087,6 +1114,7 @@ static int geni_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
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struct i3c_master_controller *m = i3c_dev_get_master(dev);
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struct geni_i3c_dev *gi3c = to_geni_i3c_master(m);
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struct geni_i3c_i2c_dev_data *data;
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struct i3c_dev_boardinfo *i3cboardinfo;
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data = devm_kzalloc(gi3c->se.dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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@ -1094,6 +1122,12 @@ static int geni_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
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data->ibi = -1;
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i3c_dev_set_master_data(dev, data);
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if (!dev->boardinfo) {
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list_for_each_entry(i3cboardinfo, &m->boardinfo.i3c, node) {
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if (dev->info.pid == i3cboardinfo->pid)
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dev->boardinfo = i3cboardinfo;
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}
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}
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return 0;
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}
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@ -1101,6 +1135,16 @@ static int geni_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
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static int geni_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
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u8 old_dyn_addr)
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{
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struct i3c_master_controller *m = i3c_dev_get_master(dev);
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struct i3c_dev_boardinfo *i3cboardinfo;
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if (!dev->boardinfo) {
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list_for_each_entry(i3cboardinfo, &m->boardinfo.i3c, node) {
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if (dev->info.pid == i3cboardinfo->pid)
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dev->boardinfo = i3cboardinfo;
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}
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}
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return 0;
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}
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@ -1167,7 +1211,7 @@ static int geni_i3c_master_bus_init(struct i3c_master_controller *m)
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goto err_cleanup;
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}
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qcom_geni_i3c_conf(gi3c);
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qcom_geni_i3c_conf(gi3c, OPEN_DRAIN_MODE);
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/* Get an address for the master. */
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ret = i3c_master_get_free_addr(m, 0);
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