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disp:msm:dsi:add support to config dsi PHY Driver Strength

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Hardware team required to set ordered DSI driver strength for
different DSI PHY.

Add support to config DSI PHY driver strength from DTSI config.

Change-Id: I60c5ee335c897d3f20dde42114798c15576cf32e
Reviewed-on: https://gerrit.mot.com/1783170
SLTApproved: Slta Waiver
SME-Granted: SME Approvals Granted
Tested-by: Jira Key
Reviewed-by: Yeqing Wang <wangyq13@motorola.com>
Reviewed-by: Huosheng Liao <liaohs@motorola.com>
Reviewed-by: Shanshan Dai <daiss1@motorola.com>
Submit-Approved: Jira Key
This commit is contained in:
shuoyan 2020-10-23 15:09:53 +08:00 • committed by tongkun1
commit e63a7de99a
7 changed files with 82 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

1
msm/dsi/dsi_defs.h
View file

@ -638,6 +638,7 @@ struct dsi_display_mode_priv_info {
u32 dsi_transfer_time_us;
u64 clk_rate_hz;
u64 min_dsi_clk_hz;
u32 phy_drive_strength;
struct msm_display_topology topology;
struct msm_display_dsc_info dsc;

10
msm/dsi/dsi_display.c
View file

@ -5783,6 +5783,16 @@ static int dsi_display_set_mode_sub(struct dsi_display *display,
dsi_display_validate_dms_fps(display->panel->cur_mode, mode);
}
if (priv_info->phy_drive_strength) {
display_for_each_ctrl(i, display) {
ctrl = &display->ctrl[i];
rc = dsi_phy_set_drive_strength_params(ctrl->phy,
priv_info->phy_drive_strength);
if (rc)
DSI_ERR("Fail to add drive strength params\n");
}
}
if (priv_info->phy_timing_len) {
display_for_each_ctrl(i, display) {
ctrl = &display->ctrl[i];

28
msm/dsi/dsi_panel.c
View file

@ -2911,6 +2911,28 @@ error:
return rc;
}
static int dsi_panel_parse_phy_ldo(struct dsi_display_mode *mode,
struct dsi_parser_utils *utils)
{
u32 data;
int rc = 0;
struct dsi_display_mode_priv_info *priv_info;
if (!mode || !mode->priv_info)
return -EINVAL;
priv_info = mode->priv_info;
rc = utils->read_u32(utils->data,
"qcom,mdss-dsi-panel-phy-drive-strength", &data);
if (rc)
DSI_DEBUG("Unsupport to set Phy Driver Strength\n");
else
priv_info->phy_drive_strength = data;
return rc;
}
static int dsi_panel_parse_phy_timing(struct dsi_display_mode *mode,
struct dsi_parser_utils *utils)
{
@ -4744,6 +4766,12 @@ int dsi_panel_get_mode(struct dsi_panel *panel,
DSI_ERR(
"failed to parse panel jitter config, rc=%d\n", rc);
rc = dsi_panel_parse_phy_ldo(mode, utils);
if (rc) {
DSI_ERR(
"failed to parse panel phy ldo rc=%d\n", rc);
}
rc = dsi_panel_parse_phy_timing(mode, utils);
if (rc) {
DSI_ERR(

27
msm/dsi/dsi_phy.c
View file

@ -1114,6 +1114,32 @@ int dsi_phy_set_clk_freq(struct msm_dsi_phy *phy,
return 0;
}
/**
* dsi_phy_set_drive_strength_params - drive strength parameters for the panel
* @phy: DSI PHY handle
* @drive strength: array holding timing params.
*
* Return: error code.
*/
int dsi_phy_set_drive_strength_params(struct msm_dsi_phy *phy,
u32 drive_strength)
{
int rc = 0;
if (!phy || !drive_strength) {
DSI_PHY_ERR(phy, "Invalid params\n");
return -EINVAL;
}
mutex_lock(&phy->phy_lock);
phy->cfg.phy_drive_strength = drive_strength;
mutex_unlock(&phy->phy_lock);
return rc;
}
/**
* dsi_phy_set_timing_params() - timing parameters for the panel
* @phy: DSI PHY handle
@ -1147,7 +1173,6 @@ int dsi_phy_set_timing_params(struct msm_dsi_phy *phy,
if (phy->hw.ops.commit_phy_timing && commit)
phy->hw.ops.commit_phy_timing(&phy->hw, &phy->cfg.timing);
mutex_unlock(&phy->phy_lock);
return rc;
}

10
msm/dsi/dsi_phy.h
View file

@ -256,6 +256,16 @@ int dsi_phy_set_clamp_state(struct msm_dsi_phy *phy, bool enable);
int dsi_phy_set_clk_freq(struct msm_dsi_phy *phy,
struct link_clk_freq *clk_freq);
/**
* dsi_phy_set_drive_strength_params() - drive strength parameters for the panel
* @phy: DSI PHY handle
* @drive_strength: DSI PHY Drive Strength
*
* Return: error code.
*/
int dsi_phy_set_drive_strength_params(struct msm_dsi_phy *phy,
u32 drive_strength);
/**
* dsi_phy_set_timing_params() - timing parameters for the panel
* @phy: DSI PHY handle

2
msm/dsi/dsi_phy_hw.h
View file

@ -103,6 +103,7 @@ struct dsi_phy_per_lane_cfgs {
* @force_clk_lane_hs:Boolean whether to force clock lane in HS mode.
* @phy_type: Phy-type (Dphy/Cphy).
* @bit_clk_rate_hz: DSI bit clk rate in HZ.
* @drive_strength: DSI PHY drive strength.
*/
struct dsi_phy_cfg {
struct dsi_phy_per_lane_cfgs lanecfg;
@ -115,6 +116,7 @@ struct dsi_phy_cfg {
bool force_clk_lane_hs;
enum dsi_phy_type phy_type;
unsigned long bit_clk_rate_hz;
u32 phy_drive_strength;
};
struct dsi_phy_hw;

5
msm/dsi/dsi_phy_hw_v4_0.c
View file

@ -349,6 +349,11 @@ static void dsi_phy_hw_dphy_enable(struct dsi_phy_hw *phy,
glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c;
glbl_str_swi_cal_sel_ctrl = 0x00;
glbl_hstx_str_ctrl_0 = 0x88;
if (cfg->phy_drive_strength != glbl_hstx_str_ctrl_0) {
glbl_str_swi_cal_sel_ctrl = 0x03;
glbl_hstx_str_ctrl_0 = cfg->phy_drive_strength;
}
} else {
vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59;
glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00;