From e6489bd8f8e85db959ddf09eb1b7c5d88bb8829c Mon Sep 17 00:00:00 2001 From: Chris Lew Date: Tue, 6 Aug 2019 16:04:47 -0700 Subject: [PATCH] dt-bindings: arm: msm: Introduce qsee_ipc_irq_bridge bindings QSEE needs to occasionally send sideband signals to APPS userspace. The qsee_ipc_irq_bridge creates a device node for userspace to poll on and posts notifications about interrupt and ssr events to this node. Change-Id: Ia895a1c6e5a31b762d61fef034244f245e1113e6 --- bindings/arm/msm/qsee_ipc_irq_bridge.txt | 30 ++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 bindings/arm/msm/qsee_ipc_irq_bridge.txt diff --git a/bindings/arm/msm/qsee_ipc_irq_bridge.txt b/bindings/arm/msm/qsee_ipc_irq_bridge.txt new file mode 100644 index 000000000000..442ad52b4bf6 --- /dev/null +++ b/bindings/arm/msm/qsee_ipc_irq_bridge.txt @@ -0,0 +1,30 @@ +Qualcomm Technologies, Inc. Secure Execution Environment IPC Interrupt Bridge + +[Root level node] +Required properties: +-compatible : should be "qcom,qsee-ipc-irq-bridge"; + +[Second level nodes] +qcom,qsee-ipc-irq-subsystem +Required properties: +-qcom,dev-name: the bridge device name +-interrupt: IPC interrupt line from remote subsystem to QSEE +-label : The name of this subsystem. + +Required properties if interrupt type is IRQ_TYPE_LEVEL_HIGH[4]: +-qcom,rx-irq-clr : the register to clear the level triggered rx interrupt +-qcom,rx-irq-clr-mask : the bitmask to clear the rx interrupt + +Example: + + qcom,qsee_ipc_irq_bridge { + compatible = "qcom,qsee-ipc-irq-bridge"; + + qcom,qsee-ipc-irq-spss { + qcom,rx-irq-clr = <0x1d08008 0x4>; + qcom,rx-irq-clr-mask = <0x2>; + qcom,dev-name = "qsee_ipc_irq_spss"; + interrupts = <0 349 4>; + label = "spss"; + }; + };