mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 02:32:09 -04:00
MMC core:
- Add support for Marvell SD8787 Wifi/BT chip - Improve UHS support for SDIO - Invent MMC_CAP_3_3V_DDR and a DT binding for eMMC DDR 3.3V mode - Detect Auto BKOPS enable bit - Export eMMC device lifetime information through sysfs - First take to slim down the public mmc headers to avoid abuse - Re-factoring of the mmc block device driver to prepare for blkmq - Cleanup code for the mmc block device driver - Clarify and cleanup code dealing with data requests - Cleanup some code by converting to ida_simple_ functions - Cleanup code dealing with card quirks - Cleanup private and public mmc header files MMC host: - Don't rely on public mmc headers to include non-mmc related headers - meson: Add support for eMMC HS400 mode - meson: Various cleanups and improvements - omap_hsmmc: Use the proper provided busy timeout from the core - sunxi: Enable new timings for the A64 MMC controllers - sunxi: Improvements for clock management - tmio: Improvements for SDIO interrupts - mxs-mmc: Add CMD23 support - sdhci-msm: Enable HS400 enhanced strobe mode support - sdhci-msm: Correct HS400 tuning sequence - sdhci-acpi: Support deferred probe - sdhci-pci: Add support for eMMC HS200 tuning mode on AMD - mediatek: Correct the implementation of card busy detection - dw_mmc: Initial support for ZX mmc controller - sh_mobile_sdhi: Enable support for eMMC HS200 mode - sh_mmcif: Various cleanups and improvements -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYrC2eAAoJEP4mhCVzWIwpDvYP/j4qMa5uSGOuxrHPorAq1Hru VP11zZGx5iZGFJOrSulDq/El4wnaZFH8ceol3QXvw9ss6YZMFrIdwWVaZxTISFrb Vn84w0lebo7ZWSWsdaMzPowuJVzsqeEwUKH5it1jyp5WnWUAzA6h1wSkwwh8djl5 i05/iHGuOcwMCITvSryqUIGaMZnuXnc6NWIJXaYlL3BQPhaSaxWnkHupGTYzgDtU 8Xkm401iXShKZLCUzuMLZShFIJ2qvnGNmSbMpt9f1VdMvDmKmSJVfs/Tzfyn/E+R 5DEUl/BPgyTx7bbUa45V0gRqbQGqQXACbhaPBcjy8BQn0gH60MjuKxWxM9kUM0Mu 8wa5A73Qo7sFoySCLPtDtOopzozop9No3UWeTv/V1ezzXra52P0oB4gp86Ys6x5G 7GcsmqJ+Km/xMNNP8sS2WQv5l9zFM7dv6+JRxNrBsb1dk5c5pio/RKN8KQ1Wqo/N /p+iCsEi+4iKrpms5ImIpEF1hfEyJtt/wAL0rKE4NhuR8xRhO+EBGj73smrHJVgO JvDkFMlo9ZeE5aj1kmYYTdUcrIK5DRFSPdNWTs7T1B6XeZ8ePcTQxVwXcV01amWM zvx8fIGMm14M774pe85B0kmgki85XQFk0D6j3z8ElWA2QygOZlOdaSviJIZSh4jX aj85sRSJ6EVWJl17GggW =Iv7W -----END PGP SIGNATURE----- Merge tag 'mmc-v4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc Pull MMC updates from Ulf Hansson: "MMC core: - Add support for Marvell SD8787 Wifi/BT chip - Improve UHS support for SDIO - Invent MMC_CAP_3_3V_DDR and a DT binding for eMMC DDR 3.3V mode - Detect Auto BKOPS enable bit - Export eMMC device lifetime information through sysfs - First take to slim down the public mmc headers to avoid abuse - Re-factoring of the mmc block device driver to prepare for blkmq - Cleanup code for the mmc block device driver - Clarify and cleanup code dealing with data requests - Cleanup some code by converting to ida_simple_ functions - Cleanup code dealing with card quirks - Cleanup private and public mmc header files MMC host: - Don't rely on public mmc headers to include non-mmc related headers - meson: Add support for eMMC HS400 mode - meson: Various cleanups and improvements - omap_hsmmc: Use the proper provided busy timeout from the core - sunxi: Enable new timings for the A64 MMC controllers - sunxi: Improvements for clock management - tmio: Improvements for SDIO interrupts - mxs-mmc: Add CMD23 support - sdhci-msm: Enable HS400 enhanced strobe mode support - sdhci-msm: Correct HS400 tuning sequence - sdhci-acpi: Support deferred probe - sdhci-pci: Add support for eMMC HS200 tuning mode on AMD - mediatek: Correct the implementation of card busy detection - dw_mmc: Initial support for ZX mmc controller - sh_mobile_sdhi: Enable support for eMMC HS200 mode - sh_mmcif: Various cleanups and improvements" * tag 'mmc-v4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (145 commits) mmc: core: add mmc prefix for blk_fixups mmc: core: move all quirks together into quirks.h mmc: core: improve the quirks for sdio devices mmc: core: move some sdio IDs out of quirks file mmc: core: change quirks.c to be a header file mmc: sdhci-cadence: fix bit shift of read data from PHY port mmc: Adding AUTO_BKOPS_EN bit set for Auto BKOPS support mmc: MAN_BKOPS_EN inverse debug message logic mmc: meson-gx: add support for HS400 mode mmc: meson-gx: remove unneeded checks in remove mmc: meson-gx: reduce bounce buffer size mmc: meson-gx: set max block count and request size mmc: meson-gx: improve interrupt handling mmc: meson-gx: improve meson_mmc_irq_thread mmc: meson-gx: improve meson_mmc_clk_set mmc: meson-gx: minor improvements in meson_mmc_set_ios mmc: meson: Assign the minimum clk rate as close to 400KHz as possible mmc: core: start to break apart mmc_start_areq() mmc: block: respect bool returned from blk_end_request() mmc: block: return errorcode from mmc_sd_num_wr_blocks() ...
This commit is contained in:
Linus Torvalds
commit
e67bd12d60
114 changed files with 2591 additions and 1818 deletions
|
|
@ -17,7 +17,7 @@ Required properties:
|
|||
"core" - Main peripheral bus clock
|
||||
"clkin0" - Parent clock of internal mux
|
||||
"clkin1" - Other parent clock of internal mux
|
||||
The driver has an interal mux clock which switches between clkin0 and clkin1 depending on the
|
||||
The driver has an internal mux clock which switches between clkin0 and clkin1 depending on the
|
||||
clock rate requested by the MMC core.
|
||||
|
||||
Example:
|
||||
|
|
|
|||
16
Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.txt
Normal file
16
Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.txt
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
* Marvell SD8787 power sequence provider
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "mmc-pwrseq-sd8787".
|
||||
- powerdown-gpios: contains a power down GPIO specifier with the
|
||||
default active state
|
||||
- reset-gpios: contains a reset GPIO specifier with the default
|
||||
active state
|
||||
|
||||
Example:
|
||||
|
||||
wifi_pwrseq: wifi_pwrseq {
|
||||
compatible = "mmc-pwrseq-sd8787";
|
||||
powerdown-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
|
||||
reset-gpios = <&twl_gpio 1 GPIO_ACTIVE_LOW>;
|
||||
}
|
||||
|
|
@ -40,6 +40,7 @@ Optional properties:
|
|||
- cap-mmc-hw-reset: eMMC hardware reset is supported
|
||||
- cap-sdio-irq: enable SDIO IRQ signalling on this interface
|
||||
- full-pwr-cycle: full power cycle of the card is supported
|
||||
- mmc-ddr-3_3v: eMMC high-speed DDR mode(3.3V I/O) is supported
|
||||
- mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported
|
||||
- mmc-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported
|
||||
- mmc-hs200-1_8v: eMMC HS200 mode(1.8V I/O) is supported
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ Optional properties:
|
|||
- bus-width: Number of data lines.
|
||||
See: Documentation/devicetree/bindings/mmc/mmc.txt.
|
||||
|
||||
- max-frequency: Can be 200MHz, 100Mz or 50MHz (default) and used for
|
||||
- max-frequency: Can be 200MHz, 100MHz or 50MHz (default) and used for
|
||||
configuring the CCONFIG3 in the mmcss.
|
||||
See: Documentation/devicetree/bindings/mmc/mmc.txt.
|
||||
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ host controllers refer to the mmc[1] bindings.
|
|||
|
||||
Optional properties:
|
||||
- sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit
|
||||
property corresponds to the bits in the sdhci capabilty register. If the bit
|
||||
property corresponds to the bits in the sdhci capability register. If the bit
|
||||
is on in the mask then the bit is incorrect in the register and should be
|
||||
turned off, before applying sdhci-caps.
|
||||
- sdhci-caps: The sdhci capabilities register is incorrect. This 64bit
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@ Required properties:
|
|||
* "allwinner,sun5i-a13-mmc"
|
||||
* "allwinner,sun7i-a20-mmc"
|
||||
* "allwinner,sun9i-a80-mmc"
|
||||
* "allwinner,sun50i-a64-emmc"
|
||||
* "allwinner,sun50i-a64-mmc"
|
||||
- reg : mmc controller base registers
|
||||
- clocks : a list with 4 phandle + clock specifier pairs
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ Required Properties:
|
|||
each child-node representing a supported slot. There should be atleast one
|
||||
child node representing a card slot. The name of the child node representing
|
||||
the slot is recommended to be slot@n where n is the unique number of the slot
|
||||
connnected to the controller. The following are optional properties which
|
||||
connected to the controller. The following are optional properties which
|
||||
can be included in the slot child node.
|
||||
|
||||
* reg: specifies the physical slot number. The valid values of this
|
||||
|
|
@ -75,6 +75,17 @@ Optional properties:
|
|||
* card-detect-delay: Delay in milli-seconds before detecting card after card
|
||||
insert event. The default value is 0.
|
||||
|
||||
* data-addr: Override fifo address with value provided by DT. The default FIFO reg
|
||||
offset is assumed as 0x100 (version < 0x240A) and 0x200(version >= 0x240A) by
|
||||
driver. If the controller does not follow this rule, please use this property
|
||||
to set fifo address in device tree.
|
||||
|
||||
* fifo-watermark-aligned: Data done irq is expected if data length is less than
|
||||
watermark in PIO mode. But fifo watermark is requested to be aligned with data
|
||||
length in some SoC so that TX/RX irq can be generated with data done irq. Add this
|
||||
watermark quirk to mark this requirement and force fifo watermark setting
|
||||
accordingly.
|
||||
|
||||
* vmmc-supply: The phandle to the regulator to use for vmmc. If this is
|
||||
specified we'll defer probe until we can find this regulator.
|
||||
|
||||
|
|
@ -102,6 +113,8 @@ board specific portions as listed below.
|
|||
interrupts = <0 75 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
data-addr = <0x200>;
|
||||
fifo-watermark-aligned;
|
||||
resets = <&rst 20>;
|
||||
reset-names = "reset";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -25,6 +25,19 @@ Required properties:
|
|||
"renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
|
||||
"renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC
|
||||
|
||||
- clocks: Most controllers only have 1 clock source per channel. However, on
|
||||
some variations of this controller, the internal card detection
|
||||
logic that exists in this controller is sectioned off to be run by a
|
||||
separate second clock source to allow the main core clock to be turned
|
||||
off to save power.
|
||||
If 2 clocks are specified by the hardware, you must name them as
|
||||
"core" and "cd". If the controller only has 1 clock, naming is not
|
||||
required.
|
||||
Below is the number clocks for each supported SoC:
|
||||
1: SH73A0, R8A73A4, R8A7740, R8A7778, R8A7779, R8A7790
|
||||
R8A7791, R8A7792, R8A7793, R8A7794, R8A7795, R8A7796
|
||||
2: R7S72100
|
||||
|
||||
Optional properties:
|
||||
- toshiba,mmc-wrprotect-disable: write-protect detection is unavailable
|
||||
- pinctrl-names: should be "default", "state_uhs"
|
||||
|
|
|
|||
33
Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt
Normal file
33
Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
* ZTE specific extensions to the Synopsys Designware Mobile Storage
|
||||
Host Controller
|
||||
|
||||
The Synopsys designware mobile storage host controller is used to interface
|
||||
a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
|
||||
differences between the core Synopsys dw mshc controller properties described
|
||||
by synopsys-dw-mshc.txt and the properties used by the ZTE specific
|
||||
extensions to the Synopsys Designware Mobile Storage Host Controller.
|
||||
|
||||
Required Properties:
|
||||
|
||||
* compatible: should be
|
||||
- "zte,zx296718-dw-mshc": for ZX SoCs
|
||||
|
||||
Example:
|
||||
|
||||
mmc1: mmc@1110000 {
|
||||
compatible = "zte,zx296718-dw-mshc";
|
||||
reg = <0x01110000 0x1000>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
fifo-depth = <32>;
|
||||
data-addr = <0x200>;
|
||||
fifo-watermark-aligned;
|
||||
bus-width = <4>;
|
||||
clock-frequency = <50000000>;
|
||||
clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>;
|
||||
clock-names = "biu", "ciu";
|
||||
num-slots = <1>;
|
||||
max-frequency = <50000000>;
|
||||
cap-sdio-irq;
|
||||
cap-sd-highspeed;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
Marvell 8897/8997 (sd8897/sd8997/pcie8997) SDIO/PCIE devices
|
||||
Marvell 8787/8897/8997 (sd8787/sd8897/sd8997/pcie8997) SDIO/PCIE devices
|
||||
------
|
||||
|
||||
This node provides properties for controlling the Marvell SDIO/PCIE wireless device.
|
||||
|
|
@ -8,6 +8,7 @@ connects the device to the system.
|
|||
Required properties:
|
||||
|
||||
- compatible : should be one of the following:
|
||||
* "marvell,sd8787"
|
||||
* "marvell,sd8897"
|
||||
* "marvell,sd8997"
|
||||
* "pci11ab,2b42"
|
||||
|
|
@ -34,6 +35,9 @@ Optional properties:
|
|||
so that the wifi chip can wakeup host platform under certain condition.
|
||||
during system resume, the irq will be disabled to make sure
|
||||
unnecessary interrupt is not received.
|
||||
- vmmc-supply: a phandle of a regulator, supplying VCC to the card
|
||||
- mmc-pwrseq: phandle to the MMC power sequence node. See "mmc-pwrseq-*"
|
||||
for documentation of MMC power sequence bindings.
|
||||
|
||||
Example:
|
||||
|
||||
|
|
@ -46,6 +50,7 @@ so that firmware can wakeup host using this device side pin.
|
|||
&mmc3 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&wlan_en_reg>;
|
||||
mmc-pwrseq = <&wifi_pwrseq>;
|
||||
bus-width = <4>;
|
||||
cap-power-off-card;
|
||||
keep-power-in-suspend;
|
||||
|
|
|
|||
Loading…
Reference in a new issue