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clk: ingenic: Fix recalc_rate for clocks with fixed divider

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Previously, the clocks with a fixed divider would report their rate
as being the same as the one of their parent, independently of the
divider in use. This commit fixes this behaviour.

This went unnoticed as neither the jz4740 nor the jz4780 CGU code
have clocks with fixed dividers yet.

Signed-off-by: Paul Cercueil <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: Maarten ter Huurne <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/18477/
Signed-off-by: James Hogan <[email protected]>
This commit is contained in:
Paul Cercueil 2018-01-16 16:47:52 +01:00 • committed by James Hogan
commit e6cfa64375
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1 changed files with 2 additions and 0 deletions
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2
drivers/clk/ingenic/cgu.c
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@ -328,6 +328,8 @@ ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
div *= clk_info->div.div;
rate /= div;
} else if (clk_info->type & CGU_CLK_FIXDIV) {
rate /= clk_info->fixdiv.div;
}
return rate;