diff --git a/qcom/direwolf-pinctrl.dtsi b/qcom/direwolf-pinctrl.dtsi
index 8b7b9bd9baa8..e3fb955590ac 100644
--- a/qcom/direwolf-pinctrl.dtsi
+++ b/qcom/direwolf-pinctrl.dtsi
@@ -1 +1,1580 @@
-&tlmm { };
+&tlmm {
+	qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
+		qupv3_se0_i2c_active: qupv3_se0_i2c_active {
+			mux {
+				pins = "gpio135", "gpio136";
+				function = "qup0";
+			};
+
+			config {
+				pins = "gpio135", "gpio136";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
+			mux {
+				pins = "gpio135", "gpio136";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio135", "gpio136";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se0_spi_pins: qupv3_se0_spi_pins {
+		qupv3_se0_spi_active: qupv3_se0_spi_active {
+			mux {
+				pins = "gpio135", "gpio136",
+						"gpio137", "gpio138";
+				function = "qup0";
+			};
+
+			config {
+				pins = "gpio135", "gpio136",
+						"gpio137", "gpio138";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
+			mux {
+				pins = "gpio135", "gpio136",
+						"gpio137", "gpio138";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio135", "gpio136",
+						"gpio137", "gpio138";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
+		qupv3_se1_i2c_active: qupv3_se1_i2c_active {
+			mux {
+				pins = "gpio158", "gpio159";
+				function = "qup1";
+			};
+
+			config {
+				pins = "gpio158", "gpio159";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
+			mux {
+				pins = "gpio158", "gpio159";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio158", "gpio159";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se1_spi_pins: qupv3_se1_spi_pins {
+		qupv3_se1_spi_active: qupv3_se1_spi_active {
+			mux {
+				pins = "gpio158", "gpio159",
+						"gpio160", "gpio161";
+				function = "qup1";
+			};
+
+			config {
+				pins = "gpio158", "gpio159",
+						"gpio160", "gpio161";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
+			mux {
+				pins = "gpio158", "gpio159",
+						"gpio160", "gpio161";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio158", "gpio159",
+						"gpio160", "gpio161";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
+		qupv3_se2_i2c_active: qupv3_se2_i2c_active {
+			mux {
+				pins = "gpio121", "gpio122";
+				function = "qup2";
+			};
+
+			config {
+				pins = "gpio121", "gpio122";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
+			mux {
+				pins = "gpio121", "gpio122";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio121", "gpio122";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se2_spi_pins: qupv3_se2_spi_pins {
+		qupv3_se2_spi_active: qupv3_se2_spi_active {
+			mux {
+				pins = "gpio121", "gpio122",
+						"gpio123", "gpio124";
+				function = "qup2";
+			};
+
+			config {
+				pins = "gpio121", "gpio122",
+						"gpio123", "gpio124";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
+			mux {
+				pins = "gpio121", "gpio122",
+						"gpio123", "gpio124";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio121", "gpio122",
+						"gpio123", "gpio124";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se2_4uart_pins: qupv3_se2_4uart_pins {
+		qupv3_se2_default_cts:
+				qupv3_se2_default_cts {
+			mux {
+				pins = "gpio121";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio121";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se2_default_rtsrx:
+			qupv3_se2_default_rtsrx {
+			mux {
+				pins = "gpio122", "gpio124";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio122", "gpio124";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se2_default_tx:
+			qupv3_se2_default_tx {
+			mux {
+				pins = "gpio123";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio123";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se2_ctsrx: qupv3_se2_ctsrx {
+			mux {
+				pins = "gpio121", "gpio124";
+				function = "qup2";
+			};
+
+			config {
+				pins = "gpio121", "gpio124";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se2_rts: qupv3_se2_rts {
+			mux {
+				pins = "gpio122";
+				function = "qup2";
+			};
+
+			config {
+				pins = "gpio122";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se2_tx: qupv3_se2_tx {
+			mux {
+				pins = "gpio123";
+				function = "qup2";
+			};
+
+			config {
+				pins = "gpio123";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+	};
+
+	qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
+		qupv3_se3_i2c_active: qupv3_se3_i2c_active {
+			mux {
+				pins = "gpio137", "gpio138";
+				function = "qup3";
+			};
+
+			config {
+				pins = "gpio137", "gpio138";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
+			mux {
+				pins = "gpio137", "gpio138";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio137", "gpio138";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se3_spi_pins: qupv3_se3_spi_pins {
+		qupv3_se3_spi_active: qupv3_se3_spi_active {
+			mux {
+				pins = "gpio137", "gpio138",
+						"gpio135", "gpio136";
+				function = "qup3";
+			};
+
+			config {
+				pins = "gpio137", "gpio138",
+						"gpio135", "gpio136";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se3_spi_sleep: qupv3_se3_spi_sleep {
+			mux {
+				pins = "gpio137", "gpio138",
+						"gpio135", "gpio136";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio137", "gpio138",
+						"gpio135", "gpio136";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
+		qupv3_se4_i2c_active: qupv3_se4_i2c_active {
+			mux {
+				pins = "gpio171", "gpio172";
+				function = "qup4";
+			};
+
+			config {
+				pins = "gpio171", "gpio172";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
+			mux {
+				pins = "gpio171", "gpio172";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio171", "gpio172";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se4_spi_pins: qupv3_se4_spi_pins {
+		qupv3_se4_spi_active: qupv3_se4_spi_active {
+			mux {
+				pins = "gpio171", "gpio172",
+						"gpio173", "gpio174";
+				function = "qup4";
+			};
+
+			config {
+				pins = "gpio171", "gpio172",
+						"gpio173", "gpio174";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
+			mux {
+				pins = "gpio171", "gpio172",
+						"gpio173", "gpio174";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio171", "gpio172",
+						"gpio173", "gpio174";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
+		qupv3_se5_i2c_active: qupv3_se5_i2c_active {
+			mux {
+				pins = "gpio111", "gpio112";
+				function = "qup5";
+			};
+
+			config {
+				pins = "gpio111", "gpio112";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
+			mux {
+				pins = "gpio111", "gpio112";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio111", "gpio112";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se5_spi_pins: qupv3_se5_spi_pins {
+		qupv3_se5_spi_active: qupv3_se5_spi_active {
+			mux {
+				pins = "gpio111", "gpio112",
+						"gpio145", "gpio146";
+				function = "qup5";
+			};
+
+			config {
+				pins = "gpio111", "gpio112",
+						"gpio145", "gpio146";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
+			mux {
+				pins = "gpio111", "gpio112",
+						"gpio145", "gpio146";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio111", "gpio112",
+						"gpio145", "gpio146";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
+		qupv3_se6_i2c_active: qupv3_se6_i2c_active {
+			mux {
+				pins = "gpio154", "gpio155";
+				function = "qup6";
+			};
+
+			config {
+				pins = "gpio154", "gpio155";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
+			mux {
+				pins = "gpio154", "gpio155";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio154", "gpio155";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se6_spi_pins: qupv3_se6_spi_pins {
+		qupv3_se6_spi_active: qupv3_se6_spi_active {
+			mux {
+				pins = "gpio154", "gpio155",
+						"gpio156", "gpio157";
+				function = "qup6";
+			};
+
+			config {
+				pins = "gpio154", "gpio155",
+						"gpio156", "gpio157";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
+			mux {
+				pins = "gpio154", "gpio155",
+						"gpio156", "gpio157";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio154", "gpio155",
+						"gpio156", "gpio157";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se7_i2c_pins: qupv3_se7_i2c_pins {
+		qupv3_se7_i2c_active: qupv3_se7_i2c_active {
+			mux {
+				pins = "gpio128", "gpio129";
+				function = "qup7";
+			};
+
+			config {
+				pins = "gpio128", "gpio129";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep {
+			mux {
+				pins = "gpio128", "gpio129";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio128", "gpio129";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se7_spi_pins: qupv3_se7_spi_pins {
+		qupv3_se7_spi_active: qupv3_se7_spi_active {
+			mux {
+				pins = "gpio128", "gpio129",
+						"gpio125", "gpio126";
+				function = "qup7";
+			};
+
+			config {
+				pins = "gpio128", "gpio129",
+						"gpio125", "gpio126";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se7_spi_sleep: qupv3_se7_spi_sleep {
+			mux {
+				pins = "gpio128", "gpio129",
+						"gpio125", "gpio126";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio128", "gpio129",
+						"gpio125", "gpio126";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
+		qupv3_se8_i2c_active: qupv3_se8_i2c_active {
+			mux {
+				pins = "gpio43", "gpio44";
+				function = "qup8";
+			};
+
+			config {
+				pins = "gpio43", "gpio44";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
+			mux {
+				pins = "gpio43", "gpio44";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio43", "gpio44";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se8_spi_pins: qupv3_se8_spi_pins {
+		qupv3_se8_spi_active: qupv3_se8_spi_active {
+			mux {
+				pins = "gpio43", "gpio44",
+						"gpio45", "gpio46";
+				function = "qup8";
+			};
+
+			config {
+				pins = "gpio43", "gpio44",
+						"gpio45", "gpio46";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se8_spi_sleep: qupv3_se8_spi_sleep {
+			mux {
+				pins = "gpio43", "gpio44",
+						"gpio45", "gpio46";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio43", "gpio44",
+						"gpio45", "gpio46";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
+		qupv3_se9_i2c_active: qupv3_se9_i2c_active {
+			mux {
+				pins = "gpio41", "gpio42";
+				function = "qup9";
+			};
+
+			config {
+				pins = "gpio41", "gpio42";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
+			mux {
+				pins = "gpio41", "gpio42";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio41", "gpio42";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se9_spi_pins: qupv3_se9_spi_pins {
+		qupv3_se9_spi_active: qupv3_se9_spi_active {
+			mux {
+				pins = "gpio41", "gpio42",
+						"gpio43", "gpio44";
+				function = "qup9";
+			};
+
+			config {
+				pins = "gpio41", "gpio42",
+						"gpio43", "gpio44";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se9_spi_sleep: qupv3_se9_spi_sleep {
+			mux {
+				pins = "gpio41", "gpio42",
+						"gpio43", "gpio44";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio41", "gpio42",
+						"gpio43", "gpio44";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
+		qupv3_se10_i2c_active: qupv3_se10_i2c_active {
+			mux {
+				pins = "gpio22", "gpio23";
+				function = "qup10";
+			};
+
+			config {
+				pins = "gpio22", "gpio23";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
+			mux {
+				pins = "gpio22", "gpio23";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio22", "gpio23";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se10_spi_pins: qupv3_se10_spi_pins {
+		qupv3_se10_spi_active: qupv3_se10_spi_active {
+			mux {
+				pins = "gpio22", "gpio23",
+						"gpio24", "gpio25";
+				function = "qup10";
+			};
+
+			config {
+				pins = "gpio22", "gpio23",
+						"gpio24", "gpio25";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {
+			mux {
+				pins = "gpio22", "gpio23",
+						"gpio24", "gpio25";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio22", "gpio23",
+						"gpio24", "gpio25";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se11_i2c_pins: qupv3_se11_i2c_pins {
+		qupv3_se11_i2c_active: qupv3_se11_i2c_active {
+			mux {
+				pins = "gpio18", "gpio19";
+				function = "qup11";
+			};
+
+			config {
+				pins = "gpio18", "gpio19";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
+			mux {
+				pins = "gpio18", "gpio19";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio18", "gpio19";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se11_spi_pins: qupv3_se11_spi_pins {
+		qupv3_se11_spi_active: qupv3_se11_spi_active {
+			mux {
+				pins = "gpio18", "gpio19",
+						"gpio20", "gpio21";
+				function = "qup11";
+			};
+
+			config {
+				pins = "gpio18", "gpio19",
+						"gpio20", "gpio21";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se11_spi_sleep: qupv3_se11_spi_sleep {
+			mux {
+				pins = "gpio18", "gpio19",
+						"gpio20", "gpio21";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio18", "gpio19",
+						"gpio20", "gpio21";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se12_i2c_pins: qupv3_se12_i2c_pins {
+		qupv3_se12_i2c_active: qupv3_se12_i2c_active {
+			mux {
+				pins = "gpio0", "gpio1";
+				function = "qup12";
+			};
+
+			config {
+				pins = "gpio0", "gpio1";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep {
+			mux {
+				pins = "gpio0", "gpio1";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio0", "gpio1";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se12_spi_pins: qupv3_se12_spi_pins {
+		qupv3_se12_spi_active: qupv3_se12_spi_active {
+			mux {
+				pins = "gpio0", "gpio1",
+						"gpio2", "gpio3";
+				function = "qup12";
+			};
+
+			config {
+				pins = "gpio0", "gpio1",
+						"gpio2", "gpio3";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se12_spi_sleep: qupv3_se12_spi_sleep {
+			mux {
+				pins = "gpio0", "gpio1",
+						"gpio2", "gpio3";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio0", "gpio1",
+						"gpio2", "gpio3";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se13_i2c_pins: qupv3_se13_i2c_pins {
+		qupv3_se13_i2c_active: qupv3_se13_i2c_active {
+			mux {
+				pins = "gpio26", "gpio27";
+				function = "qup13";
+			};
+
+			config {
+				pins = "gpio26", "gpio27";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep {
+			mux {
+				pins = "gpio26", "gpio27";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio26", "gpio27";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se13_spi_pins: qupv3_se13_spi_pins {
+		qupv3_se13_spi_active: qupv3_se13_spi_active {
+			mux {
+				pins = "gpio26", "gpio27",
+						"gpio28", "gpio29";
+				function = "qup13";
+			};
+
+			config {
+				pins = "gpio26", "gpio27",
+						"gpio28", "gpio29";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se13_spi_sleep: qupv3_se13_spi_sleep {
+			mux {
+				pins = "gpio26", "gpio27",
+						"gpio28", "gpio29";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio26", "gpio27",
+						"gpio28", "gpio29";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se13_2uart_pins: qupv3_se13_2uart_pins {
+		qupv3_se13_2uart_active: qupv3_se13_2uart_active {
+			mux {
+				pins = "gpio28", "gpio29";
+				function = "qup13";
+			};
+
+			config {
+				pins = "gpio28", "gpio29";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se13_2uart_sleep: qupv3_se13_2uart_sleep {
+			mux {
+				pins = "gpio28", "gpio29";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio28", "gpio29";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+	};
+
+	qupv3_se14_i2c_pins: qupv3_se14_i2c_pins {
+		qupv3_se14_i2c_active: qupv3_se14_i2c_active {
+			mux {
+				pins = "gpio4", "gpio5";
+				function = "qup14";
+			};
+
+			config {
+				pins = "gpio4", "gpio5";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep {
+			mux {
+				pins = "gpio4", "gpio5";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio4", "gpio5";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se14_spi_pins: qupv3_se14_spi_pins {
+		qupv3_se14_spi_active: qupv3_se14_spi_active {
+			mux {
+				pins = "gpio4", "gpio5",
+						"gpio6", "gpio7";
+				function = "qup14";
+			};
+
+			config {
+				pins = "gpio4", "gpio5",
+						"gpio6", "gpio7";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se14_spi_sleep: qupv3_se14_spi_sleep {
+			mux {
+				pins = "gpio4", "gpio5",
+						"gpio6", "gpio7";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio4", "gpio5",
+						"gpio6", "gpio7";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se15_i2c_pins: qupv3_se15_i2c_pins {
+		qupv3_se15_i2c_active: qupv3_se15_i2c_active {
+			mux {
+				pins = "gpio36", "gpio37";
+				function = "qup15";
+			};
+
+			config {
+				pins = "gpio36", "gpio37";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep {
+			mux {
+				pins = "gpio36", "gpio37";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio36", "gpio37";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se15_spi_pins: qupv3_se15_spi_pins {
+		qupv3_se15_spi_active: qupv3_se15_spi_active {
+			mux {
+				pins = "gpio36", "gpio37",
+						"gpio38", "gpio39";
+				function = "qup15";
+			};
+
+			config {
+				pins = "gpio36", "gpio37",
+						"gpio38", "gpio39";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se15_spi_sleep: qupv3_se15_spi_sleep {
+			mux {
+				pins = "gpio36", "gpio37",
+						"gpio38", "gpio39";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio36", "gpio37",
+						"gpio38", "gpio39";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se17_2uart_pins: qupv3_se17_2uart_pins {
+		qupv3_se17_2uart_active: qupv3_se17_2uart_active {
+			mux {
+				pins = "gpio63", "gpio64";
+				function = "qup17";
+			};
+
+			config {
+				pins = "gpio63", "gpio64";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se17_2uart_sleep: qupv3_se17_2uart_sleep {
+			mux {
+				pins = "gpio63", "gpio64";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio63", "gpio64";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+	};
+
+	qupv3_se16_i2c_pins: qupv3_se16_i2c_pins {
+		qupv3_se16_i2c_active: qupv3_se16_i2c_active {
+			mux {
+				pins = "gpio70", "gpio71";
+				function = "qup16";
+			};
+
+			config {
+				pins = "gpio70", "gpio71";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se16_i2c_sleep: qupv3_se16_i2c_sleep {
+			mux {
+				pins = "gpio70", "gpio71";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio70", "gpio71";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se16_spi_pins: qupv3_se16_spi_pins {
+		qupv3_se16_spi_active: qupv3_se16_spi_active {
+			mux {
+				pins = "gpio70", "gpio71",
+						"gpio72", "gpio73";
+				function = "qup16";
+			};
+
+			config {
+				pins = "gpio70", "gpio71",
+						"gpio72", "gpio73";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se16_spi_sleep: qupv3_se16_spi_sleep {
+			mux {
+				pins = "gpio70", "gpio71",
+						"gpio72", "gpio73";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio70", "gpio71",
+						"gpio72", "gpio73";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se17_i2c_pins: qupv3_se17_i2c_pins {
+		qupv3_se17_i2c_active: qupv3_se17_i2c_active {
+			mux {
+				pins = "gpio61", "gpio62";
+				function = "qup17";
+			};
+
+			config {
+				pins = "gpio61", "gpio62";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se17_i2c_sleep: qupv3_se17_i2c_sleep {
+			mux {
+				pins = "gpio61", "gpio62";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio61", "gpio62";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se17_spi_pins: qupv3_se17_spi_pins {
+		qupv3_se17_spi_active: qupv3_se17_spi_active {
+			mux {
+				pins = "gpio61", "gpio62",
+						"gpio63", "gpio64";
+				function = "qup17";
+			};
+
+			config {
+				pins = "gpio61", "gpio62",
+						"gpio63", "gpio64";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se17_spi_sleep: qupv3_se17_spi_sleep {
+			mux {
+				pins = "gpio61", "gpio62",
+						"gpio63", "gpio64";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio61", "gpio62",
+						"gpio63", "gpio64";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se18_i2c_pins: qupv3_se18_i2c_pins {
+		qupv3_se18_i2c_active: qupv3_se18_i2c_active {
+			mux {
+				pins = "gpio66", "gpio67";
+				function = "qup18";
+			};
+
+			config {
+				pins = "gpio66", "gpio67";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se18_i2c_sleep: qupv3_se18_i2c_sleep {
+			mux {
+				pins = "gpio66", "gpio67";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio66", "gpio67";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se18_spi_pins: qupv3_se18_spi_pins {
+		qupv3_se18_spi_active: qupv3_se18_spi_active {
+			mux {
+				pins = "gpio66", "gpio67",
+						"gpio68", "gpio69";
+				function = "qup18";
+			};
+
+			config {
+				pins = "gpio66", "gpio67",
+						"gpio68", "gpio69";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se18_spi_sleep: qupv3_se18_spi_sleep {
+			mux {
+				pins = "gpio66", "gpio67",
+						"gpio68", "gpio69";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio66", "gpio67",
+						"gpio68", "gpio69";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se19_i2c_pins: qupv3_se19_i2c_pins {
+		qupv3_se19_i2c_active: qupv3_se19_i2c_active {
+			mux {
+				pins = "gpio55", "gpio56";
+				function = "qup19";
+			};
+
+			config {
+				pins = "gpio55", "gpio56";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se19_i2c_sleep: qupv3_se19_i2c_sleep {
+			mux {
+				pins = "gpio55", "gpio56";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio55", "gpio56";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se19_spi_pins: qupv3_se19_spi_pins {
+		qupv3_se19_spi_active: qupv3_se19_spi_active {
+			mux {
+				pins = "gpio55", "gpio56",
+						"gpio57", "gpio58";
+				function = "qup19";
+			};
+
+			config {
+				pins = "gpio55", "gpio56",
+						"gpio57", "gpio58";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se19_spi_sleep: qupv3_se19_spi_sleep {
+			mux {
+				pins = "gpio55", "gpio56",
+						"gpio57", "gpio58";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio55", "gpio56",
+						"gpio57", "gpio58";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se20_i2c_pins: qupv3_se20_i2c_pins {
+		qupv3_se20_i2c_active: qupv3_se20_i2c_active {
+			mux {
+				pins = "gpio87", "gpio88";
+				function = "qup20";
+			};
+
+			config {
+				pins = "gpio87", "gpio88";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se20_i2c_sleep: qupv3_se20_i2c_sleep {
+			mux {
+				pins = "gpio87", "gpio88";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio87", "gpio88";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se20_spi_pins: qupv3_se20_spi_pins {
+		qupv3_se20_spi_active: qupv3_se20_spi_active {
+			mux {
+				pins = "gpio87", "gpio88",
+						"gpio89", "gpio90";
+				function = "qup20";
+			};
+
+			config {
+				pins = "gpio87", "gpio88",
+						"gpio89", "gpio90";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se20_spi_sleep: qupv3_se20_spi_sleep {
+			mux {
+				pins = "gpio87", "gpio88",
+						"gpio89", "gpio90";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio87", "gpio88",
+						"gpio89", "gpio90";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se21_i2c_pins: qupv3_se21_i2c_pins {
+		qupv3_se21_i2c_active: qupv3_se21_i2c_active {
+			mux {
+				pins = "gpio81", "gpio82";
+				function = "qup21";
+			};
+
+			config {
+				pins = "gpio81", "gpio82";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se21_i2c_sleep: qupv3_se21_i2c_sleep {
+			mux {
+				pins = "gpio81", "gpio82";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio81", "gpio82";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se21_spi_pins: qupv3_se21_spi_pins {
+		qupv3_se21_spi_active: qupv3_se21_spi_active {
+			mux {
+				pins = "gpio81", "gpio82",
+						"gpio83", "gpio84";
+				function = "qup21";
+			};
+
+			config {
+				pins = "gpio81", "gpio82",
+						"gpio83", "gpio84";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se21_spi_sleep: qupv3_se21_spi_sleep {
+			mux {
+				pins = "gpio81", "gpio82",
+						"gpio83", "gpio84";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio81", "gpio82",
+						"gpio83", "gpio84";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se22_i2c_pins: qupv3_se22_i2c_pins {
+		qupv3_se22_i2c_active: qupv3_se22_i2c_active {
+			mux {
+				pins = "gpio85", "gpio85";
+				function = "qup22";
+			};
+
+			config {
+				pins = "gpio85", "gpio85";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se22_i2c_sleep: qupv3_se22_i2c_sleep {
+			mux {
+				pins = "gpio85", "gpio85";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio85", "gpio85";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se22_spi_pins: qupv3_se22_spi_pins {
+		qupv3_se22_spi_active: qupv3_se22_spi_active {
+			mux {
+				pins = "gpio85", "gpio86",
+						"gpio83", "gpio84";
+				function = "qup22";
+			};
+
+			config {
+				pins = "gpio85", "gpio86",
+						"gpio83", "gpio84";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se22_spi_sleep: qupv3_se22_spi_sleep {
+			mux {
+				pins = "gpio85", "gpio86",
+						"gpio83", "gpio84";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio85", "gpio86",
+						"gpio83", "gpio84";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se23_i2c_pins: qupv3_se23_i2c_pins {
+		qupv3_se23_i2c_active: qupv3_se23_i2c_active {
+			mux {
+				pins = "gpio59", "gpio60";
+				function = "qup23";
+			};
+
+			config {
+				pins = "gpio59", "gpio60";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+
+		qupv3_se23_i2c_sleep: qupv3_se23_i2c_sleep {
+			mux {
+				pins = "gpio59", "gpio60";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio59", "gpio60";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
+	qupv3_se23_spi_pins: qupv3_se23_spi_pins {
+		qupv3_se23_spi_active: qupv3_se23_spi_active {
+			mux {
+				pins = "gpio59", "gpio60",
+						"gpio61", "gpio62";
+				function = "qup23";
+			};
+
+			config {
+				pins = "gpio59", "gpio60",
+						"gpio61", "gpio62";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se23_spi_sleep: qupv3_se23_spi_sleep {
+			mux {
+				pins = "gpio59", "gpio60",
+						"gpio61", "gpio62";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio59", "gpio60",
+						"gpio61", "gpio62";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+	};
+};
diff --git a/qcom/direwolf-qupv3.dtsi b/qcom/direwolf-qupv3.dtsi
new file mode 100644
index 000000000000..a0274605c38f
--- /dev/null
+++ b/qcom/direwolf-qupv3.dtsi
@@ -0,0 +1,996 @@
+#include <dt-bindings/interconnect/qcom,direwolf.h>
+
+&soc {
+	/* QUPv3 SE Instances
+	 * Qup0 0: SE 0
+	 * Qup0 1: SE 1
+	 * Qup0 2: SE 2
+	 * Qup0 3: SE 3
+	 * Qup0 4: SE 4
+	 * Qup0 5: SE 5
+	 * Qup0 6: SE 6
+	 * Qup0 7: SE 7
+	 * Qup1 0: SE 8
+	 * Qup1 1: SE 9
+	 * Qup1 2: SE 10
+	 * Qup1 3: SE 11
+	 * Qup1 4: SE 12
+	 * Qup1 5: SE 13
+	 * Qup1 6: SE 14
+	 * Qup1 7: SE 15
+	 * Qup2 0: SE 16
+	 * Qup2 1: SE 17
+	 * Qup2 2: SE 18
+	 * Qup2 3: SE 19
+	 * Qup2 4: SE 20
+	 * Qup2 5: SE 21
+	 * Qup2 6: SE 22
+	 * Qup2 7: SE 23
+	 */
+
+	/* QUPv3_0  wrapper  instance */
+	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
+		compatible = "qcom,qupv3-geni-se";
+		reg = <0x9c0000 0x2000>;
+		qcom,msm-bus,num-paths = <2>;
+		qcom,msm-bus,vectors-bus-ids =
+			<MASTER_QUP_CORE_0 SLAVE_QUP_CORE_0>,
+			<MASTER_QUP_0 SLAVE_EBI1>;
+		iommus = <&apps_smmu 0x563 0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		status = "ok";
+	};
+
+	/* QUPv3_1  wrapper  instance */
+	qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
+		compatible = "qcom,qupv3-geni-se";
+		reg = <0xac0000 0x2000>;
+		qcom,msm-bus,num-paths = <2>;
+		qcom,msm-bus,vectors-bus-ids =
+			<MASTER_QUP_CORE_1 SLAVE_QUP_CORE_1>,
+			<MASTER_QUP_1 SLAVE_EBI1>;
+		iommus = <&apps_smmu 0x83 0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		status = "ok";
+	};
+
+	/* QUPv3_2  wrapper  instance */
+	qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
+		compatible = "qcom,qupv3-geni-se";
+		reg = <0x8c0000 0x2000>;
+		qcom,msm-bus,num-paths = <2>;
+		qcom,msm-bus,vectors-bus-ids =
+			<MASTER_QUP_CORE_2 SLAVE_QUP_CORE_2>,
+			<MASTER_QUP_2 SLAVE_EBI1>;
+		iommus = <&apps_smmu 0xa3 0x0>;
+		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		qcom,iommu-geometry = <0x40000000 0x10000000>;
+		qcom,iommu-dma = "fastmap";
+		status = "ok";
+	};
+
+	/* Debug UART Instance */
+	qupv3_se17_2uart: qcom,qup_uart@884000 {
+		compatible = "qcom,msm-geni-console";
+		reg = <0x884000 0x4000>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se17_2uart_active>;
+		pinctrl-1 = <&qupv3_se17_2uart_sleep>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se16_i2c: i2c@880000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x880000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se16_i2c_active>;
+		pinctrl-1 = <&qupv3_se16_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se16_spi: spi@880000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x880000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se16_spi_active>;
+		pinctrl-1 = <&qupv3_se16_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se17_i2c: i2c@884000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x884000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se17_i2c_active>;
+		pinctrl-1 = <&qupv3_se17_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se17_spi: spi@884000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x884000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se17_spi_active>;
+		pinctrl-1 = <&qupv3_se17_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se18_i2c: i2c@888000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x888000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se18_i2c_active>;
+		pinctrl-1 = <&qupv3_se18_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se18_spi: spi@888000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x888000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se18_spi_active>;
+		pinctrl-1 = <&qupv3_se18_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se19_i2c: i2c@88c000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x88c000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se19_i2c_active>;
+		pinctrl-1 = <&qupv3_se19_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se19_spi: spi@88c000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x88c000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se19_spi_active>;
+		pinctrl-1 = <&qupv3_se19_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se20_i2c: i2c@890000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x890000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se20_i2c_active>;
+		pinctrl-1 = <&qupv3_se20_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se20_spi: spi@890000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x890000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se20_spi_active>;
+		pinctrl-1 = <&qupv3_se20_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se21_i2c: i2c@894000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x894000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se21_i2c_active>;
+		pinctrl-1 = <&qupv3_se21_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se21_spi: spi@894000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x894000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se21_spi_active>;
+		pinctrl-1 = <&qupv3_se21_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se22_i2c: i2c@898000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x898000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se22_i2c_active>;
+		pinctrl-1 = <&qupv3_se22_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se22_spi: spi@898000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x898000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se22_spi_active>;
+		pinctrl-1 = <&qupv3_se22_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se23_i2c: i2c@89c000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x89c000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se23_i2c_active>;
+		pinctrl-1 = <&qupv3_se23_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	qupv3_se23_spi: spi@89c000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x89c000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se23_spi_active>;
+		pinctrl-1 = <&qupv3_se23_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_2>;
+		status = "disabled";
+	};
+
+	/* 4-wire HSUART Instance */
+	qupv3_se2_4uart: qcom,qup_uart@988000 {
+		compatible = "qcom,msm-geni-serial-hs";
+		reg = <0x988000 0x4000>;
+		reg-names = "se_phys";
+		interrupts-extended = <&intc GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
+				<&tlmm 124 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "active", "sleep";
+		pinctrl-0 = <&qupv3_se2_default_cts>,
+			<&qupv3_se2_default_rtsrx>, <&qupv3_se2_default_tx>;
+		pinctrl-1 = <&qupv3_se2_ctsrx>, <&qupv3_se2_rts>,
+						<&qupv3_se2_tx>;
+		pinctrl-2 = <&qupv3_se2_ctsrx>, <&qupv3_se2_rts>,
+						<&qupv3_se2_tx>;
+		qcom,wakeup-byte = <0xFD>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se0_i2c: i2c@980000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x980000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se0_i2c_active>;
+		pinctrl-1 = <&qupv3_se0_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se0_spi: spi@980000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x980000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se0_spi_active>;
+		pinctrl-1 = <&qupv3_se0_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se1_i2c: i2c@984000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x984000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se1_i2c_active>;
+		pinctrl-1 = <&qupv3_se1_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se1_spi: spi@984000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x984000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se1_spi_active>;
+		pinctrl-1 = <&qupv3_se1_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se2_i2c: i2c@988000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x988000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se2_i2c_active>;
+		pinctrl-1 = <&qupv3_se2_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se2_spi: spi@988000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x988000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se2_spi_active>;
+		pinctrl-1 = <&qupv3_se2_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se3_i2c: i2c@98c000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x98c000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se3_i2c_active>;
+		pinctrl-1 = <&qupv3_se3_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se3_spi: spi@98c000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x98c000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se3_spi_active>;
+		pinctrl-1 = <&qupv3_se3_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se4_i2c: i2c@990000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x990000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se4_i2c_active>;
+		pinctrl-1 = <&qupv3_se4_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se4_spi: spi@990000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x990000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se4_spi_active>;
+		pinctrl-1 = <&qupv3_se4_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se5_i2c: i2c@994000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x994000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se5_i2c_active>;
+		pinctrl-1 = <&qupv3_se5_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se5_spi: spi@994000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x994000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se5_spi_active>;
+		pinctrl-1 = <&qupv3_se5_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se6_i2c: i2c@998000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x998000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se6_i2c_active>;
+		pinctrl-1 = <&qupv3_se6_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se6_spi: spi@998000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x998000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se6_spi_active>;
+		pinctrl-1 = <&qupv3_se6_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se7_i2c: i2c@99c000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x99c000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se7_i2c_active>;
+		pinctrl-1 = <&qupv3_se7_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se7_spi: spi@99c000 {
+		compatible = "qcom,spi-geni";
+		reg = <0x99c000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se7_spi_active>;
+		pinctrl-1 = <&qupv3_se7_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+
+	qupv3_se8_i2c: i2c@a80000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0xa80000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se8_i2c_active>;
+		pinctrl-1 = <&qupv3_se8_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se8_spi: spi@a80000 {
+		compatible = "qcom,spi-geni";
+		reg = <0xa80000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se8_spi_active>;
+		pinctrl-1 = <&qupv3_se8_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se9_i2c: i2c@a84000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0xa84000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se9_i2c_active>;
+		pinctrl-1 = <&qupv3_se9_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se9_spi: spi@a84000 {
+		compatible = "qcom,spi-geni";
+		reg = <0xa84000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se9_spi_active>;
+		pinctrl-1 = <&qupv3_se9_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se10_i2c: i2c@a88000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0xa88000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se10_i2c_active>;
+		pinctrl-1 = <&qupv3_se10_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se10_spi: spi@a88000 {
+		compatible = "qcom,spi-geni";
+		reg = <0xa88000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se10_spi_active>;
+		pinctrl-1 = <&qupv3_se10_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se11_i2c: i2c@a8c000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0xa8c000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se11_i2c_active>;
+		pinctrl-1 = <&qupv3_se11_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se11_spi: spi@a8c000 {
+		compatible = "qcom,spi-geni";
+		reg = <0xa8c000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se11_spi_active>;
+		pinctrl-1 = <&qupv3_se11_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se12_i2c: i2c@a90000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0xa90000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se12_i2c_active>;
+		pinctrl-1 = <&qupv3_se12_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se12_spi: spi@a90000 {
+		compatible = "qcom,spi-geni";
+		reg = <0xa90000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se12_spi_active>;
+		pinctrl-1 = <&qupv3_se12_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se13_i2c: i2c@a94000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0xa94000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se13_i2c_active>;
+		pinctrl-1 = <&qupv3_se13_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se13_spi: spi@a94000 {
+		compatible = "qcom,spi-geni";
+		reg = <0xa94000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se13_spi_active>;
+		pinctrl-1 = <&qupv3_se13_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	/* 2-Wire HSUART Instance */
+	qupv3_se13_2uart: qcom,qup_uart@a94000 {
+		compatible = "qcom,msm-geni-serial-hs";
+		reg = <0xa94000 0x4000>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se13_2uart_active>;
+		pinctrl-1 = <&qupv3_se13_2uart_sleep>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se14_i2c: i2c@a98000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0xa98000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se14_i2c_active>;
+		pinctrl-1 = <&qupv3_se14_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se14_spi: spi@a98000 {
+		compatible = "qcom,spi-geni";
+		reg = <0xa98000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se14_spi_active>;
+		pinctrl-1 = <&qupv3_se14_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se15_i2c: i2c@a9c000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0xa9c000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se15_i2c_active>;
+		pinctrl-1 = <&qupv3_se15_i2c_sleep>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+
+	qupv3_se15_spi: spi@a9c000 {
+		compatible = "qcom,spi-geni";
+		reg = <0xa9c000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se15_spi_active>;
+		pinctrl-1 = <&qupv3_se15_spi_sleep>;
+		spi-max-frequency = <50000000>;
+		qcom,wrapper-core = <&qupv3_1>;
+		status = "disabled";
+	};
+};