From e71c756ffc0f6acb84912717fe2ce77abf81e9d7 Mon Sep 17 00:00:00 2001
From: Saurabh Ambulkar <sambulka@qti.qualcomm.com>
Date: Wed, 19 Aug 2020 22:45:45 +0530
Subject: [PATCH] ARM: dts: msm: Add lpass device node for PIL on SDMSHRIKE

Add PIL device tree node to load firmware images of lpass
on SDMSHRIKE.

Change-Id: Ic04366af333b8cb9292820539937df1d538c769d
---
 qcom/sdmshrike.dtsi | 44 +++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 43 insertions(+), 1 deletion(-)

diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi
index f3ba2a28e8b3..9ea6492e327f 100644
--- a/qcom/sdmshrike.dtsi
+++ b/qcom/sdmshrike.dtsi
@@ -1463,7 +1463,6 @@
 		qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
 
 		qcom,devfreq,freq-table = <50000000 200000000>;
-
 		status = "disabled";
 
 		qos0 {
@@ -1477,6 +1476,49 @@
 		};
 	};
 
+	qcom,lpass@17300000 {
+		compatible = "qcom,pil-tz-generic";
+		reg = <0x17300000 0x00100>;
+
+		vdd_cx-supply = <&VDD_CX_LEVEL>;
+		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+		qcom,proxy-reg-names = "vdd_cx";
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+		qcom,proxy-clock-names = "xo";
+
+		qcom,pas-id = <1>;
+		qcom,proxy-timeout-ms = <10000>;
+		qcom,smem-id = <423>;
+		qcom,sysmon-id = <1>;
+		qcom,ssctl-instance-id = <0x14>;
+		qcom,firmware-name = "adsp";
+		memory-region = <&pil_adsp_mem>;
+		qcom,signal-aop;
+		qcom,complete-ramdump;
+		qcom,pil-force-shutdown;
+
+		/* Inputs from lpass */
+		interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+				<&adsp_smp2p_in 0 0>,
+				<&adsp_smp2p_in 2 0>,
+				<&adsp_smp2p_in 1 0>,
+				<&adsp_smp2p_in 3 0>;
+
+		interrupt-names = "qcom,wdog",
+				"qcom,err-fatal",
+				"qcom,proxy-unvote",
+				"qcom,err-ready",
+				"qcom,stop-ack";
+
+		/* Outputs to lpass */
+		qcom,smem-states = <&adsp_smp2p_out 0>;
+		qcom,smem-state-names = "qcom,force-stop";
+
+		mboxes = <&qmp_aop 0>;
+		mbox-names = "adsp-pil";
+	};
 };
 
 #include "sdmshrike-pinctrl.dtsi"