mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-09 21:59:12 -04:00
Merge "ARM: dts: msm: add PMIC devices for SCSHRIKE"
This commit is contained in:
qctecmdr
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commit
e72cf7987f
4 changed files with 495 additions and 0 deletions
307
qcom/pm8195.dtsi
Normal file
307
qcom/pm8195.dtsi
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@ -0,0 +1,307 @@
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/iio/qcom,spmi-vadc.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/input/qcom,qpnp-power-on.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/spmi/spmi.h>
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&spmi_bus {
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#address-cells = <2>;
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#size-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <4>;
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qcom,pm8195@0 {
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compatible = "qcom,spmi-pmic";
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reg = <0 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pm8195_1_tz: qcom,temp-alarm@2400 {
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compatible = "qcom,spmi-temp-alarm";
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reg = <0x2400>;
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interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
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io-channels = <&pm8195_1_vadc ADC5_DIE_TEMP>;
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io-channel-names = "thermal";
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#thermal-sensor-cells = <0>;
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qcom,temperature-threshold-set = <1>;
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};
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pm8195_1_vadc: vadc@3100 {
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compatible = "qcom,spmi-adc5";
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reg = <0x3100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eoc-int-en-set";
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#io-channel-cells = <1>;
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io-channel-ranges;
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/* Channel node */
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ref_gnd {
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reg = <ADC5_REF_GND>;
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label = "ref_gnd";
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qcom,pre-scaling = <1 1>;
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};
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vref_1p25 {
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reg = <ADC5_1P25VREF>;
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label = "vref_1p25";
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qcom,pre-scaling = <1 1>;
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};
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die_temp {
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reg = <ADC5_DIE_TEMP>;
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label = "die_temp";
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qcom,pre-scaling = <1 1>;
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};
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};
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qcom,power-on@800 {
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compatible = "qcom,qpnp-power-on";
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reg = <0x800>;
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interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>,
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<0x0 0x8 0x1 IRQ_TYPE_NONE>;
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interrupt-names = "kpdpwr", "resin";
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qcom,pon-dbc-delay = <15625>;
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qcom,kpdpwr-sw-debounce;
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qcom,system-reset;
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qcom,store-hard-reset-reason;
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qcom,pon_1 {
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qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
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qcom,pull-up;
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linux,code = <KEY_POWER>;
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};
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qcom,pon_2 {
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qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
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qcom,pull-up;
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linux,code = <KEY_VOLUMEDOWN>;
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};
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};
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pm8195_1_clkdiv: clock-controller@5b00 {
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compatible = "qcom,spmi-clkdiv";
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reg = <0x5b00>;
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#clock-cells = <1>;
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qcom,num-clkdivs = <2>;
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clock-output-names = "pm8195_1_div_clk1",
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"pm8195_1_div_clk2";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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};
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pm8195_1_rtc: qcom,pm8195_1_rtc {
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compatible = "qcom,pm8941-rtc";
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reg = <0x6000>, <0x6100>;
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reg-names = "rtc", "alarm";
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interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
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};
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pm8195_1_gpios: pinctrl@c000 {
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compatible = "qcom,pm8150-gpio";
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reg = <0xc000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pm8195_1_sdam_2: sdam@b100 {
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compatible = "qcom,spmi-sdam";
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reg = <0xb100>;
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};
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};
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qcom,pm8195@1 {
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compatible ="qcom,spmi-pmic";
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reg = <1 SPMI_USID>;
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#address-cells = <2>;
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#size-cells = <0>;
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};
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/* below definitions are for the second instance of pm8195 */
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qcom,pm8195@4 {
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compatible = "qcom,spmi-pmic";
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reg = <4 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pm8195_2_tz: qcom,temp-alarm@2400 {
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compatible = "qcom,spmi-temp-alarm";
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reg = <0x2400>;
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interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
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io-channels = <&pm8195_2_vadc ADC5_DIE_TEMP>;
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io-channel-names = "thermal";
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#thermal-sensor-cells = <0>;
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qcom,temperature-threshold-set = <1>;
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};
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pm8195_2_vadc: vadc@3100 {
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compatible = "qcom,spmi-adc5";
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reg = <0x3100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eoc-int-en-set";
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#io-channel-cells = <1>;
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io-channel-ranges;
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/* Channel node */
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ref_gnd {
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reg = <ADC5_REF_GND>;
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label = "ref_gnd";
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qcom,pre-scaling = <1 1>;
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};
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vref_1p25 {
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reg = <ADC5_1P25VREF>;
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label = "vref_1p25";
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qcom,pre-scaling = <1 1>;
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};
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die_temp {
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reg = <ADC5_DIE_TEMP>;
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label = "die_temp";
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qcom,pre-scaling = <1 1>;
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};
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};
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qcom,power-on@800 {
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compatible = "qcom,qpnp-power-on";
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reg = <0x800>;
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};
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pm8195_2_clkdiv: clock-controller@5b00 {
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compatible = "qcom,spmi-clkdiv";
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reg = <0x5b00>;
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#clock-cells = <1>;
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qcom,num-clkdivs = <2>;
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clock-output-names = "pm8195_2_div_clk1",
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"pm8195_2_div_clk2";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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};
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pm8195_2_gpios: pinctrl@c000 {
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compatible = "qcom,pm8150-gpio";
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reg = <0xc000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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qcom,pm8195@5 {
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compatible ="qcom,spmi-pmic";
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reg = <5 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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/* below definitions are for the third instance of pm8195 */
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qcom,pm8195@8 {
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compatible = "qcom,spmi-pmic";
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reg = <8 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pm8195_3_tz: qcom,temp-alarm@2400 {
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compatible = "qcom,spmi-temp-alarm";
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reg = <0x2400>;
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interrupts = <0x8 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
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io-channels = <&pm8195_3_vadc ADC5_DIE_TEMP>;
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io-channel-names = "thermal";
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#thermal-sensor-cells = <0>;
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qcom,temperature-threshold-set = <1>;
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};
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pm8195_3_vadc: vadc@3100 {
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compatible = "qcom,spmi-adc5";
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reg = <0x3100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eoc-int-en-set";
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#io-channel-cells = <1>;
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io-channel-ranges;
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/* Channel node */
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ref_gnd {
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reg = <ADC5_REF_GND>;
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label = "ref_gnd";
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qcom,pre-scaling = <1 1>;
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};
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vref_1p25 {
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reg = <ADC5_1P25VREF>;
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label = "vref_1p25";
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qcom,pre-scaling = <1 1>;
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};
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die_temp {
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reg = <ADC5_DIE_TEMP>;
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label = "die_temp";
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qcom,pre-scaling = <1 1>;
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};
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};
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qcom,power-on@800 {
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compatible = "qcom,qpnp-power-on";
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reg = <0x800>;
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};
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pm8195_3_clkdiv: clock-controller@5b00 {
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compatible = "qcom,spmi-clkdiv";
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reg = <0x5b00>;
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#clock-cells = <1>;
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qcom,num-clkdivs = <2>;
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clock-output-names = "pm8195_3_div_clk1",
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"pm8195_3_div_clk2";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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};
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pm8195_3_gpios: pinctrl@c000 {
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compatible = "qcom,pm8150-gpio";
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reg = <0xc000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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qcom,pm8195@9 {
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compatible ="qcom,spmi-pmic";
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reg = <9 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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/* PMIC GPIO pin control configurations */
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&pm8195_1_gpios {
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storage_sd_detect {
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storage_cd_default: storage_cd_default {
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pins = "gpio4";
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function = "normal";
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input-enable;
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bias-pull-up;
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power-source = <0>;
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};
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};
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key_vol_up {
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key_vol_up_default: key_vol_up_default {
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pins = "gpio6";
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function = "normal";
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input-enable;
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bias-pull-up;
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power-source = <1>;
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};
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};
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};
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@ -69,3 +69,4 @@
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};
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#include "sa8195p-regulator.dtsi"
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#include "pm8195.dtsi"
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@ -11,3 +11,33 @@
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vdd_scc_cx-supply = <&VDD_SCC_CX_LEVEL>;
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status = "ok"
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};
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&ufsphy_mem {
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compatible = "qcom,ufs-phy-qmp-v4";
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vdda-phy-supply = <&pm8195_3_l5>;
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vdda-pll-supply = <&pm8195_1_l9>;
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vdda-phy-max-microamp = <138000>;
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vdda-pll-max-microamp = <65100>;
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status = "ok"
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};
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&ufshc_mem {
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vdd-hba-supply = <&ufs_phy_gdsc>;
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vdd-hba-fixed-regulator;
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vcc-supply = <&pm8195_3_l10>;
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vcc-voltage-level = <2894000 2904000>;
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vcc-low-voltage-sup;
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vccq-supply = <&pm8195_1_l11>;
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vccq2-supply = <&pm8195_3_l7>;
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vcc-max-microamp = <750000>;
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vccq-max-microamp = <750000>;
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vccq2-max-microamp = <750000>;
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qcom,vddp-ref-clk-supply = <&pm8195_2_l5>;
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qcom,vddp-ref-clk-max-microamp = <100>;
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qcom,vccq-parent-supply = <&pm8195_1_s2>;
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qcom,vccq-parent-max-microamp = <210000>;
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status= "ok"
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};
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|
|
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@ -7,11 +7,14 @@
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#include <dt-bindings/clock/qcom,scc-sm8150.h>
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#include <dt-bindings/clock/qcom,videocc-sm8150.h>
|
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#include <dt-bindings/clock/qcom,rpmh.h>
|
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
|
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#include <dt-bindings/interconnect/qcom,osm-l3.h>
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#include <dt-bindings/interconnect/qcom,scshrike.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
|
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
|
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
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|
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/ {
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model = "Qualcomm Technologies, Inc. SDMSHRIKE";
|
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|
|
@ -26,6 +29,7 @@
|
|||
|
||||
aliases {
|
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serial0 = &uart2;
|
||||
ufshc1 = &ufshc_mem; /* Embedded UFS slot */
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
@ -974,6 +978,159 @@
|
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#freq-domain-cells = <2>;
|
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};
|
||||
|
||||
ufsphy_mem: ufsphy_mem@1d87000 {
|
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reg = <0x1d87000 0xe00>; /* PHY regs */
|
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reg-names = "phy_mem";
|
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#phy-cells = <0>;
|
||||
|
||||
lanes-per-direction = <2>;
|
||||
|
||||
clock-names = "ref_clk_src",
|
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"ref_clk",
|
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"ref_aux_clk";
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_UFS_MEM_CLKREF_CLK>,
|
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<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
|
||||
|
||||
resets = <&ufshc_mem 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ufshc_mem: ufshc@1d84000 {
|
||||
compatible = "qcom,ufshc";
|
||||
reg = <0x1d84000 0x3000>,
|
||||
<0x1d90000 0x8000>;
|
||||
reg-names = "ufs_mem", "ufs_ice";
|
||||
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&ufsphy_mem>;
|
||||
phy-names = "ufsphy";
|
||||
#reset-cells = <1>;
|
||||
|
||||
lanes-per-direction = <2>;
|
||||
dev-ref-clk-freq = <0>; /* 19.2 MHz */
|
||||
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"bus_aggr_clk",
|
||||
"iface_clk",
|
||||
"core_clk_unipro",
|
||||
"core_clk_ice",
|
||||
"ref_clk",
|
||||
"tx_lane0_sync_clk",
|
||||
"rx_lane0_sync_clk",
|
||||
"rx_lane1_sync_clk";
|
||||
clocks =
|
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<&gcc GCC_UFS_PHY_AXI_CLK>,
|
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<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
||||
<&gcc GCC_UFS_PHY_AHB_CLK>,
|
||||
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
|
||||
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
|
||||
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
|
||||
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
|
||||
freq-table-hz =
|
||||
<37500000 300000000>,
|
||||
<0 0>,
|
||||
<0 0>,
|
||||
<37500000 300000000>,
|
||||
<37500000 300000000>,
|
||||
<0 0>,
|
||||
<0 0>,
|
||||
<0 0>,
|
||||
<0 0>;
|
||||
interconnects =
|
||||
<&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
|
||||
<&gem_noc MASTER_APPSS_PROC
|
||||
&config_noc SLAVE_UFS_MEM_0_CFG>;
|
||||
interconnect-names = "ufs-ddr", "cpu-ufs";
|
||||
|
||||
qcom,ufs-bus-bw,name = "ufshc_mem";
|
||||
qcom,ufs-bus-bw,num-cases = <26>;
|
||||
qcom,ufs-bus-bw,num-paths = <2>;
|
||||
qcom,ufs-bus-bw,vectors-KBps =
|
||||
/*
|
||||
* During HS G3 UFS runs at nominal voltage corner, vote
|
||||
* higher bandwidth to push other buses in the data path
|
||||
* to run at nominal to achieve max throughput.
|
||||
* 4GBps pushes BIMC to run at nominal.
|
||||
* 200MBps pushes CNOC to run at nominal.
|
||||
* Vote for half of this bandwidth for HS G3 1-lane.
|
||||
* For max bandwidth, vote high enough to push the buses
|
||||
* to run in turbo voltage corner.
|
||||
*/
|
||||
<0 0>, <0 0>, /* No vote */
|
||||
<922 0>, <1000 0>, /* PWM G1 */
|
||||
<1844 0>, <1000 0>, /* PWM G2 */
|
||||
<3688 0>, <1000 0>, /* PWM G3 */
|
||||
<7376 0>, <1000 0>, /* PWM G4 */
|
||||
<1844 0>, <1000 0>, /* PWM G1 L2 */
|
||||
<3688 0>, <1000 0>, /* PWM G2 L2 */
|
||||
<7376 0>, <1000 0>, /* PWM G3 L2 */
|
||||
<14752 0>, <1000 0>, /* PWM G4 L2 */
|
||||
<127796 0>, <1000 0>, /* HS G1 RA */
|
||||
<255591 0>, <1000 0>, /* HS G2 RA */
|
||||
<2097152 0>, <102400 0>, /* HS G3 RA */
|
||||
<4194304 0>, <204800 0>, /* HS G4 RA */
|
||||
<255591 0>, <1000 0>, /* HS G1 RA L2 */
|
||||
<511181 0>, <1000 0>, /* HS G2 RA L2 */
|
||||
<4194304 0>, <204800 0>, /* HS G3 RA L2 */
|
||||
<8388608 0>, <409600 0>, /* HS G4 RA L2 */
|
||||
<149422 0>, <1000 0>, /* HS G1 RB */
|
||||
<298189 0>, <1000 0>, /* HS G2 RB */
|
||||
<2097152 0>, <102400 0>, /* HS G3 RB */
|
||||
<4194304 0>, <204800 0>, /* HS G4 RB */
|
||||
<298189 0>, <1000 0>, /* HS G1 RB L2 */
|
||||
<596378 0>, <1000 0>, /* HS G2 RB L2 */
|
||||
/* As UFS working in HS G3 RB L2 mode, aggregated
|
||||
* bandwidth (AB) should take care of providing
|
||||
* optimum throughput requested. However, as tested,
|
||||
* in order to scale up CNOC clock, instantaneous
|
||||
* bindwidth (IB) needs to be given a proper value too.
|
||||
*/
|
||||
<4194304 0>, <204800 409600>, /* HS G3 RB L2 */
|
||||
<8388608 0>, <409600 409600>, /* HS G4 RB L2 */
|
||||
<7643136 0>, <307200 0>; /* Max. bandwidth */
|
||||
|
||||
qcom,bus-vector-names = "MIN",
|
||||
"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
|
||||
"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
|
||||
"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
|
||||
"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
|
||||
"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
|
||||
"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
|
||||
"MAX";
|
||||
|
||||
reset-gpios = <&tlmm 190 GPIO_ACTIVE_LOW>;
|
||||
|
||||
resets = <&gcc GCC_UFS_PHY_BCR>;
|
||||
reset-names = "rst";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spmi_bus: qcom,spmi@c440000 {
|
||||
compatible = "qcom,spmi-pmic-arb";
|
||||
reg = <0xc440000 0x1000>,
|
||||
<0xc600000 0x2000000>,
|
||||
<0xe600000 0x100000>,
|
||||
<0xe700000 0xa0000>,
|
||||
<0xc40a000 0x700>;
|
||||
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
||||
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "periph_irq";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <4>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
qcom,channel = <0>;
|
||||
qcom,ee = <0>;
|
||||
};
|
||||
|
||||
thermal_zones: thermal-zones {
|
||||
};
|
||||
|
||||
tcsr_mutex_block: syscon@1f40000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x1f40000 0x20000>;
|
||||
|
|
|
|||
Loading…
Reference in a new issue