mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-25 22:23:14 -04:00
Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6
* 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (88 commits) PCI: fix HT MSI mapping fix PCI: don't enable too much HT MSI mapping x86/PCI: make pci=lastbus=255 work when acpi is on PCI: save and restore PCIe 2.0 registers PCI: update fakephp for bus_id removal PCI: fix kernel oops on bridge removal PCI: fix conflict between SR-IOV and config space sizing powerpc/PCI: include pci.h in powerpc MSI implementation PCI Hotplug: schedule fakephp for feature removal PCI Hotplug: rename legacy_fakephp to fakephp PCI Hotplug: restore fakephp interface with complete reimplementation PCI: Introduce /sys/bus/pci/devices/.../rescan PCI: Introduce /sys/bus/pci/devices/.../remove PCI: Introduce /sys/bus/pci/rescan PCI: Introduce pci_rescan_bus() PCI: do not enable bridges more than once PCI: do not initialize bridges more than once PCI: always scan child buses PCI: pci_scan_slot() returns newly found devices PCI: don't scan existing devices ... Fix trivial append-only conflict in Documentation/feature-removal-schedule.txt
This commit is contained in:
Linus Torvalds
commit
e76e5b2c66
62 changed files with 3641 additions and 1902 deletions
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@ -257,6 +257,40 @@ void __init acpi_no_s4_hw_signature(void);
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void __init acpi_old_suspend_ordering(void);
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void __init acpi_s4_no_nvs(void);
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#endif /* CONFIG_PM_SLEEP */
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#define OSC_QUERY_TYPE 0
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#define OSC_SUPPORT_TYPE 1
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#define OSC_CONTROL_TYPE 2
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#define OSC_SUPPORT_MASKS 0x1f
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/* _OSC DW0 Definition */
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#define OSC_QUERY_ENABLE 1
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#define OSC_REQUEST_ERROR 2
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#define OSC_INVALID_UUID_ERROR 4
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#define OSC_INVALID_REVISION_ERROR 8
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#define OSC_CAPABILITIES_MASK_ERROR 16
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/* _OSC DW1 Definition (OS Support Fields) */
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#define OSC_EXT_PCI_CONFIG_SUPPORT 1
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#define OSC_ACTIVE_STATE_PWR_SUPPORT 2
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#define OSC_CLOCK_PWR_CAPABILITY_SUPPORT 4
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#define OSC_PCI_SEGMENT_GROUPS_SUPPORT 8
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#define OSC_MSI_SUPPORT 16
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/* _OSC DW1 Definition (OS Control Fields) */
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#define OSC_PCI_EXPRESS_NATIVE_HP_CONTROL 1
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#define OSC_SHPC_NATIVE_HP_CONTROL 2
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#define OSC_PCI_EXPRESS_PME_CONTROL 4
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#define OSC_PCI_EXPRESS_AER_CONTROL 8
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#define OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL 16
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#define OSC_CONTROL_MASKS (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL | \
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OSC_SHPC_NATIVE_HP_CONTROL | \
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OSC_PCI_EXPRESS_PME_CONTROL | \
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OSC_PCI_EXPRESS_AER_CONTROL | \
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OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL)
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extern acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 flags);
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#else /* CONFIG_ACPI */
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static inline int early_acpi_boot_init(void)
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@ -20,20 +20,23 @@ extern void write_msi_msg(unsigned int irq, struct msi_msg *msg);
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struct msi_desc {
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struct {
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__u8 type : 5; /* {0: unused, 5h:MSI, 11h:MSI-X} */
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__u8 is_msix : 1;
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__u8 multiple: 3; /* log2 number of messages */
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__u8 maskbit : 1; /* mask-pending bit supported ? */
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__u8 masked : 1;
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__u8 is_64 : 1; /* Address size: 0=32bit 1=64bit */
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__u8 pos; /* Location of the msi capability */
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__u32 maskbits_mask; /* mask bits mask */
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__u16 entry_nr; /* specific enabled entry */
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unsigned default_irq; /* default pre-assigned irq */
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}msi_attrib;
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} msi_attrib;
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u32 masked; /* mask bits */
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unsigned int irq;
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struct list_head list;
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void __iomem *mask_base;
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union {
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void __iomem *mask_base;
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u8 mask_pos;
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};
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struct pci_dev *dev;
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/* Last set MSI message */
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@ -10,72 +10,25 @@
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#include <linux/acpi.h>
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#define OSC_QUERY_TYPE 0
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#define OSC_SUPPORT_TYPE 1
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#define OSC_CONTROL_TYPE 2
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#define OSC_SUPPORT_MASKS 0x1f
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/*
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* _OSC DW0 Definition
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*/
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#define OSC_QUERY_ENABLE 1
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#define OSC_REQUEST_ERROR 2
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#define OSC_INVALID_UUID_ERROR 4
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#define OSC_INVALID_REVISION_ERROR 8
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#define OSC_CAPABILITIES_MASK_ERROR 16
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/*
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* _OSC DW1 Definition (OS Support Fields)
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*/
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#define OSC_EXT_PCI_CONFIG_SUPPORT 1
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#define OSC_ACTIVE_STATE_PWR_SUPPORT 2
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#define OSC_CLOCK_PWR_CAPABILITY_SUPPORT 4
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#define OSC_PCI_SEGMENT_GROUPS_SUPPORT 8
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#define OSC_MSI_SUPPORT 16
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/*
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* _OSC DW1 Definition (OS Control Fields)
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*/
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#define OSC_PCI_EXPRESS_NATIVE_HP_CONTROL 1
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#define OSC_SHPC_NATIVE_HP_CONTROL 2
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#define OSC_PCI_EXPRESS_PME_CONTROL 4
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#define OSC_PCI_EXPRESS_AER_CONTROL 8
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#define OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL 16
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#define OSC_CONTROL_MASKS (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL | \
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OSC_SHPC_NATIVE_HP_CONTROL | \
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OSC_PCI_EXPRESS_PME_CONTROL | \
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OSC_PCI_EXPRESS_AER_CONTROL | \
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OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL)
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#ifdef CONFIG_ACPI
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extern acpi_status pci_osc_control_set(acpi_handle handle, u32 flags);
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int pci_acpi_osc_support(acpi_handle handle, u32 flags);
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static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev *pdev)
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{
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/* Find root host bridge */
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while (pdev->bus->self)
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pdev = pdev->bus->self;
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return acpi_get_pci_rootbridge_handle(pci_domain_nr(pdev->bus),
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pdev->bus->number);
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struct pci_bus *pbus = pdev->bus;
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/* Find a PCI root bus */
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while (pbus->parent)
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pbus = pbus->parent;
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return acpi_get_pci_rootbridge_handle(pci_domain_nr(pbus),
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pbus->number);
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}
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static inline acpi_handle acpi_pci_get_bridge_handle(struct pci_bus *pbus)
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{
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int seg = pci_domain_nr(pbus), busnr = pbus->number;
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struct pci_dev *bridge = pbus->self;
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if (bridge)
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return DEVICE_ACPI_HANDLE(&(bridge->dev));
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return acpi_get_pci_rootbridge_handle(seg, busnr);
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if (pbus->parent)
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return DEVICE_ACPI_HANDLE(&(pbus->self->dev));
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return acpi_get_pci_rootbridge_handle(pci_domain_nr(pbus),
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pbus->number);
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}
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#else
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#if !defined(AE_ERROR)
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typedef u32 acpi_status;
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#define AE_ERROR (acpi_status) (0x0001)
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#endif
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static inline acpi_status pci_osc_control_set(acpi_handle handle, u32 flags)
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{return AE_ERROR;}
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static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev *pdev)
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{ return NULL; }
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#endif
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@ -52,6 +52,7 @@
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#include <asm/atomic.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/irqreturn.h>
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/* Include the ID list */
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#include <linux/pci_ids.h>
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@ -93,6 +94,12 @@ enum {
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/* #6: expansion ROM resource */
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PCI_ROM_RESOURCE,
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/* device specific resources */
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#ifdef CONFIG_PCI_IOV
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PCI_IOV_RESOURCES,
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PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
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#endif
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/* resources assigned to buses behind the bridge */
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#define PCI_BRIDGE_RESOURCE_NUM 4
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@ -180,6 +187,7 @@ struct pci_cap_saved_state {
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struct pcie_link_state;
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struct pci_vpd;
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struct pci_sriov;
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/*
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* The pci_dev structure is used to describe PCI devices.
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@ -257,6 +265,8 @@ struct pci_dev {
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unsigned int is_managed:1;
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unsigned int is_pcie:1;
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unsigned int state_saved:1;
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unsigned int is_physfn:1;
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unsigned int is_virtfn:1;
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pci_dev_flags_t dev_flags;
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atomic_t enable_cnt; /* pci_enable_device has been called */
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@ -270,6 +280,12 @@ struct pci_dev {
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struct list_head msi_list;
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#endif
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struct pci_vpd *vpd;
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#ifdef CONFIG_PCI_IOV
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union {
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struct pci_sriov *sriov; /* SR-IOV capability related */
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struct pci_dev *physfn; /* the PF this VF is associated with */
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};
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#endif
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};
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extern struct pci_dev *alloc_pci_dev(void);
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@ -341,6 +357,15 @@ struct pci_bus {
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#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
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#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
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/*
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* Returns true if the pci bus is root (behind host-pci bridge),
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* false otherwise
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*/
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static inline bool pci_is_root_bus(struct pci_bus *pbus)
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{
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return !(pbus->parent);
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}
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#ifdef CONFIG_PCI_MSI
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static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
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{
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@ -528,7 +553,7 @@ void pcibios_update_irq(struct pci_dev *, int irq);
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/* Generic PCI functions used internally */
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extern struct pci_bus *pci_find_bus(int domain, int busnr);
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void pci_bus_add_devices(struct pci_bus *bus);
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void pci_bus_add_devices(const struct pci_bus *bus);
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struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
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struct pci_ops *ops, void *sysdata);
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static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
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@ -702,6 +727,9 @@ int pci_back_from_sleep(struct pci_dev *dev);
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/* Functions for PCI Hotplug drivers to use */
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int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
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#ifdef CONFIG_HOTPLUG
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unsigned int pci_rescan_bus(struct pci_bus *bus);
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#endif
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/* Vital product data routines */
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ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
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@ -709,7 +737,7 @@ ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void
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int pci_vpd_truncate(struct pci_dev *dev, size_t size);
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/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
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void pci_bus_assign_resources(struct pci_bus *bus);
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void pci_bus_assign_resources(const struct pci_bus *bus);
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void pci_bus_size_bridges(struct pci_bus *bus);
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int pci_claim_resource(struct pci_dev *, int);
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void pci_assign_unassigned_resources(void);
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@ -790,7 +818,7 @@ struct msix_entry {
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#ifndef CONFIG_PCI_MSI
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static inline int pci_enable_msi(struct pci_dev *dev)
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static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
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{
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return -1;
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}
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@ -800,6 +828,10 @@ static inline void pci_msi_shutdown(struct pci_dev *dev)
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static inline void pci_disable_msi(struct pci_dev *dev)
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{ }
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static inline int pci_msix_table_size(struct pci_dev *dev)
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{
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return 0;
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}
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static inline int pci_enable_msix(struct pci_dev *dev,
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struct msix_entry *entries, int nvec)
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{
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@ -821,9 +853,10 @@ static inline int pci_msi_enabled(void)
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return 0;
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}
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#else
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extern int pci_enable_msi(struct pci_dev *dev);
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extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
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extern void pci_msi_shutdown(struct pci_dev *dev);
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extern void pci_disable_msi(struct pci_dev *dev);
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extern int pci_msix_table_size(struct pci_dev *dev);
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extern int pci_enable_msix(struct pci_dev *dev,
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struct msix_entry *entries, int nvec);
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extern void pci_msix_shutdown(struct pci_dev *dev);
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@ -842,6 +875,8 @@ static inline int pcie_aspm_enabled(void)
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extern int pcie_aspm_enabled(void);
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#endif
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#define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
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#ifdef CONFIG_HT_IRQ
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/* The functions a driver should call */
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int ht_create_irq(struct pci_dev *dev, int idx);
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@ -1195,5 +1230,23 @@ int pci_ext_cfg_avail(struct pci_dev *dev);
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void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
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#ifdef CONFIG_PCI_IOV
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extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
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extern void pci_disable_sriov(struct pci_dev *dev);
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extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
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#else
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static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
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{
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return -ENODEV;
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}
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static inline void pci_disable_sriov(struct pci_dev *dev)
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{
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}
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static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
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{
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return IRQ_NONE;
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}
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#endif
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#endif /* __KERNEL__ */
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#endif /* LINUX_PCI_H */
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@ -2396,6 +2396,7 @@
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#define PCI_DEVICE_ID_INTEL_82801CA_12 0x248c
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#define PCI_DEVICE_ID_INTEL_82801DB_0 0x24c0
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#define PCI_DEVICE_ID_INTEL_82801DB_1 0x24c1
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#define PCI_DEVICE_ID_INTEL_82801DB_2 0x24c2
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#define PCI_DEVICE_ID_INTEL_82801DB_3 0x24c3
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#define PCI_DEVICE_ID_INTEL_82801DB_5 0x24c5
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#define PCI_DEVICE_ID_INTEL_82801DB_6 0x24c6
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@ -235,7 +235,7 @@
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#define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */
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#define PCI_PM_CTRL 4 /* PM control and status register */
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#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
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#define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 /* No reset for D3hot->D0 */
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#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
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#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
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#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
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#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
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@ -375,6 +375,7 @@
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#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
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#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
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#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
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#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */
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#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
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#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
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#define PCI_EXP_DEVCAP 4 /* Device capabilities */
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@ -487,6 +488,8 @@
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#define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */
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#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
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#define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */
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#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
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#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */
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/* Extended Capabilities (PCI-X 2.0 and Express) */
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#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
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@ -498,6 +501,7 @@
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#define PCI_EXT_CAP_ID_DSN 3
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#define PCI_EXT_CAP_ID_PWR 4
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#define PCI_EXT_CAP_ID_ARI 14
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#define PCI_EXT_CAP_ID_SRIOV 16
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/* Advanced Error Reporting */
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#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
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@ -615,4 +619,35 @@
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#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */
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#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */
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/* Single Root I/O Virtualization */
|
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#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
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#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */
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#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */
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#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
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#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */
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#define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */
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#define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */
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#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */
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#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */
|
||||
#define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */
|
||||
#define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */
|
||||
#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */
|
||||
#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
|
||||
#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */
|
||||
#define PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */
|
||||
#define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */
|
||||
#define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */
|
||||
#define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */
|
||||
#define PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */
|
||||
#define PCI_SRIOV_SYS_PGSIZE 0x20 /* System Page Size */
|
||||
#define PCI_SRIOV_BAR 0x24 /* VF BAR0 */
|
||||
#define PCI_SRIOV_NUM_BARS 6 /* Number of VF BARs */
|
||||
#define PCI_SRIOV_VFM 0x3c /* VF Migration State Array Offset*/
|
||||
#define PCI_SRIOV_VFM_BIR(x) ((x) & 7) /* State BIR */
|
||||
#define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) /* State Offset */
|
||||
#define PCI_SRIOV_VFM_UA 0x0 /* Inactive.Unavailable */
|
||||
#define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */
|
||||
#define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */
|
||||
#define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */
|
||||
|
||||
#endif /* LINUX_PCI_REGS_H */
|
||||
|
|
|
|||
|
|
@ -16,29 +16,30 @@
|
|||
#define PCIE_ANY_PORT 7
|
||||
|
||||
/* Service Type */
|
||||
#define PCIE_PORT_SERVICE_PME 1 /* Power Management Event */
|
||||
#define PCIE_PORT_SERVICE_AER 2 /* Advanced Error Reporting */
|
||||
#define PCIE_PORT_SERVICE_HP 4 /* Native Hotplug */
|
||||
#define PCIE_PORT_SERVICE_VC 8 /* Virtual Channel */
|
||||
#define PCIE_PORT_SERVICE_PME_SHIFT 0 /* Power Management Event */
|
||||
#define PCIE_PORT_SERVICE_PME (1 << PCIE_PORT_SERVICE_PME_SHIFT)
|
||||
#define PCIE_PORT_SERVICE_AER_SHIFT 1 /* Advanced Error Reporting */
|
||||
#define PCIE_PORT_SERVICE_AER (1 << PCIE_PORT_SERVICE_AER_SHIFT)
|
||||
#define PCIE_PORT_SERVICE_HP_SHIFT 2 /* Native Hotplug */
|
||||
#define PCIE_PORT_SERVICE_HP (1 << PCIE_PORT_SERVICE_HP_SHIFT)
|
||||
#define PCIE_PORT_SERVICE_VC_SHIFT 3 /* Virtual Channel */
|
||||
#define PCIE_PORT_SERVICE_VC (1 << PCIE_PORT_SERVICE_VC_SHIFT)
|
||||
|
||||
/* Root/Upstream/Downstream Port's Interrupt Mode */
|
||||
#define PCIE_PORT_NO_IRQ (-1)
|
||||
#define PCIE_PORT_INTx_MODE 0
|
||||
#define PCIE_PORT_MSI_MODE 1
|
||||
#define PCIE_PORT_MSIX_MODE 2
|
||||
|
||||
struct pcie_port_service_id {
|
||||
__u32 vendor, device; /* Vendor and device ID or PCI_ANY_ID*/
|
||||
__u32 subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
|
||||
__u32 class, class_mask; /* (class,subclass,prog-if) triplet */
|
||||
__u32 port_type, service_type; /* Port Entity */
|
||||
kernel_ulong_t driver_data;
|
||||
struct pcie_port_data {
|
||||
int port_type; /* Type of the port */
|
||||
int port_irq_mode; /* [0:INTx | 1:MSI | 2:MSI-X] */
|
||||
};
|
||||
|
||||
struct pcie_device {
|
||||
int irq; /* Service IRQ/MSI/MSI-X Vector */
|
||||
int interrupt_mode; /* [0:INTx | 1:MSI | 2:MSI-X] */
|
||||
struct pcie_port_service_id id; /* Service ID */
|
||||
struct pci_dev *port; /* Root/Upstream/Downstream Port */
|
||||
struct pci_dev *port; /* Root/Upstream/Downstream Port */
|
||||
u32 service; /* Port service this device represents */
|
||||
void *priv_data; /* Service Private Data */
|
||||
struct device device; /* Generic Device Interface */
|
||||
};
|
||||
|
|
@ -56,10 +57,9 @@ static inline void* get_service_data(struct pcie_device *dev)
|
|||
|
||||
struct pcie_port_service_driver {
|
||||
const char *name;
|
||||
int (*probe) (struct pcie_device *dev,
|
||||
const struct pcie_port_service_id *id);
|
||||
int (*probe) (struct pcie_device *dev);
|
||||
void (*remove) (struct pcie_device *dev);
|
||||
int (*suspend) (struct pcie_device *dev, pm_message_t state);
|
||||
int (*suspend) (struct pcie_device *dev);
|
||||
int (*resume) (struct pcie_device *dev);
|
||||
|
||||
/* Service Error Recovery Handler */
|
||||
|
|
@ -68,7 +68,9 @@ struct pcie_port_service_driver {
|
|||
/* Link Reset Capability - AER service driver specific */
|
||||
pci_ers_result_t (*reset_link) (struct pci_dev *dev);
|
||||
|
||||
const struct pcie_port_service_id *id_table;
|
||||
int port_type; /* Type of the port this driver can handle */
|
||||
u32 service; /* Port service this device represents */
|
||||
|
||||
struct device_driver driver;
|
||||
};
|
||||
#define to_service_driver(d) \
|
||||
|
|
|
|||
Loading…
Reference in a new issue