A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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Merge "ARM: dts: msm: Update all gdsc time out to 500 us"

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qctecmdr 2020-03-15 03:11:02 -07:00 • committed by Gerrit - the friendly Code Review server
commit e779c534b0
1 changed files with 19 additions and 0 deletions
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19
qcom/lahaina.dtsi
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@ -921,6 +921,7 @@
compatible = "qcom,gdsc";
reg = <0xad07004 0x4>;
regulator-name = "cam_cc_bps_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
@ -933,6 +934,7 @@
compatible = "qcom,gdsc";
reg = <0xad0a004 0x4>;
regulator-name = "cam_cc_ife_0_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
@ -944,6 +946,7 @@
compatible = "qcom,gdsc";
reg = <0xad0b004 0x4>;
regulator-name = "cam_cc_ife_1_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
@ -955,6 +958,7 @@
compatible = "qcom,gdsc";
reg = <0xad0b070 0x4>;
regulator-name = "cam_cc_ife_2_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
@ -966,6 +970,7 @@
compatible = "qcom,gdsc";
reg = <0xad08004 0x4>;
regulator-name = "cam_cc_ipe_0_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
@ -978,6 +983,7 @@
compatible = "qcom,gdsc";
reg = <0xad09004 0x4>;
regulator-name = "cam_cc_sbi_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
@ -989,6 +995,7 @@
compatible = "qcom,gdsc";
reg = <0xad0c120 0x4>;
regulator-name = "cam_cc_titan_top_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
@ -1001,6 +1008,7 @@
compatible = "qcom,gdsc";
reg = <0xaf03000 0x4>;
regulator-name = "disp_cc_mdss_core_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
@ -1016,6 +1024,7 @@
compatible = "qcom,gdsc";
reg = <0x16b004 0x4>;
regulator-name = "gcc_pcie_0_gdsc";
qcom,gds-timeout = <500>;
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
};
@ -1024,6 +1033,7 @@
compatible = "qcom,gdsc";
reg = <0x18d004 0x4>;
regulator-name = "gcc_pcie_1_gdsc";
qcom,gds-timeout = <500>;
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
};
@ -1032,6 +1042,7 @@
compatible = "qcom,gdsc";
reg = <0x175004 0x4>;
regulator-name = "gcc_ufs_card_gdsc";
qcom,gds-timeout = <500>;
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
};
@ -1040,6 +1051,7 @@
compatible = "qcom,gdsc";
reg = <0x177004 0x4>;
regulator-name = "gcc_ufs_phy_gdsc";
qcom,gds-timeout = <500>;
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
};
@ -1048,6 +1060,7 @@
compatible = "qcom,gdsc";
reg = <0x10f004 0x4>;
regulator-name = "gcc_usb30_prim_gdsc";
qcom,gds-timeout = <500>;
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
};
@ -1056,6 +1069,7 @@
compatible = "qcom,gdsc";
reg = <0x110004 0x4>;
regulator-name = "gcc_usb30_sec_gdsc";
qcom,gds-timeout = <500>;
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
};
@ -1124,6 +1138,7 @@
compatible = "qcom,gdsc";
reg = <0x3d9100c 0x4>;
regulator-name = "gpu_cc_gx_gdsc";
qcom,gds-timeout = <500>;
domain-addr = <&gpu_cc_gx_domain_addr>;
sw-reset = <&gpu_cc_gx_sw_reset>;
parent-supply = <&VDD_GFX_LEVEL>;
@ -1137,6 +1152,7 @@
compatible = "qcom,gdsc";
reg = <0xabf0d18 0x4>;
regulator-name = "video_cc_mvs0_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
@ -1149,6 +1165,7 @@
compatible = "qcom,gdsc";
reg = <0xabf0bf8 0x4>;
regulator-name = "video_cc_mvs0c_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
@ -1160,6 +1177,7 @@
compatible = "qcom,gdsc";
reg = <0xabf0d98 0x4>;
regulator-name = "video_cc_mvs1_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;
@ -1172,6 +1190,7 @@
compatible = "qcom,gdsc";
reg = <0xabf0c98 0x4>;
regulator-name = "video_cc_mvs1c_gdsc";
qcom,gds-timeout = <500>;
clock-names = "ahb_clk";
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
parent-supply = <&VDD_MM_LEVEL>;