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serial: 8250_pci: all known Braswell ports are 1 channel

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There is no need to have channel offset defined since all BayTrail and Braswell
ports are 1 channel. Remove unneeded definition.

While here, remove comment which has no value.

Signed-off-by: Andy Shevchenko <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
This commit is contained in:
Andy Shevchenko 2016-02-15 18:02:13 +02:00 • committed by Greg Kroah-Hartman
commit e78240152b
1 changed files with 0 additions and 5 deletions
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5
drivers/tty/serial/8250/8250_pci.c
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@ -3698,15 +3698,10 @@ static struct pciserial_board pci_boards[] = {
.base_baud = 921600,
.reg_shift = 2,
},
/*
* Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
* but is overridden by byt_set_termios.
*/
[pbn_byt] = {
.flags = FL_BASE0,
.num_ports = 1,
.base_baud = 2764800,
.uart_offset = 0x80,
.reg_shift = 2,
},
[pbn_qrk] = {