From e7d707464f44b57ca54bcace791f23fae24ef011 Mon Sep 17 00:00:00 2001 From: Nilesh Laad Date: Fri, 24 Mar 2023 18:25:16 +0530 Subject: [PATCH] disp: msm: dp: Convert clock operations to byte2 ops Convert clock operation to byte2 ops to meet DISPCC requirement. Clock unit is changed from KHZ to HZ. Added link clock parent as freq table is no longer supported in byte2 ops. Change-Id: Iefeca1ecf7fb6335c45f7664a661d1bbe2d6f1e5 Signed-off-by: Xiaowen Wu Signed-off-by: Soutrik Mukhopadhyay Signed-off-by: Nilesh Laad --- msm/dp/dp_ctrl.c | 8 ++++++++ msm/dp/dp_power.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/msm/dp/dp_ctrl.c b/msm/dp/dp_ctrl.c index 3a4f2badba58..395d5a7e1cc9 100644 --- a/msm/dp/dp_ctrl.c +++ b/msm/dp/dp_ctrl.c @@ -621,6 +621,14 @@ static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl, { u32 num = ctrl->parser->mp[clk_type].num_clk; struct dss_clk *cfg = ctrl->parser->mp[clk_type].clk_config; + struct dp_catalog *catalog; + + catalog = container_of(ctrl->catalog, struct dp_catalog, ctrl); + + if (catalog->hpd.is_edp) { + /* convert to HZ for byte2 ops */ + rate *= 1000; + } while (num && strcmp(cfg->clk_name, name)) { num--; diff --git a/msm/dp/dp_power.c b/msm/dp/dp_power.c index dd32941f84a7..254f32c36b53 100644 --- a/msm/dp/dp_power.c +++ b/msm/dp/dp_power.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ @@ -20,6 +21,8 @@ struct dp_power_private { struct clk *pixel_clk_rcg; struct clk *pixel_parent; struct clk *pixel1_clk_rcg; + struct clk *link_clk_rcg; + struct clk *link_parent; struct dp_power dp_power; @@ -229,6 +232,22 @@ static int dp_power_clk_init(struct dp_power_private *power, bool enable) goto err_pixel1_clk_rcg; } } + + power->link_clk_rcg = clk_get(dev, "link_clk_src"); + if (IS_ERR(power->link_clk_rcg)) { + DP_ERR("Unable to get DP link clk RCG: %ld\n", + PTR_ERR(power->link_clk_rcg)); + rc = 0; + power->link_clk_rcg = NULL; + } + + power->link_parent = clk_get(dev, "link_parent"); + if (IS_ERR(power->link_parent)) { + DP_ERR("Unable to get DP link parent: %ld\n", + PTR_ERR(power->link_parent)); + rc = 0; + power->link_parent = NULL; + } } else { if (power->pixel1_clk_rcg) clk_put(power->pixel1_clk_rcg); @@ -239,6 +258,12 @@ static int dp_power_clk_init(struct dp_power_private *power, bool enable) if (power->pixel_clk_rcg) clk_put(power->pixel_clk_rcg); + if (power->link_parent) + clk_put(power->link_parent); + + if (power->link_clk_rcg) + clk_put(power->link_clk_rcg); + dp_power_clk_put(power); } @@ -349,6 +374,14 @@ static int dp_power_clk_enable(struct dp_power *dp_power, } } + if (pm_type == DP_LINK_PM && enable && power->link_parent) { + rc = clk_set_parent(power->link_clk_rcg, power->link_parent); + if (rc) { + DP_ERR("failed to set link parent\n"); + goto error; + } + } + rc = dp_power_clk_set_rate(power, pm_type, enable); if (rc) { DP_ERR("failed to '%s' clks for: %s. err=%d\n",