From e7ff4a4ecfd7e4007eb8d79e0835ad34ff9e7e46 Mon Sep 17 00:00:00 2001 From: Siddartha Mohanadoss Date: Mon, 2 Nov 2020 17:32:50 -0800 Subject: [PATCH] msm: ep_pcie: Clear PERST_RAW_RESET_STATUS after link training Clear AOSS_CC_RESET_STATUS::PERST_RAW_RESET_STATUS after PCIe link training in HLOS. Failure to clear it in HLOS will result in PBL to consider it a controller reset pending state during warm reset and initiate a controller reset even if the PCIe link is up. Change-Id: I3e5b89181be29062f79e4c5ace1863124367c72c Signed-off-by: Siddartha Mohanadoss --- drivers/platform/msm/ep_pcie/ep_pcie_com.h | 3 +++ drivers/platform/msm/ep_pcie/ep_pcie_core.c | 20 +++++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_com.h b/drivers/platform/msm/ep_pcie/ep_pcie_com.h index c0859f5cf5ba..e880a5af8177 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_com.h +++ b/drivers/platform/msm/ep_pcie/ep_pcie_com.h @@ -245,6 +245,7 @@ enum ep_pcie_res { EP_PCIE_RES_IATU, EP_PCIE_RES_EDMA, EP_PCIE_RES_TCSR_PERST, + EP_PCIE_RES_AOSS_CC_RESET, EP_PCIE_MAX_RES, }; @@ -339,6 +340,7 @@ struct ep_pcie_dev_t { void __iomem *elbi; void __iomem *iatu; void __iomem *tcsr_perst_en; + void __iomem *aoss_rst_perst; struct msm_bus_scale_pdata *bus_scale_table; struct icc_path *icc_path; @@ -353,6 +355,7 @@ struct ep_pcie_dev_t { bool tcsr_not_supported; bool m2_autonomous; bool mhi_soc_reset_en; + bool aoss_rst_clear; u32 dbi_base_reg; u32 slv_space_reg; u32 phy_status_reg; diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_core.c b/drivers/platform/msm/ep_pcie/ep_pcie_core.c index 6ebc0e30d946..09558633aee7 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_core.c +++ b/drivers/platform/msm/ep_pcie/ep_pcie_core.c @@ -40,6 +40,7 @@ #define ICC_AVG_BW 500 #define ICC_PEAK_BW 800 +#define PERST_RAW_RESET_STATUS BIT(11) /* debug mask sys interface */ static int ep_pcie_debug_mask; @@ -97,6 +98,7 @@ static const struct ep_pcie_res_info_t ep_pcie_res_info[EP_PCIE_MAX_RES] = { {"iatu", NULL, NULL}, {"edma", NULL, NULL}, {"tcsr_pcie_perst_en", NULL, NULL}, + {"aoss_cc_reset", NULL, NULL}, }; static const struct ep_pcie_irq_info_t ep_pcie_irq_info[EP_PCIE_MAX_IRQ] = { @@ -1270,13 +1272,14 @@ static int ep_pcie_get_resources(struct ep_pcie_dev_t *dev, EP_PCIE_ERR(dev, "PCIe V%d: can't get resource for %s\n", dev->rev, res_info->name); - if (!strcmp(res_info->name, "tcsr_pcie_perst_en")) { - if (!dev->tcsr_not_supported) { + if (!strcmp(res_info->name, "tcsr_pcie_perst_en") || + (!strcmp(res_info->name, "aoss_reset_perst_raw"))) { + if (!dev->tcsr_not_supported && !dev->aoss_rst_clear) { ret = -ENOMEM; goto out; } } - dev->mmio_res_size = res->end = res->start; + dev->mmio_res_size = res->end = res->start; } else { EP_PCIE_DBG(dev, "start addr for %s is %pa\n", res_info->name, &res->start); @@ -1321,6 +1324,7 @@ static int ep_pcie_get_resources(struct ep_pcie_dev_t *dev, dev->elbi = dev->res[EP_PCIE_RES_ELBI].base; dev->iatu = dev->res[EP_PCIE_RES_IATU].base; dev->tcsr_perst_en = dev->res[EP_PCIE_RES_TCSR_PERST].base; + dev->aoss_rst_perst = dev->res[EP_PCIE_RES_AOSS_CC_RESET].base; out: kfree(clkfreq); @@ -1896,6 +1900,10 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt) } checkbme: + /* Clear AOSS_CC_RESET_STATUS::PERST_RAW_RESET_STATUS when linking up */ + if (dev->aoss_rst_clear) + writel_relaxed(PERST_RAW_RESET_STATUS, dev->aoss_rst_perst); + /* * De-assert WAKE# GPIO following link until L2/3 and WAKE# * is triggered to send data from device to host at which point @@ -3195,6 +3203,12 @@ static int ep_pcie_probe(struct platform_device *pdev) "PCIe V%d: tcsr pcie perst is %s supported\n", ep_pcie_dev.rev, ep_pcie_dev.tcsr_not_supported ? "not" : ""); + ep_pcie_dev.aoss_rst_clear = of_property_read_bool + ((&pdev->dev)->of_node, + "qcom,aoss-rst-clr"); + EP_PCIE_DBG(&ep_pcie_dev, + "PCIe V%d: AOSS reset for perst needed\n", ep_pcie_dev.rev); + ep_pcie_dev.rev = 1711211; ep_pcie_dev.pdev = pdev; ep_pcie_dev.m2_autonomous =