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Merge "bindings: clock: Add support clock controllers for SDXLEMUR"

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qctecmdr 2020-07-29 01:13:59 -07:00 • committed by Gerrit - the friendly Code Review server
commit e85c5b1fbe
3 changed files with 56 additions and 2 deletions
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9
bindings/clock/qcom,debugcc.txt
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@ -2,8 +2,13 @@ Qualcomm Technologies, Inc. Debug Clock Controller Binding
----------------------------------------------------------
Required properties :
- compatible: Shall contain "qcom,lahaina-debugcc" or "qcom,shima-debugcc"
or qcom,holi-debugcc.
- compatible: shall contain only one of the following:
"qcom,lahaina-debugcc"
"qcom,shima-debugcc"
"qcom,holi-debugcc"
"qcom,sdxlemur-debugcc"
- qcom,gcc: phandle to the GCC device node.
- qcom,videocc: phandle to the Video CC device node.
- qcom,camcc: phandle to the Camera CC device node.

1
bindings/clock/qcom,gcc.txt
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@ -30,6 +30,7 @@ Required properties :
"qcom,gcc-sa8155-v2"
"qcom,shima-gcc"
"qcom,holi-gcc"
"qcom,sdxlemur-gcc"
- reg : shall contain base register location and length
- vdd_cx-supply: The vdd_cx logic rail supply.

48
bindings/clock/qcom,sdxlemur-apsscc.txt Normal file
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@ -0,0 +1,48 @@
Qualcomm Technologies, Inc. SDXLEMUR CPU clock driver
-----------------------------------------------------
It is the clock controller driver which provides higher frequency
clocks and allows CPU frequency scaling on qcs405 based platforms.
Required properties:
- compatible: Shall contain following:
"qcom,sdxlemur-apsscc"
- clocks: Phandle to the clock device.
- clock-names: Names of the used clocks. Shall contain following:
"xo_ao", "gpll0_ao"
- reg: Shall contain base register offset and size.
- reg-names: Names of the bases for the above registers. Shall contain following:
"apcs_cmd", "apcs_pll"
- vdd_dig_ao-supply: The regulator(active only) powering the digital logic of APSS PLL.
- vdd_hf_pll-supply: The regulator(active only) powering the Analog logic of APSS PLL.
- cpu-vdd-supply: The regulator powering the APSS RCG.
- qcom,speedX-bin-vZ: A table of CPU frequency (Hz) to regulator voltage (uV) mapping.
Format: <freq uV>
This represents the max frequency possible for each possible
power configuration for a CPU that's binned as speed bin X,
speed bin revision Z. Version can be between [0-3].
- #clock-cells: Shall contain 1.
Optional properties:
- reg-names: "efuse"
- qcom,cpucc-init-rate: Initial rate which needs to be set from cpu driver.
Example:
clock_cpu: qcom,clock-cpu@17808100 {
compatible = "qcom,sdxlemur-apsscc";
clocks = <&rpmhcc RPMH_CXO_CLK>>;
<&gcc GPLL0_AO_OUT_MAIN>;;
clock-names = "xo_ao", "gpll0_ao" ;
reg = <0x17810008 0x8>,
<0x17808100 0x44>;
reg-names = "apcs_cmd" , "apcs_pll";
vdd-lucid-pll-supply = <&VDD_CX_LEVEL_AO>;
cpu-vdd-supply = <&VDD_CX_LEVEL_AO>;
qcom,speed0-bin-v0 =
< 0 RPMH_REGULATOR_LEVEL_OFF>,
< 345600000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
< 576000000 RPMH_REGULATOR_LEVEL_SVS>,
< 1094400000 RPMH_REGULATOR_LEVEL_NOM>,
< 1555200000 RPMH_REGULATOR_LEVEL_TURBO>;
#clock-cells = <1>;
};