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Merge "msm: pcie: correct PCIe1 and PCIe2 clock order"

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qctecmdr 2020-03-26 20:45:05 -07:00 • committed by Gerrit - the friendly Code Review server
commit e86a371037
1 changed files with 2 additions and 2 deletions
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4
drivers/pci/controller/pci-msm.c
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@ -886,9 +886,9 @@ static struct msm_pcie_clk_info_t
{NULL, "pcie_1_sleep_clk", 0, false, false},
{NULL, "pcie_phy_refgen_clk", 0, false, true},
{NULL, "pcie_tbu_clk", 0, false, true},
{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},
{NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false},
{NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false},
{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},
{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
{NULL, "pcie_phy_aux_clk", 0, false, false},
{NULL, "pcie_pipe_clk_mux", 0, false, false},
@ -906,9 +906,9 @@ static struct msm_pcie_clk_info_t
{NULL, "pcie_2_sleep_clk", 0, false, false},
{NULL, "pcie_phy_refgen_clk", 0, false, true},
{NULL, "pcie_tbu_clk", 0, false, true},
{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},
{NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false},
{NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false},
{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},
{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
{NULL, "pcie_phy_aux_clk", 0, false, false},
{NULL, "pcie_pipe_clk_mux", 0, false, false},