From e23780c60d60de0f963224cf0a07c67948047653 Mon Sep 17 00:00:00 2001 From: David Collins Date: Wed, 4 Dec 2019 15:04:35 -0800 Subject: [PATCH 1/4] dt-bindings: rtc: rtc-pm8xxx: Add binding documentation for pmk8350 rtc Add binding documentation for qcom,pmk8350-rtc which is used on Qualcomm Technologies, Inc. Lahaina boards. Change-Id: I555e22110b0f4a4d9b91c7dc3dcde876a625604c --- bindings/mfd/qcom-pm8xxx.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/mfd/qcom-pm8xxx.txt b/bindings/mfd/qcom-pm8xxx.txt index 9e5eba4a4f0d..07f49254f366 100644 --- a/bindings/mfd/qcom-pm8xxx.txt +++ b/bindings/mfd/qcom-pm8xxx.txt @@ -64,6 +64,7 @@ The below bindings specify the set of valid subnodes. "qcom,pm8921-rtc" "qcom,pm8941-rtc" "qcom,pm8018-rtc" + "qcom,pmk8350-rtc" - reg: Usage: required From f6ea1a1997a92b6e7297f1a8fc47d276e456be86 Mon Sep 17 00:00:00 2001 From: David Collins Date: Mon, 2 Dec 2019 17:48:05 -0800 Subject: [PATCH 2/4] ARM: dts: msm: add PMIC devices for Lahaina Add top level SPMI slave devices for PMK8350, PM8350, PM8350C, PM8350B, PMR735A, and PMR735B PMICs. Also add some of the peripheral devices within the SPMI slave devices. Change-Id: I06952059cc52652ca8a02d8c2fcfec2e6480eaff --- qcom/lahaina-cdp.dtsi | 1 + qcom/lahaina-mtp.dtsi | 1 + qcom/lahaina-pmic-overlay.dtsi | 8 +++++ qcom/lahaina-qrd.dtsi | 1 + qcom/lahaina-rumi.dtsi | 1 + qcom/lahaina.dtsi | 3 ++ qcom/pm8350.dtsi | 61 ++++++++++++++++++++++++++++++++++ qcom/pm8350b.dtsi | 61 ++++++++++++++++++++++++++++++++++ qcom/pm8350c.dtsi | 61 ++++++++++++++++++++++++++++++++++ qcom/pmk8350.dtsi | 38 +++++++++++++++++++++ qcom/pmr735a.dtsi | 61 ++++++++++++++++++++++++++++++++++ qcom/pmr735b.dtsi | 61 ++++++++++++++++++++++++++++++++++ 12 files changed, 358 insertions(+) create mode 100644 qcom/lahaina-pmic-overlay.dtsi create mode 100644 qcom/pm8350.dtsi create mode 100644 qcom/pm8350b.dtsi create mode 100644 qcom/pm8350c.dtsi create mode 100644 qcom/pmk8350.dtsi create mode 100644 qcom/pmr735a.dtsi create mode 100644 qcom/pmr735b.dtsi diff --git a/qcom/lahaina-cdp.dtsi b/qcom/lahaina-cdp.dtsi index e69de29bb2d1..c9c8940cf46b 100644 --- a/qcom/lahaina-cdp.dtsi +++ b/qcom/lahaina-cdp.dtsi @@ -0,0 +1 @@ +#include "lahaina-pmic-overlay.dtsi" diff --git a/qcom/lahaina-mtp.dtsi b/qcom/lahaina-mtp.dtsi index e69de29bb2d1..c9c8940cf46b 100644 --- a/qcom/lahaina-mtp.dtsi +++ b/qcom/lahaina-mtp.dtsi @@ -0,0 +1 @@ +#include "lahaina-pmic-overlay.dtsi" diff --git a/qcom/lahaina-pmic-overlay.dtsi b/qcom/lahaina-pmic-overlay.dtsi new file mode 100644 index 000000000000..e01ee2450d01 --- /dev/null +++ b/qcom/lahaina-pmic-overlay.dtsi @@ -0,0 +1,8 @@ +#include + +#include "pmk8350.dtsi" +#include "pm8350.dtsi" +#include "pm8350c.dtsi" +#include "pm8350b.dtsi" +#include "pmr735a.dtsi" +#include "pmr735b.dtsi" diff --git a/qcom/lahaina-qrd.dtsi b/qcom/lahaina-qrd.dtsi index e69de29bb2d1..c9c8940cf46b 100644 --- a/qcom/lahaina-qrd.dtsi +++ b/qcom/lahaina-qrd.dtsi @@ -0,0 +1 @@ +#include "lahaina-pmic-overlay.dtsi" diff --git a/qcom/lahaina-rumi.dtsi b/qcom/lahaina-rumi.dtsi index baf5e635a33c..268916beb1cc 100644 --- a/qcom/lahaina-rumi.dtsi +++ b/qcom/lahaina-rumi.dtsi @@ -1,4 +1,5 @@ #include "lahaina.dtsi" +#include "lahaina-pmic-overlay.dtsi" &ufsphy_mem { compatible = "qcom,ufs-phy-qrbtc-sdm845"; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 186edb981295..b58c7b57e3af 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -874,6 +874,9 @@ qcom,retain-regs; }; + thermal_zones: thermal-zones { + }; + cache-controller@9200000 { compatible = "qcom,lahaina-llcc", "qcom,llcc-v2"; reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>; diff --git a/qcom/pm8350.dtsi b/qcom/pm8350.dtsi new file mode 100644 index 000000000000..1b79409a0e74 --- /dev/null +++ b/qcom/pm8350.dtsi @@ -0,0 +1,61 @@ +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm8350@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8350_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8350_gpios: pinctrl@8800 { + compatible = "qcom,pm8350-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&thermal_zones { + pm8350_temp_alarm: pm8350_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8350_tz>; + + trips { + pm8350_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8350_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8350_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/pm8350b.dtsi b/qcom/pm8350b.dtsi new file mode 100644 index 000000000000..aeeb5680dc75 --- /dev/null +++ b/qcom/pm8350b.dtsi @@ -0,0 +1,61 @@ +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm8350b@3 { + compatible = "qcom,spmi-pmic"; + reg = <3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8350b_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8350b_gpios: pinctrl@8800 { + compatible = "qcom,pm8350b-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&thermal_zones { + pm8350b_temp_alarm: pm8350b_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8350b_tz>; + + trips { + pm8350b_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8350b_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8350b_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/pm8350c.dtsi b/qcom/pm8350c.dtsi new file mode 100644 index 000000000000..ed51205ade31 --- /dev/null +++ b/qcom/pm8350c.dtsi @@ -0,0 +1,61 @@ +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm8350c@2 { + compatible = "qcom,spmi-pmic"; + reg = <2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8350c_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8350c_gpios: pinctrl@8800 { + compatible = "qcom,pm8350c-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&thermal_zones { + pm8350c_temp_alarm: pm8350c_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8350c_tz>; + + trips { + pm8350c_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8350c_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8350c_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/pmk8350.dtsi b/qcom/pmk8350.dtsi new file mode 100644 index 000000000000..355dedbd2c30 --- /dev/null +++ b/qcom/pmk8350.dtsi @@ -0,0 +1,38 @@ +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pmk8350@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmk8350_sdam_2: sdam@7100 { + compatible = "qcom,spmi-sdam"; + reg = <0x7100>; + }; + + pmk8350_gpios: pinctrl@b000 { + compatible = "qcom,pmk8350-gpio"; + reg = <0xb000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmk8350_rtc: rtc@6100 { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, <0x6200>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + }; + }; +}; diff --git a/qcom/pmr735a.dtsi b/qcom/pmr735a.dtsi new file mode 100644 index 000000000000..3e8ca911ad2a --- /dev/null +++ b/qcom/pmr735a.dtsi @@ -0,0 +1,61 @@ +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pmr735a@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmr735a_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmr735a_gpios: pinctrl@8800 { + compatible = "qcom,pmr735a-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&thermal_zones { + pmr735a_temp_alarm: pmr735a_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pmr735a_tz>; + + trips { + pmr735a_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pmr735a_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + pmr735a_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/pmr735b.dtsi b/qcom/pmr735b.dtsi new file mode 100644 index 000000000000..b1050bf06072 --- /dev/null +++ b/qcom/pmr735b.dtsi @@ -0,0 +1,61 @@ +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pmr735b@5 { + compatible = "qcom,spmi-pmic"; + reg = <5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmr735b_tz: qcom,temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmr735b_gpios: pinctrl@8800 { + compatible = "qcom,pmr735b-gpio"; + reg = <0x8800>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&thermal_zones { + pmr735b_temp_alarm: pmr735b_tz { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pmr735b_tz>; + + trips { + pmr735b_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pmr735b_trip1: trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "passive"; + }; + + pmr735b_trip2: trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; +}; From 0fe72f90685b9ac9f25aa2902b9a6b1c85a11e15 Mon Sep 17 00:00:00 2001 From: David Collins Date: Mon, 2 Dec 2019 17:02:52 -0800 Subject: [PATCH 3/4] ARM: dts: msm: add SPMI debug bus for Lahaina boards Add an SPMI debug bus device and associated child devices so that consumers can have unrestricted access to the PMICs on pre-production devices. This helps to make debugging easier. Change-Id: Ie0e7150bedd3b791344acaafd9f557dd9e1ff302 --- qcom/lahaina-cdp.dtsi | 4 +++ qcom/lahaina-mtp.dtsi | 4 +++ qcom/lahaina-qrd.dtsi | 4 +++ qcom/lahaina-rumi.dtsi | 4 +++ qcom/lahaina.dtsi | 61 ++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 77 insertions(+) diff --git a/qcom/lahaina-cdp.dtsi b/qcom/lahaina-cdp.dtsi index c9c8940cf46b..2e3ab49ddbbe 100644 --- a/qcom/lahaina-cdp.dtsi +++ b/qcom/lahaina-cdp.dtsi @@ -1 +1,5 @@ #include "lahaina-pmic-overlay.dtsi" + +&spmi_debug_bus { + status = "ok"; +}; diff --git a/qcom/lahaina-mtp.dtsi b/qcom/lahaina-mtp.dtsi index c9c8940cf46b..2e3ab49ddbbe 100644 --- a/qcom/lahaina-mtp.dtsi +++ b/qcom/lahaina-mtp.dtsi @@ -1 +1,5 @@ #include "lahaina-pmic-overlay.dtsi" + +&spmi_debug_bus { + status = "ok"; +}; diff --git a/qcom/lahaina-qrd.dtsi b/qcom/lahaina-qrd.dtsi index c9c8940cf46b..2e3ab49ddbbe 100644 --- a/qcom/lahaina-qrd.dtsi +++ b/qcom/lahaina-qrd.dtsi @@ -1 +1,5 @@ #include "lahaina-pmic-overlay.dtsi" + +&spmi_debug_bus { + status = "ok"; +}; diff --git a/qcom/lahaina-rumi.dtsi b/qcom/lahaina-rumi.dtsi index 268916beb1cc..25f5de69b125 100644 --- a/qcom/lahaina-rumi.dtsi +++ b/qcom/lahaina-rumi.dtsi @@ -1,6 +1,10 @@ #include "lahaina.dtsi" #include "lahaina-pmic-overlay.dtsi" +&spmi_debug_bus { + status = "ok"; +}; + &ufsphy_mem { compatible = "qcom,ufs-phy-qrbtc-sdm845"; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index b58c7b57e3af..ccb480bd094f 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -1203,6 +1204,66 @@ qcom,ee = <0>; }; + spmi_debug_bus: qcom,spmi-debug@6b12000 { + compatible = "qcom,spmi-pmic-arb-debug"; + reg = <0x6b12000 0x60>, <0x7820a8 0x4>; + reg-names = "core", "fuse"; + clocks = <&clock_aop QDSS_CLK>; + clock-names = "core_clk"; + qcom,fuse-disable-bit = <24>; + #address-cells = <2>; + #size-cells = <0>; + status = "disabled"; + + qcom,pmk8350-debug@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8350-debug@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8350c-debug@2 { + compatible = "qcom,spmi-pmic"; + reg = <2 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pm8350b-debug@3 { + compatible = "qcom,spmi-pmic"; + reg = <3 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pmr735a-debug@4 { + compatible = "qcom,spmi-pmic"; + reg = <4 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + + qcom,pmr735b-debug@5 { + compatible = "qcom,spmi-pmic"; + reg = <5 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + qcom,can-sleep; + }; + }; + qcom,msm-cdsp-loader { compatible = "qcom,cdsp-loader"; qcom,proc-img-to-load = "cdsp"; From 5d48fb40b76c9af60bf9921cf979befdf48590ba Mon Sep 17 00:00:00 2001 From: David Collins Date: Thu, 5 Dec 2019 13:45:57 -0800 Subject: [PATCH 4/4] dt-bindings: input: add qpnp-power-on bindings Add device tree bindings for Qualcomm Technologies, Inc. QPNP Power-on devices. These are PMIC peripherals which manage PMIC power on, power off, key presses, and other related activities. Change-Id: I07ae4e7e4505b8f4973520532106401ca9f76beb --- bindings/input/qpnp-power-on.txt | 247 +++++++++++++++++++++++++++++++ 1 file changed, 247 insertions(+) create mode 100644 bindings/input/qpnp-power-on.txt diff --git a/bindings/input/qpnp-power-on.txt b/bindings/input/qpnp-power-on.txt new file mode 100644 index 000000000000..d935a2a443d3 --- /dev/null +++ b/bindings/input/qpnp-power-on.txt @@ -0,0 +1,247 @@ +Qualcomm Technologies, Inc. QPNP Power-on PMIC Peripheral Device Tree Bindings + +qpnp-power-on devices support the power-on (PON) peripheral found on +Qualcomm Technologies, Inc. PMICs. The supported functionality includes power +on/off reason, key press/release detection, PMIC reset configurations and other +PON specific features. The PON module supports multiple physical power-on +(KPDPWR_N, CBLPWR) and reset (KPDPWR_N, RESIN, KPDPWR+RESIN) sources. This +peripheral is connected to the host processor via the SPMI interface. + +Required properties: +- compatible: Must be "qcom,qpnp-power-on" +- reg: Specifies the SPMI base address for this PON + (power-on) peripheral. + +Optional properties: +- interrupts: Specifies the interrupts associated with PON. +- interrupt-names: Specifies the interrupt names associated with + the interrupts property. Must be a subset of + "kpdpwr", "kpdpwr-bark", "resin", "resin-bark", + "cblpwr", "kpdpwr-resin-bark", and + "pmic-wd-bark". Bark interrupts are associated + with system reset configuration to allow default + reset configuration to be activated. If system + reset configuration is not supported then bark + interrupts are nops. Additionally, the + "pmic-wd-bark" interrupt can be added if the + system needs to handle PMIC watchdog barks. +- qcom,pon-dbc-delay: The debounce delay for the power-key interrupt + specified in us. + Possible values for GEN1 PON are: + 15625, 31250, 62500, 125000, 250000, 500000, + 1000000 and 2000000. + Possible values for GEN2 PON are: + 62, 123, 245, 489, 977, 1954, 3907, 7813, + 15625, 31250, 62500, 125000 and 250000. + Intermediate value is rounded down to the + nearest valid value. +- qcom,system-reset: Boolean which specifies that this PON peripheral + can be used to reset the system. This property + can only be used by one device on the system. It + is an error to include it more than once. +- qcom,modem-reset: Boolean which specifies that this PON peripheral + can be used to reset the attached modem chip. + This property can only be used by one PON device + on the system. qcom,modem-reset and + qcom,system-reset cannot be specified for the + same PON device. +- qcom,s3-debounce: The debounce delay for stage 3 reset trigger in + secs. The values range from 0 to 128. +- qcom,s3-src: The source for stage 3 reset. It can be one of + "kpdpwr", "resin", "kpdpwr-or-resin" or + "kpdpwr-and-resin". +- qcom,uvlo-panic: Boolean indicating that the device should + trigger a controlled panic shutdown if a restart + was caused by under voltage lock-out (UVLO). +- qcom,clear-warm-reset: Boolean which specifies that the WARM_RESET + reason registers need to be cleared for this + target. The property is used for the targets + which have a hardware feature to catch resets + which aren't triggered by the application + processor. In such cases clearing WARM_REASON + registers across processor resets keeps the + registers in a useful state. +- qcom,secondary-pon-reset: Boolean property which indicates that the PON + peripheral is a secondary PON device which + needs to be configured during reset in addition + to the primary PON device that is configured + for system reset through qcom,system-reset + property. + This should not be defined along with the + qcom,system-reset or qcom,modem-reset property. +- qcom,store-hard-reset-reason: Boolean property which if set will store the + hardware reset reason to SOFT_RB_SPARE register + of the core PMIC PON peripheral. +- qcom,warm-reset-poweroff-type: Poweroff type required to be configured + on PS_HOLD reset control register when the + system goes for warm reset. If this property is + not specified, then the default type, warm reset + will be configured to PS_HOLD reset control + register. + Supported values: PON_POWER_OFF_TYPE_* found in + include/dt-bindings/input/qcom,qpnp-power-on.h +- qcom,hard-reset-poweroff-type: Same description as + qcom,warm-reset-poweroff-type but this applies + for the system hard reset case. +- qcom,shutdown-poweroff-type: Same description as qcom,warm-reset-poweroff- + type but this applies for the system shutdown + case. +- qcom,kpdpwr-sw-debounce: Boolean property to enable the debounce logic + on the KPDPWR_N rising edge. +- qcom,resin-pon-reset: Boolean property which indicates that resin + needs to be configured during reset in addition + to the primary PON device that is configured + for system reset through qcom,system-reset + property. +- qcom,resin-warm-reset-type: Poweroff type required to be configured on + RESIN reset control register when the system + initiates warm reset. If this property is not + specified, then the default type, warm reset + will be configured to RESIN reset control + register. This property is effective only if + qcom,resin-pon-reset is defined. + Supported values: PON_POWER_OFF_TYPE_* found in + include/dt-bindings/input/qcom,qpnp-power-on.h +- qcom,resin-hard-reset-type: Same description as qcom,resin-warm-reset-type + but this applies for the system hard reset case. +- qcom,resin-shutdown-type: Same description as qcom,resin-warm-reset-type + but this applies for the system shutdown case. +- qcom,resin-shutdown-disable: Boolean property to disable RESIN power off + trigger during system shutdown case. + This property is effective only if + qcom,resin-pon-reset is defined. +- qcom,resin-hard-reset-disable: Boolean property to disable RESIN power + off trigger during system hard reset case. + This property is effective only if + qcom,resin-pon-reset is defined. +- qcom,ps-hold-shutdown-disable: Boolean property to disable PS_HOLD + power off trigger during system shutdown case. +- qcom,ps-hold-hard-reset-disable: Boolean property to disable PS_HOLD + power off trigger during system hard reset case. + +Optional Sub-nodes: +- qcom,pon_1 ... qcom,pon_n: These PON child nodes correspond to features + supported by the PON peripheral including reset + configurations, pushbutton keys, and regulators. + +Sub-node properties: + +Sub-nodes (if defined) should belong to either a PON configuration or a +regulator configuration. + +Regulator sub-node required properties: +- regulator-name: Regulator name for the PON regulator that is + being configured. +- qcom,pon-spare-reg-addr: Register offset from the base address of the + PON peripheral that needs to be configured for + the regulator being controlled. +- qcom,pon-spare-reg-bit: Bit position in the specified register that + needs to be configured for the regulator being + controlled. + +PON sub-node required properties: +- qcom,pon-type: The type of PON/RESET source. Supported values: + 0 = KPDPWR + 1 = RESIN + 2 = CBLPWR + 3 = KPDPWR_RESIN + These values are PON_POWER_ON_TYPE_* found in + include/dt-bindings/input/qcom,qpnp-power-on.h + +PON sub-node optional properties: +- qcom,pull-up: Boolean flag indicating if a pull-up resistor + should be enabled for the input. +- qcom,support-reset: Indicates if this PON source supports + reset functionality. + 0 = Not supported + 1 = Supported + If this property is not defined, then default S2 + reset configurations should not be modified. +- qcom,use-bark: Specify if this PON type needs to handle a bark + interrupt. +- linux,code: The input key-code associated with the reset + source. The reset source in its default + configuration can be used to support standard + keys. + +The below mentioned properties are required only when qcom,support-reset DT +property is defined and is set to 1. + +- qcom,s1-timer: The debounce timer for the BARK interrupt for + the reset source. Value is specified in ms. + Supported values are: + 0, 32, 56, 80, 128, 184, 272, 408, 608, 904, + 1352, 2048, 3072, 4480, 6720, 10256 +- qcom,s2-timer: The debounce timer for the S2 reset specified + in ms. On the expiry of this timer, the PMIC + executes the reset sequence. + Supported values are: + 0, 10, 50, 100, 250, 500, 1000, 2000 +- qcom,s2-type: The type of reset associated with this source. + Supported values: + 0 = SOFT_RESET (legacy) + 1 = WARM_RESET + 4 = SHUTDOWN + 5 = DVDD_SHUTDOWN + 7 = HARD_RESET + 8 = DVDD_HARD_RESET + These values are PON_POWER_OFF_TYPE_* found in + include/dt-bindings/input/qcom,qpnp-power-on.h + +Examples: + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x8 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x8 0x5 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "kpdpwr", "resin", "resin-bark", + "kpdpwr-resin-bark"; + qcom,pon-dbc-delay = <15625>; + qcom,system-reset; + qcom,s3-debounce = <32>; + qcom,s3-src = "resin"; + qcom,clear-warm-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = ; + qcom,pull-up; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + qcom,support-reset = <1>; + qcom,pull-up; + qcom,s1-timer = <0>; + qcom,s2-timer = <2000>; + qcom,s2-type = ; + linux,code = ; + qcom,use-bark; + }; + + qcom,pon_3 { + qcom,pon-type = ; + qcom,support-reset = <1>; + qcom,s1-timer = <6720>; + qcom,s2-timer = <2000>; + qcom,s2-type = ; + qcom,pull-up; + qcom,use-bark; + }; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800>; + qcom,secondary-pon-reset; + qcom,hard-reset-poweroff-type = ; + + pon_perph_reg: qcom,pon_perph_reg { + regulator-name = "pon_spare_reg"; + qcom,pon-spare-reg-addr = <0x8c>; + qcom,pon-spare-reg-bit = <1>; + }; + };