From e8ca9d4eee66a37e15493abca64f463712ba5eb5 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Fri, 6 Nov 2020 09:22:55 +0530 Subject: [PATCH] ARM: dts: msm: Add clock controller and gdsc nodes for sm8150 Add support for all the clock controllers and also add gdsc regulators. Change-Id: Ic313db887845e43c1d69b82f6bd8af4154145832 --- qcom/sa8155-regulator.dtsi | 1 + qcom/sa8155-v1.dtsi | 20 +++ qcom/sa8155-v2.dtsi | 20 +++ qcom/sa8155.dtsi | 13 ++ qcom/sm8150-gdsc.dtsi | 254 +++++++++++++++++++++++++++++++ qcom/sm8150-regulator.dtsi | 1 + qcom/sm8150-v2.dtsi | 24 +++ qcom/sm8150.dtsi | 296 +++++++++++++++++++++++++++++++++++-- 8 files changed, 620 insertions(+), 9 deletions(-) create mode 100644 qcom/sm8150-gdsc.dtsi diff --git a/qcom/sa8155-regulator.dtsi b/qcom/sa8155-regulator.dtsi index a3575be84b12..5685f98c665a 100644 --- a/qcom/sa8155-regulator.dtsi +++ b/qcom/sa8155-regulator.dtsi @@ -344,6 +344,7 @@ rpmh-regulator-gfxlvl { compatible = "qcom,rpmh-arc-regulator"; qcom,resource-name = "gfx.lvl"; + VDD_GFX_LEVEL: S3C_LEVEL: pm8150_2_s3_level: regulator-pm8150-2-s3-level { regulator-name = "pm8150_2_s3_level"; qcom,set = ; diff --git a/qcom/sa8155-v1.dtsi b/qcom/sa8155-v1.dtsi index 50d09d7a5ba4..1e52e3797265 100644 --- a/qcom/sa8155-v1.dtsi +++ b/qcom/sa8155-v1.dtsi @@ -7,3 +7,23 @@ qcom,msm-name = "SA8155 V1"; qcom,msm-id = <362 0x10000>; }; + +&scc { + compatible = "qcom,sa8155-scc", "syscon"; +}; + +&gcc { + compatible = "qcom,sa8155-gcc", "syscon"; +}; + +&videocc { + compatible = "qcom,sa8155-videocc", "syscon"; +}; + +&npucc { + compatible = "qcom,sa8155-npucc", "syscon"; +}; + +&camcc { + compatible = "qcom,sa8155-camcc", "syscon"; +}; diff --git a/qcom/sa8155-v2.dtsi b/qcom/sa8155-v2.dtsi index 09d9488c0872..f995a319af99 100644 --- a/qcom/sa8155-v2.dtsi +++ b/qcom/sa8155-v2.dtsi @@ -6,3 +6,23 @@ qcom,msm-name = "SA8155 V2"; qcom,msm-id = <362 0x20000>; }; + +&scc { + compatible = "qcom,sa8155-scc-v2", "syscon"; +}; + +&gcc { + compatible = "qcom,sa8155-gcc-v2", "syscon"; +}; + +&videocc { + compatible = "qcom,sa8155-videocc-v2", "syscon"; +}; + +&npucc { + compatible = "qcom,sa8155-npucc-v2", "syscon"; +}; + +&camcc { + compatible = "qcom,sa8155-camcc-v2", "syscon"; +}; diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index b048176d4cbb..a3fcc5063c04 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -55,3 +55,16 @@ /* Add regulator nodes specific to SA8155 */ #include "sa8155-regulator.dtsi" + +&gpucc { + compatible = "qcom,sa8155-gpucc", "syscon"; +}; + +&scc { + vdd_scc_cx-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_gx_gdsc { + parent-supply = <&VDD_GFX_LEVEL>; +}; diff --git a/qcom/sm8150-gdsc.dtsi b/qcom/sm8150-gdsc.dtsi new file mode 100644 index 000000000000..07d8e929ce7a --- /dev/null +++ b/qcom/sm8150-gdsc.dtsi @@ -0,0 +1,254 @@ +&soc { + /* GDSCs in Global CC */ + emac_gdsc: qcom,gdsc@106004 { + compatible = "qcom,gdsc"; + regulator-name = "emac_gdsc"; + reg = <0x106004 0x4>; + status = "disabled"; + }; + + pcie_0_gdsc: qcom,gdsc@16b004 { + compatible = "qcom,gdsc"; + regulator-name = "pcie_0_gdsc"; + reg = <0x16b004 0x4>; + status = "disabled"; + }; + + pcie_1_gdsc: qcom,gdsc@18d004 { + compatible = "qcom,gdsc"; + regulator-name = "pcie_1_gdsc"; + reg = <0x18d004 0x4>; + status = "disabled"; + }; + + ufs_card_gdsc: qcom,gdsc@175004 { + compatible = "qcom,gdsc"; + regulator-name = "ufs_card_gdsc"; + reg = <0x175004 0x4>; + status = "disabled"; + }; + + ufs_phy_gdsc: qcom,gdsc@177004 { + compatible = "qcom,gdsc"; + regulator-name = "ufs_phy_gdsc"; + reg = <0x177004 0x4>; + status = "disabled"; + }; + + usb30_prim_gdsc: qcom,gdsc@10f004 { + compatible = "qcom,gdsc"; + regulator-name = "usb30_prim_gdsc"; + reg = <0x10f004 0x4>; + status = "disabled"; + }; + + usb30_sec_gdsc: qcom,gdsc@110004 { + compatible = "qcom,gdsc"; + regulator-name = "usb30_sec_gdsc"; + reg = <0x110004 0x4>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc: qcom,gdsc@17d040 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc"; + reg = <0x17d040 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_tbu1_gdsc: qcom,gdsc@17d044 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc"; + reg = <0x17d044 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_tbu2_gdsc: qcom,gdsc@17d048 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc"; + reg = <0x17d048 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc: qcom,gdsc@17d04c { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc"; + reg = <0x17d04c 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc"; + reg = <0x17d050 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@17d054 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc"; + reg = <0x17d054 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc"; + reg = <0x17d058 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@17d05c { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc"; + reg = <0x17d05c 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@17d060 { + compatible = "qcom,gdsc"; + regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc"; + reg = <0x17d060 0x4>; + qcom,no-status-check-on-disable; + qcom,gds-timeout = <500>; + status = "disabled"; + }; + + /* GDSCs in Camera CC */ + bps_gdsc: qcom,gdsc@ad07004 { + compatible = "qcom,gdsc"; + regulator-name = "bps_gdsc"; + reg = <0xad07004 0x4>; + status = "disabled"; + }; + + ipe_0_gdsc: qcom,gdsc@ad08004 { + compatible = "qcom,gdsc"; + regulator-name = "ipe_0_gdsc"; + reg = <0xad08004 0x4>; + status = "disabled"; + }; + + ipe_1_gdsc: qcom,gdsc@ad09004 { + compatible = "qcom,gdsc"; + regulator-name = "ipe_1_gdsc"; + reg = <0xad09004 0x4>; + status = "disabled"; + }; + + ife_0_gdsc: qcom,gdsc@ad0a004 { + compatible = "qcom,gdsc"; + regulator-name = "ife_0_gdsc"; + reg = <0xad0a004 0x4>; + status = "disabled"; + }; + + ife_1_gdsc: qcom,gdsc@ad0b004 { + compatible = "qcom,gdsc"; + regulator-name = "ife_1_gdsc"; + reg = <0xad0b004 0x4>; + status = "disabled"; + }; + + titan_top_gdsc: qcom,gdsc@ad0c1bc { + compatible = "qcom,gdsc"; + regulator-name = "titan_top_gdsc"; + reg = <0xad0c1bc 0x4>; + status = "disabled"; + }; + + /* GDSCs in Display CC */ + mdss_core_gdsc: qcom,gdsc@af03000 { + compatible = "qcom,gdsc"; + regulator-name = "mdss_core_gdsc"; + reg = <0xaf03000 0x4>; + qcom,support-hw-trigger; + status = "disabled"; + proxy-supply = <&mdss_core_gdsc>; + qcom,proxy-consumer-enable; + }; + + /* GDSCs in Graphics CC */ + gpu_cx_hw_ctrl: syscon@2c91540 { + compatible = "syscon"; + reg = <0x2c91540 0x4>; + }; + + gpu_cx_gdsc: qcom,gdsc@2c9106c { + compatible = "qcom,gdsc"; + regulator-name = "gpu_cx_gdsc"; + reg = <0x2c9106c 0x4>; + hw-ctrl-addr = <&gpu_cx_hw_ctrl>; + qcom,skip-disable; + qcom,gds-timeout = <500>; + qcom,clk-dis-wait-val = <8>; + mboxes = <&qmp_aop 0>; + status = "disabled"; + }; + + gpu_gx_domain_addr: syscon@2c91508 { + compatible = "syscon"; + reg = <0x2c91508 0x4>; + }; + + gpu_gx_sw_reset: syscon@2c91008 { + compatible = "syscon"; + reg = <0x2c91008 0x4>; + }; + + gpu_gx_gdsc: qcom,gdsc@2c9100c { + compatible = "qcom,gdsc"; + regulator-name = "gpu_gx_gdsc"; + reg = <0x2c9100c 0x4>; + domain-addr = <&gpu_gx_domain_addr>; + sw-reset = <&gpu_gx_sw_reset>; + qcom,reset-aon-logic; + status = "disabled"; + }; + + /* GDSCs in Video CC */ + mvsc_gdsc: qcom,gdsc@ab00814 { + compatible = "qcom,gdsc"; + regulator-name = "mvsc_gdsc"; + reg = <0xab00814 0x4>; + status = "disabled"; + }; + + mvs0_gdsc: qcom,gdsc@ab00874 { + compatible = "qcom,gdsc"; + regulator-name = "mvs0_gdsc"; + reg = <0xab00874 0x4>; + status = "disabled"; + }; + + mvs1_gdsc: qcom,gdsc@ab008b4 { + compatible = "qcom,gdsc"; + regulator-name = "mvs1_gdsc"; + reg = <0xab008b4 0x4>; + status = "disabled"; + }; + + /* GDSCs in NPU CC */ + npu_core_gdsc: qcom,gdsc@9911028 { + compatible = "qcom,gdsc"; + regulator-name = "npu_core_gdsc"; + reg = <0x9911028 0x4>; + status = "disabled"; + }; +}; diff --git a/qcom/sm8150-regulator.dtsi b/qcom/sm8150-regulator.dtsi index b03ebd06ffe3..8cb0baf556e8 100644 --- a/qcom/sm8150-regulator.dtsi +++ b/qcom/sm8150-regulator.dtsi @@ -450,6 +450,7 @@ rpmh-regulator-gfxlvl { compatible = "qcom,rpmh-arc-regulator"; qcom,resource-name = "gfx.lvl"; + VDD_GFX_LEVEL: S2C_LEVEL: pm8150l_s2_level: regulator-pm8150l-s2-level { regulator-name = "pm8150l_s2_level"; qcom,set = ; diff --git a/qcom/sm8150-v2.dtsi b/qcom/sm8150-v2.dtsi index 3f6b99c92e77..a7ec31ec4fa3 100644 --- a/qcom/sm8150-v2.dtsi +++ b/qcom/sm8150-v2.dtsi @@ -5,3 +5,27 @@ qcom,msm-name = "SM8150 V2"; qcom,msm-id = <339 0x20000>; }; + +&gcc { + compatible = "qcom,sm8150-gcc-v2", "syscon"; +}; + +&camcc { + compatible = "qcom,sm8150-camcc-v2", "syscon"; +}; + +&dispcc { + compatible = "qcom,sm8150-dispcc-v2", "syscon"; +}; + +&videocc { + compatible = "qcom,sm8150-videocc-v2", "syscon"; +}; + +&npucc { + compatible = "qcom,sm8150-npucc-v2", "syscon"; +}; + +&scc { + compatible = "qcom,sm8150-scc-v2", "syscon"; +}; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index fcb8a87066b1..50f901d5282a 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1,3 +1,11 @@ +#include +#include +#include +#include +#include +#include +#include +#include #include #include #include @@ -701,24 +709,138 @@ }; + aopcc: qcom,aopcc { + compatible = "qcom,aop-qmp-clk"; + mboxes = <&qmp_aop 0>; + mbox-names = "qdss_clk"; + #clock-cells = <1>; + }; + gcc: clock-controller@100000 { - compatible = "qcom,gcc-sm8150"; - reg = <0x00100000 0x1f0000>; + compatible = "qcom,sm8150-gcc", "syscon"; + reg = <0x100000 0x1f0000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>; + clock-names = "bi_tcxo", "bi_tcxo_ao"; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; + }; + + videocc: clock-controller@ab00000 { + compatible = "qcom,sm8150-videocc", "syscon"; + reg = <0xab00000 0x10000>; + reg-names = "cc_base"; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + clocks = <&gcc GCC_VIDEO_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_ahb_clk", "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + camcc: clock-controller@ad00000 { + compatible = "qcom,sm8150-camcc", "syscon"; + reg = <0xad00000 0x10000>; + reg-names = "cc_base"; + vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_ahb_clk", "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8150-dispcc", "syscon"; + reg = <0xaf00000 0x20000>; + reg-names = "cc_base"; + vdd_mm-supply = <&VDD_MMCX_LEVEL>; + clocks = <&gcc GCC_DISP_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_ahb_clk", "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + npucc: clock-controller@9910000 { + compatible = "qcom,sm8150-npucc", "syscon"; + reg = <0x9910000 0x10000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_gdsc-supply = <&npu_core_gdsc>; + clocks = + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_NPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_NPU_GPLL0_CLK_SRC>, + <&gcc GCC_NPU_AXI_CLK>; + clock-names = + "bi_tcxo", + "gcc_npu_gpll0_div_clk_src", + "gcc_npu_gpll0_clk_src", + "gcc_npu_axi_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@2c90000 { + compatible = "qcom,sm8150-gpucc", "syscon"; + reg = <0x2c90000 0x9000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MX_LEVEL>; + clocks = + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; clock-names = "bi_tcxo", - "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>; + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + scc: clock-controller@2b10000 { + compatible = "qcom,sm8150-scc", "syscon"; + reg = <0x2b10000 0x30000>; + vdd_scc_cx-supply = <&pm8150_l8_level>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + status = "disabled"; + }; + + cpucc: syscon@182a0018 { + compatible = "syscon"; + reg = <0x182a0000 0x4>; + }; + + mccc: syscon@90b0000 { + compatible = "syscon"; + reg = <0x90b0000 0x1000>; + }; + + debugcc: debug-clock-controller@0 { + compatible = "qcom,sm8150-debugcc"; + qcom,gcc = <&gcc>; + qcom,videocc = <&videocc>; + qcom,camcc = <&camcc>; + qcom,dispcc = <&dispcc>; + qcom,npucc = <&npucc>; + qcom,gpucc = <&gpucc>; + qcom,cpucc = <&cpucc>; + qcom,mccc = <&mccc>; + clock-names = "xo_clk_src"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; }; qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x00ac0000 0x6000>; clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc 123>, - <&gcc 124>; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; ranges; #address-cells = <2>; #size-cells = <2>; @@ -729,7 +851,7 @@ compatible = "qcom,geni-debug-uart"; reg = <0x0 0x00a90000 0x0 0x4000>; clock-names = "se"; - clocks = <&gcc 105>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; interrupts = ; status = "ok"; }; @@ -1112,3 +1234,159 @@ #include "sm8150-pm.dtsi" #include "sm8150-slpi-pinctrl.dtsi" #include "sm8150-smp2p.dtsi" +#include "sm8150-gdsc.dtsi" + +&emac_gdsc { + status = "ok"; +}; + +&pcie_0_gdsc { + status = "ok"; +}; + +&pcie_1_gdsc { + status = "ok"; +}; + +&ufs_phy_gdsc { + status = "ok"; +}; + +&ufs_card_gdsc { + status = "ok"; +}; + +&usb30_prim_gdsc { + status = "ok"; +}; + +&usb30_sec_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu1_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_tbu2_gdsc { + status = "ok"; +}; + +&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc { + status = "ok"; +}; + +&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu0_gdsc { + status = "ok"; +}; + +&hlos1_vote_turing_mmu_tbu1_gdsc { + status = "ok"; +}; + +&bps_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&ipe_0_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&ipe_1_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&ife_0_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&ife_1_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&titan_top_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_CAMERA_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&mdss_core_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_DISP_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&gpu_cx_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; +}; + +&gpu_gx_gdsc { + parent-supply = <&VDD_GFX_LEVEL>; + status = "ok"; +}; + +&mvsc_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + status = "ok"; +}; + +&mvs0_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&mvs1_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_VIDEO_AHB_CLK>; + parent-supply = <&VDD_MMCX_LEVEL>; + qcom,support-hw-trigger; + status = "ok"; +}; + +&npu_core_gdsc { + clock-names = "ahb_clk"; + clocks = <&gcc GCC_NPU_CFG_AHB_CLK>; + status = "ok"; +};