From 994dc07f420a829f81f5039d1c7fdd52a4424720 Mon Sep 17 00:00:00 2001
From: Hareesh Gundu <hareeshg@qti.qualcomm.com>
Date: Fri, 29 Jan 2021 20:45:50 +0530
Subject: [PATCH] ARM: dts: msm: Add l3 endpoints and pwrlevels for yupik gpu

Add the l3 endpoints as well as the frequency table to be
able to vote for l3 for gpu usecases that need l3 scaling.

Change-Id: I48789c3f7b387f7cb2e24f179678307e3516b300
---
 qcom/yupik-gpu.dtsi | 31 +++++++++++++++++++++++++++----
 1 file changed, 27 insertions(+), 4 deletions(-)

diff --git a/qcom/yupik-gpu.dtsi b/qcom/yupik-gpu.dtsi
index d5e981c7300f..4a7357b398a3 100644
--- a/qcom/yupik-gpu.dtsi
+++ b/qcom/yupik-gpu.dtsi
@@ -46,10 +46,14 @@
 		qcom,min-access-length = <32>;
 		qcom,ubwc-mode = <3>;
 
+		nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>;
+		nvmem-cell-names = "speed_bin", "gaming_bin";
+
 		qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr";
 
-		interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
-		interconnect-names = "gpu_icc_path";
+		interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>,
+			<&epss_l3_cpu MASTER_EPSS_L3_APPS &epss_l3_cpu SLAVE_EPSS_L3_SHARED>;
+		interconnect-names = "gpu_icc_path", "l3_path";
 
 		qcom,bus-table-ddr7 =
 			<MHZ_TO_KBPS(0, 4)>,    /* index=0 */
@@ -82,8 +86,27 @@
 			<0>,   /* Off */
 			<100>; /* On */
 
-		nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>;
-		nvmem-cell-names = "speed_bin", "gaming_bin";
+		qcom,l3-pwrlevels {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			compatible = "qcom,l3-pwrlevels";
+
+			qcom,l3-pwrlevel@0 {
+				reg = <0>;
+				qcom,l3-freq = <0>;
+			};
+
+			qcom,l3-pwrlevel@1 {
+				reg = <1>;
+				qcom,l3-freq = <614400000>;
+			};
+
+			qcom,l3-pwrlevel@2 {
+				reg = <2>;
+				qcom,l3-freq = <1516800000>;
+			};
+		};
 
 		qcom,gpu-mempools {
 			#address-cells = <1>;