mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 19:21:31 -04:00
ARM: arm64: Devicetree updates for v4.14
As usual, device tree updates is the bulk of our material in this merge
window. This time around, 559 patches affecting both 32- and 64-bit
platforms.
Changes are too many to list individually, but some of the larger ones:
New platform/SoC support:
- Automotive:
+ Renesas R-Car D3 (R8A77995)
+ TI DT76x
+ MediaTek mt2712e
- Communication-oriented:
+ Qualcomm IPQ8074
+ Broadcom Stingray
+ Marvell Armada 8080
- Set top box:
+ Uniphier PXs3
Besides some vendor reference boards for the SoC above, there are also several
new boards/machines:
- TI AM335x Moxa UC-8100-ME-T open platform
- TI AM57xx Beaglebone X15 Rev C
- Microchip/Atmel sama5d27 SoM1 EK
- Broadcom Raspberry Pi Zero W
- Gemini-based D-Link DIR-685 router
- Freescale i.MX6:
+ Toradex Apalis module + Apalis and Ixora carrier boards
+ Engicam GEAM6UL Starter Kit
- Freescale i.MX53-based Beckhoff CX9020 Embedded PC
- Mediatek mt7623-based BananaPi R2
- Several Allwinner-based single-board computers:
+ Cubietruck plus
+ Bananapi M3, M2M and M64
+ NanoPi A64
+ A64-OLinuXino
+ Pine64
- Rockchip RK3328 Pine64/Rock64 board support
- Rockchip RK3399 boards:
+ RK3399 Sapphire module on Excavator carrier (RK3399 reference design)
+ Theobroma Systems RK3399-Q7 SoM
- ZTE ZX296718 PCBOX Board
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Merge tag 'armsoc-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM/arm64 Devicetree updates from Olof Johansson:
"As usual, device tree updates is the bulk of our material in this
merge window. This time around, 559 patches affecting both 32- and
64-bit platforms.
Changes are too many to list individually, but some of the larger
ones:
New platform/SoC support:
- Automotive:
+ Renesas R-Car D3 (R8A77995)
+ TI DT76x
+ MediaTek mt2712e
- Communication-oriented:
+ Qualcomm IPQ8074
+ Broadcom Stingray
+ Marvell Armada 8080
- Set top box:
+ Uniphier PXs3
Besides some vendor reference boards for the SoC above, there are also
several new boards/machines:
- TI AM335x Moxa UC-8100-ME-T open platform
- TI AM57xx Beaglebone X15 Rev C
- Microchip/Atmel sama5d27 SoM1 EK
- Broadcom Raspberry Pi Zero W
- Gemini-based D-Link DIR-685 router
- Freescale i.MX6:
+ Toradex Apalis module + Apalis and Ixora carrier boards
+ Engicam GEAM6UL Starter Kit
- Freescale i.MX53-based Beckhoff CX9020 Embedded PC
- Mediatek mt7623-based BananaPi R2
- Several Allwinner-based single-board computers:
+ Cubietruck plus
+ Bananapi M3, M2M and M64
+ NanoPi A64
+ A64-OLinuXino
+ Pine64
- Rockchip RK3328 Pine64/Rock64 board support
- Rockchip RK3399 boards:
+ RK3399 Sapphire module on Excavator carrier (RK3399 reference design)
+ Theobroma Systems RK3399-Q7 SoM
- ZTE ZX296718 PCBOX Board"
* tag 'armsoc-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (559 commits)
ARM: dts: at91: at91sam9g45: add AC97
arm64: dts: marvell: mcbin: enable more networking ports
arm64: dts: marvell: add a reference to the sysctrl syscon in the ppv2 node
arm64: dts: marvell: add TX interrupts for PPv2.2
arm64: dts: uniphier: add PXs3 SoC support
ARM: dts: uniphier: add pinctrl groups of ethernet phy mode
ARM: dts: uniphier: fix size of sdctrl nodes
ARM: dts: uniphier: add AIDET nodes
arm64: dts: uniphier: fix size of sdctrl node
arm64: dts: uniphier: add AIDET nodes
Revert "ARM: dts: sun8i: h3: Enable dwmac-sun8i on the Beelink X2"
arm64: dts: uniphier: add reset controller node of analog amplifier
arm64: dts: marvell: add Device Tree files for Armada-8KP
arm64: dts: rockchip: add Haikou baseboard with RK3399-Q7 SoM
arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM
dt-bindings: add rk3399-q7 SoM
ARM: dts: rockchip: enable usb for rv1108-evb
ARM: dts: rockchip: add usb nodes for rv1108 SoCs
dt-bindings: update grf-binding for rv1108 SoCs
ARM: dts: aspeed-g4: fix AHB window size of the SMC controllers
...
This commit is contained in:
Linus Torvalds
commit
e90937e756
487 changed files with 22378 additions and 2316 deletions
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@ -1188,6 +1188,7 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
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[CLKID_32K_CLK] = &gxbb_32k_clk.hw,
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[CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
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[CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
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[NR_CLKS] = NULL,
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},
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.num = NR_CLKS,
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};
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@ -1310,6 +1311,7 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
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[CLKID_32K_CLK] = &gxbb_32k_clk.hw,
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[CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
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[CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
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[NR_CLKS] = NULL,
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},
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.num = NR_CLKS,
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};
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@ -167,130 +167,33 @@
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* CLKID index values
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*
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* These indices are entirely contrived and do not map onto the hardware.
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* Migrate them out of this header and into the DT header file when they need
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* to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h
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* It has now been decided to expose everything by default in the DT header:
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* include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
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* to expose, such as the internal muxes and dividers of composite clocks,
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* will remain defined here.
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*/
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#define CLKID_SYS_PLL 0
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/* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */
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/* CLKID_HDMI_PLL */
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#define CLKID_FIXED_PLL 3
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/* CLKID_FCLK_DIV2 */
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/* CLKID_FCLK_DIV3 */
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/* CLKID_FCLK_DIV4 */
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#define CLKID_FCLK_DIV5 7
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#define CLKID_FCLK_DIV7 8
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/* CLKID_GP0_PLL */
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#define CLKID_MPEG_SEL 10
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#define CLKID_MPEG_DIV 11
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/* CLKID_CLK81 */
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#define CLKID_MPLL0 13
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#define CLKID_MPLL1 14
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/* CLKID_MPLL2 */
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#define CLKID_DDR 16
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#define CLKID_DOS 17
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#define CLKID_ISA 18
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#define CLKID_PL301 19
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#define CLKID_PERIPHS 20
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/* CLKID_SPICC */
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/* CLKID_I2C */
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/* #define CLKID_SAR_ADC */
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#define CLKID_SMART_CARD 24
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/* CLKID_RNG0 */
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/* CLKID_UART0 */
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#define CLKID_SDHC 27
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#define CLKID_STREAM 28
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#define CLKID_ASYNC_FIFO 29
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#define CLKID_SDIO 30
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#define CLKID_ABUF 31
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#define CLKID_HIU_IFACE 32
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#define CLKID_ASSIST_MISC 33
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/* CLKID_SPI */
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#define CLKID_I2S_SPDIF 35
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/* CLKID_ETH */
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#define CLKID_DEMUX 37
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/* CLKID_AIU_GLUE */
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/* CLKID_IEC958 */
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/* CLKID_I2S_OUT */
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#define CLKID_AMCLK 41
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#define CLKID_AIFIFO2 42
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#define CLKID_MIXER 43
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/* CLKID_MIXER_IFACE */
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#define CLKID_ADC 45
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#define CLKID_BLKMV 46
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/* CLKID_AIU */
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/* CLKID_UART1 */
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#define CLKID_G2D 49
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/* CLKID_USB0 */
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/* CLKID_USB1 */
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#define CLKID_RESET 52
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#define CLKID_NAND 53
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#define CLKID_DOS_PARSER 54
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/* CLKID_USB */
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#define CLKID_VDIN1 56
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#define CLKID_AHB_ARB0 57
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#define CLKID_EFUSE 58
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#define CLKID_BOOT_ROM 59
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#define CLKID_AHB_DATA_BUS 60
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#define CLKID_AHB_CTRL_BUS 61
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#define CLKID_HDMI_INTR_SYNC 62
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/* CLKID_HDMI_PCLK */
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/* CLKID_USB1_DDR_BRIDGE */
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/* CLKID_USB0_DDR_BRIDGE */
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#define CLKID_MMC_PCLK 66
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#define CLKID_DVIN 67
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/* CLKID_UART2 */
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/* #define CLKID_SANA */
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#define CLKID_VPU_INTR 70
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#define CLKID_SEC_AHB_AHB3_BRIDGE 71
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#define CLKID_CLK81_A53 72
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#define CLKID_VCLK2_VENCI0 73
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#define CLKID_VCLK2_VENCI1 74
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#define CLKID_VCLK2_VENCP0 75
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#define CLKID_VCLK2_VENCP1 76
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/* CLKID_GCLK_VENCI_INT0 */
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#define CLKID_GCLK_VENCI_INT 78
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#define CLKID_DAC_CLK 79
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/* CLKID_AOCLK_GATE */
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/* CLKID_IEC958_GATE */
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#define CLKID_ENC480P 82
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#define CLKID_RNG1 83
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#define CLKID_GCLK_VENCI_INT1 84
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#define CLKID_VCLK2_VENCLMCC 85
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#define CLKID_VCLK2_VENCL 86
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#define CLKID_VCLK_OTHER 87
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#define CLKID_EDP 88
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#define CLKID_AO_MEDIA_CPU 89
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#define CLKID_AO_AHB_SRAM 90
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#define CLKID_AO_AHB_BUS 91
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#define CLKID_AO_IFACE 92
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/* CLKID_AO_I2C */
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/* CLKID_SD_EMMC_A */
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/* CLKID_SD_EMMC_B */
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/* CLKID_SD_EMMC_C */
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/* CLKID_SAR_ADC_CLK */
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/* CLKID_SAR_ADC_SEL */
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#define CLKID_SAR_ADC_DIV 99
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/* CLKID_MALI_0_SEL */
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#define CLKID_MALI_0_DIV 101
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/* CLKID_MALI_0 */
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/* CLKID_MALI_1_SEL */
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#define CLKID_MALI_1_DIV 104
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/* CLKID_MALI_1 */
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/* CLKID_MALI */
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/* CLKID_CTS_AMCLK */
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#define CLKID_MALI_0_DIV 101
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#define CLKID_MALI_1_DIV 104
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#define CLKID_CTS_AMCLK_SEL 108
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#define CLKID_CTS_AMCLK_DIV 109
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/* CLKID_CTS_MCLK_I958 */
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#define CLKID_CTS_MCLK_I958_SEL 111
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#define CLKID_CTS_MCLK_I958_DIV 112
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/* CLKID_CTS_I958 */
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#define CLKID_32K_CLK 114
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#define CLKID_32K_CLK_SEL 115
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#define CLKID_32K_CLK_DIV 116
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#define CLKID_SD_EMMC_A_CLK0_SEL 117
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#define CLKID_SD_EMMC_A_CLK0_DIV 118
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#define CLKID_SD_EMMC_B_CLK0_SEL 120
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#define CLKID_SD_EMMC_B_CLK0_DIV 121
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#define CLKID_SD_EMMC_C_CLK0_SEL 123
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#define CLKID_SD_EMMC_C_CLK0_DIV 124
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#define NR_CLKS 117
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#define NR_CLKS 126
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/* include the CLKIDs that have been made part of the stable DT binding */
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/* include the CLKIDs that have been made part of the DT binding */
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#include <dt-bindings/clock/gxbb-clkc.h>
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#endif /* __GXBB_H */
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@ -590,6 +590,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
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[CLKID_MPLL0] = &meson8b_mpll0.hw,
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[CLKID_MPLL1] = &meson8b_mpll1.hw,
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[CLKID_MPLL2] = &meson8b_mpll2.hw,
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[CLK_NR_CLKS] = NULL,
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},
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.num = CLK_NR_CLKS,
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};
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@ -60,107 +60,12 @@
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* CLKID index values
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*
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* These indices are entirely contrived and do not map onto the hardware.
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* Migrate them out of this header and into the DT header file when they need
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* to be exposed to client nodes in DT: include/dt-bindings/clock/meson8b-clkc.h
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* It has now been decided to expose everything by default in the DT header:
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* include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
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* to expose, such as the internal muxes and dividers of composite clocks,
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* will remain defined here.
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*/
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/* CLKID_UNUSED */
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/* CLKID_XTAL */
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/* CLKID_PLL_FIXED */
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/* CLKID_PLL_VID */
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/* CLKID_PLL_SYS */
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/* CLKID_FCLK_DIV2 */
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/* CLKID_FCLK_DIV3 */
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/* CLKID_FCLK_DIV4 */
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/* CLKID_FCLK_DIV5 */
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/* CLKID_FCLK_DIV7 */
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/* CLKID_CLK81 */
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/* CLKID_MALI */
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/* CLKID_CPUCLK */
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/* CLKID_ZERO */
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/* CLKID_MPEG_SEL */
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/* CLKID_MPEG_DIV */
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#define CLKID_DDR 16
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#define CLKID_DOS 17
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#define CLKID_ISA 18
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#define CLKID_PL301 19
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#define CLKID_PERIPHS 20
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#define CLKID_SPICC 21
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#define CLKID_I2C 22
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/* #define CLKID_SAR_ADC */
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#define CLKID_SMART_CARD 24
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/* #define CLKID_RNG0 */
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#define CLKID_UART0 26
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#define CLKID_SDHC 27
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#define CLKID_STREAM 28
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#define CLKID_ASYNC_FIFO 29
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/* #define CLKID_SDIO */
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#define CLKID_ABUF 31
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#define CLKID_HIU_IFACE 32
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#define CLKID_ASSIST_MISC 33
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#define CLKID_SPI 34
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#define CLKID_I2S_SPDIF 35
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/* #define CLKID_ETH */
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#define CLKID_DEMUX 37
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#define CLKID_AIU_GLUE 38
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#define CLKID_IEC958 39
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#define CLKID_I2S_OUT 40
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#define CLKID_AMCLK 41
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#define CLKID_AIFIFO2 42
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#define CLKID_MIXER 43
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#define CLKID_MIXER_IFACE 44
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#define CLKID_ADC 45
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#define CLKID_BLKMV 46
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#define CLKID_AIU 47
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#define CLKID_UART1 48
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#define CLKID_G2D 49
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/* #define CLKID_USB0 */
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/* #define CLKID_USB1 */
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#define CLKID_RESET 52
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#define CLKID_NAND 53
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#define CLKID_DOS_PARSER 54
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/* #define CLKID_USB */
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#define CLKID_VDIN1 56
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#define CLKID_AHB_ARB0 57
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#define CLKID_EFUSE 58
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#define CLKID_BOOT_ROM 59
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#define CLKID_AHB_DATA_BUS 60
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#define CLKID_AHB_CTRL_BUS 61
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#define CLKID_HDMI_INTR_SYNC 62
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#define CLKID_HDMI_PCLK 63
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/* CLKID_USB1_DDR_BRIDGE */
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/* CLKID_USB0_DDR_BRIDGE */
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#define CLKID_MMC_PCLK 66
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#define CLKID_DVIN 67
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#define CLKID_UART2 68
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/* #define CLKID_SANA */
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#define CLKID_VPU_INTR 70
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#define CLKID_SEC_AHB_AHB3_BRIDGE 71
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#define CLKID_CLK81_A9 72
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#define CLKID_VCLK2_VENCI0 73
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#define CLKID_VCLK2_VENCI1 74
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#define CLKID_VCLK2_VENCP0 75
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#define CLKID_VCLK2_VENCP1 76
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#define CLKID_GCLK_VENCI_INT 77
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#define CLKID_GCLK_VENCP_INT 78
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#define CLKID_DAC_CLK 79
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#define CLKID_AOCLK_GATE 80
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#define CLKID_IEC958_GATE 81
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#define CLKID_ENC480P 82
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#define CLKID_RNG1 83
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#define CLKID_GCLK_VENCL_INT 84
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#define CLKID_VCLK2_VENCLMCC 85
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#define CLKID_VCLK2_VENCL 86
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#define CLKID_VCLK2_OTHER 87
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#define CLKID_EDP 88
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#define CLKID_AO_MEDIA_CPU 89
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#define CLKID_AO_AHB_SRAM 90
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#define CLKID_AO_AHB_BUS 91
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#define CLKID_AO_IFACE 92
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#define CLKID_MPLL0 93
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#define CLKID_MPLL1 94
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#define CLKID_MPLL2 95
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#define CLK_NR_CLKS 96
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/* include the CLKIDs that have been made part of the stable DT binding */
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