From e916f4a7b9eb0eb0478026c0c2c43a6eb50356b9 Mon Sep 17 00:00:00 2001
From: Tony Truong <truong@quicinc.com>
Date: Thu, 30 Jan 2020 13:49:19 -0800
Subject: [PATCH] ARM: dts: msm: enable PCIe0 and PCIe1 on lahaina

Enable PCIe0 and PCIe1 on lahaina.

Change-Id: I9b57d69184e69494f8f6b18e8fd6a52114bc790b
---
 qcom/lahaina-pcie.dtsi | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi
index 734e5c043cac..0fccbda6c6b2 100644
--- a/qcom/lahaina-pcie.dtsi
+++ b/qcom/lahaina-pcie.dtsi
@@ -163,8 +163,6 @@
 				0x0200 0x00 0x0
 				0x0244 0x03 0x0>;
 
-		status = "disabled";
-
 		pcie0_rp: pcie0_rp {
 			reg = <0 0 0 0 0>;
 		};
@@ -379,8 +377,6 @@
 				0x0200 0x00 0x0
 				0x0244 0x03 0x0>;
 
-		status = "disabled";
-
 		pcie1_rp: pcie1_rp {
 			reg = <0 0 0 0 0>;
 		};