From 0f10f878e88af23778c212e6326122e66679a769 Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Wed, 28 Apr 2021 11:39:18 +0530 Subject: [PATCH] ARM: dts: msm: Update clock frequenices for PCIe 2nd instance Clock frequencies for PCIe 2nd instance are not passed correctly due to which frequency for pcie1_phy_rchng_clk is not set to 100MHz. This results in link training fail in Gen3 speed. Hence update clock frequencies passed for PCIe 2nd instance to fix the issue. Change-Id: I3065ebf725ecd8980057588e7bf93cb8ccedf51a --- qcom/yupik-pcie.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/yupik-pcie.dtsi b/qcom/yupik-pcie.dtsi index 66476baf7f8b..557d9d49725f 100644 --- a/qcom/yupik-pcie.dtsi +++ b/qcom/yupik-pcie.dtsi @@ -365,7 +365,8 @@ "pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src"; max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, - <0>, <0>, <0>, <0>, <0>, <0>, <100000000>, <0>; + <0>, <0>, <0>, <0>, <100000000>, <0>, + <0>, <0>, <0>, <0>; resets = <&gcc GCC_PCIE_1_BCR>, <&gcc GCC_PCIE_1_PHY_BCR>;