From e9fad773e64af1d192e840e59b38a7dddc2eed4e Mon Sep 17 00:00:00 2001 From: Harshdeep Dhatt Date: Tue, 11 Feb 2020 14:05:31 -0700 Subject: [PATCH] msm: kgsl: Clear halt before gmu boot During hard reset if we are not able to toggle the CX gdsc, the halt will remain asserted at the time of next GMU boot. This causes GMU boot to fail and lead to NoC errors. So clear the halt bit before attempting GMU boot. Also, move the wptr retention out among the rest of the register writes instead of piling them inside a6xx_gmu_start(). Change-Id: Id214e0a9261c1f14de13864c715cf1a9d415e1e7 Signed-off-by: Harshdeep Dhatt --- drivers/gpu/msm/adreno_a6xx_gmu.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.c b/drivers/gpu/msm/adreno_a6xx_gmu.c index 3b2951f2be1d..59a54ea76e45 100644 --- a/drivers/gpu/msm/adreno_a6xx_gmu.c +++ b/drivers/gpu/msm/adreno_a6xx_gmu.c @@ -351,10 +351,6 @@ static int a6xx_gmu_start(struct kgsl_device *device) mask = 0xFFFFFFFF; } - /* Set the log wptr index */ - gmu_core_regwrite(device, A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, - gmu->log_wptr_retention); - /* Bring GMU out of reset */ gmu_core_regwrite(device, A6XX_GMU_CM3_SYSRESET, 0); @@ -1069,6 +1065,18 @@ static int a6xx_gmu_fw_start(struct kgsl_device *device, */ gmu_core_regwrite(device, A6XX_GMU_CM3_CFG, 0x4052); + /** + * We may have asserted gbif halt as part of reset sequence which may + * not get cleared if the gdsc was not reset. So clear it before + * attempting GMU boot. + */ + if (!adreno_is_a630(ADRENO_DEVICE(device))) + kgsl_regwrite(device, A6XX_GBIF_HALT, 0x0); + + /* Set the log wptr index */ + gmu_core_regwrite(device, A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, + gmu->log_wptr_retention); + /* Pass chipid to GMU FW, must happen before starting GMU */ /* Keep Core and Major bitfields unchanged */