mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-13 00:00:00 -04:00
ARM: dts: msm: Add changes for PCIe0 RC enablement for yupik
Add required dtsi changes for PCIe0 RC enablement for yupik. Change-Id: I323eb39d39f1bc4df9540c71a79f2e1c5fe3a2c4
This commit is contained in:
Vijayavardhan Vennapusa
parent
376ea4e156
commit
e9ff546612
3 changed files with 327 additions and 0 deletions
272
qcom/yupik-pcie.dtsi
Normal file
272
qcom/yupik-pcie.dtsi
Normal file
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@ -0,0 +1,272 @@
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#include <dt-bindings/clock/qcom,gcc-yupik.h>
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&soc {
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pcie0: qcom,pcie@1c00000 {
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compatible = "qcom,pci-msm";
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reg = <0x01c00000 0x3000>,
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<0x01c06000 0x1000>,
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<0x60000000 0xf1d>,
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<0x60000f20 0xa8>,
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<0x60001000 0x1000>,
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<0x60100000 0x100000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
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cell-index = <0>;
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
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<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
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interrupt-parent = <&pcie0>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
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0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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msi-parent = <&pcie0_msi>;
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perst-gpio = <&tlmm 87 0>;
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wake-gpio = <&tlmm 89 0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie0_perst_default
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&pcie0_clkreq_default
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&pcie0_wake_default>;
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pinctrl-1 = <&pcie0_perst_default
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&pcie0_clkreq_sleep
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&pcie0_wake_default>;
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gdsc-vdd-supply = <&gcc_pcie_0_gdsc>;
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vreg-1p8-supply = <&L6B>;
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vreg-0p9-supply = <&L10C>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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qcom,vreg-1p8-voltage-level = <1200000 1200000 15000>;
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qcom,vreg-0p9-voltage-level = <880000 880000 47900>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,bw-scale = /* Gen1 */
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<RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen2 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen3 */
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RPMH_REGULATOR_LEVEL_NOM
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RPMH_REGULATOR_LEVEL_LOW_SVS
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100000000>;
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interconnect-names = "icc_path";
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interconnects = <&aggre1_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_CLKREF_EN>,
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<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
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<&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
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<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
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<&pcie_0_pipe_clk>;
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clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
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"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
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"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
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"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
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"pcie_tbu_clk", "pcie_phy_refgen_clk",
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"pcie_ddrss_sf_tbu_clk",
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"pcie_aggre_noc_0_axi_clk",
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"pcie_aggre_noc_1_axi_clk", "pcie_pipe_clk_mux",
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"pcie_pipe_clk_ext_src";
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max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
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<0>, <0>, <0>, <0>, <100000000>, <0>,
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<0>, <0>, <0>, <0>;
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resets = <&gcc GCC_PCIE_0_BCR>,
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<&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "pcie_0_core_reset",
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"pcie_0_phy_reset";
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dma-coherent;
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qcom,smmu-sid-base = <0x1C00>;
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iommu-map = <0x0 &apps_smmu 0x1C00 0x1>,
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<0x100 &apps_smmu 0x1C01 0x1>;
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qcom,boot-option = <0x1>;
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qcom,drv-supported;
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qcom,drv-l1ss-timeout-us = <10000>;
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qcom,use-19p2mhz-aux-clk;
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qcom,no-l0s-supported;
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qcom,l1-2-th-scale = <2>;
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qcom,l1-2-th-value = <70>;
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qcom,slv-addr-space-size = <0x4000000>;
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qcom,ep-latency = <10>;
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qcom,phy-manage-pll = <1>;
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qcom,phy-resetsm-cntrl2 = <0xa0>;
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qcom,phy-core-pll-en-mux = <7>;
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qcom,phy-c-ready-status = <0x178>;
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qcom,pcie-phy-ver = <1003>;
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qcom,phy-status-offset = <0x814>;
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qcom,phy-status-bit = <6>;
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qcom,phy-power-down-offset = <0x840>;
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qcom,phy-sequence = <0x0840 0x03 0x0
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0x0094 0x08 0x0
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0x0154 0x34 0x0
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0x016c 0x08 0x0
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0x0058 0x0f 0x0
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0x00a4 0x42 0x0
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0x0110 0x24 0x0
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0x011c 0x03 0x0
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0x0118 0xb4 0x0
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0x010c 0x02 0x0
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0x01bc 0x11 0x0
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0x00bc 0x82 0x0
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0x00d4 0x03 0x0
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0x00d0 0x55 0x0
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0x00cc 0x55 0x0
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0x00b0 0x1a 0x0
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0x00ac 0x0a 0x0
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0x00c4 0x68 0x0
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0x00e0 0x02 0x0
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0x00dc 0xaa 0x0
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0x00d8 0xab 0x0
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0x00b8 0x34 0x0
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0x00b4 0x14 0x0
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0x0158 0x01 0x0
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0x0074 0x06 0x0
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0x007c 0x16 0x0
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0x0084 0x36 0x0
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0x0078 0x06 0x0
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0x0080 0x16 0x0
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0x0088 0x36 0x0
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0x01b0 0x1e 0x0
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0x01ac 0xca 0x0
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0x01b8 0x18 0x0
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0x01b4 0xa2 0x0
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0x0050 0x07 0x0
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0x0010 0x01 0x0
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0x001c 0x31 0x0
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0x0020 0x01 0x0
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0x0024 0xde 0x0
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0x0028 0x07 0x0
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0x0030 0x4c 0x0
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0x0034 0x06 0x0
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0x029c 0x12 0x0
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0x0284 0x35 0x0
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0x023c 0x11 0x0
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0x051c 0x03 0x0
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0x0518 0x1c 0x0
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0x0524 0x1e 0x0
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0x04e8 0x00 0x0
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0x04ec 0x0e 0x0
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0x04f0 0x4a 0x0
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0x04f4 0x0f 0x0
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0x05b4 0x04 0x0
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0x0434 0x7f 0x0
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0x0444 0x70 0x0
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0x0510 0x17 0x0
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0x04d4 0x04 0x0
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0x04d8 0x07 0x0
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0x0598 0xd4 0x0
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0x059c 0x54 0x0
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0x05a0 0xdb 0x0
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0x05a4 0x3b 0x0
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0x05a8 0x31 0x0
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0x0584 0x24 0x0
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0x0588 0xe4 0x0
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0x058c 0xec 0x0
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0x0590 0x3b 0x0
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0x0594 0x36 0x0
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0x0570 0x3f 0x0
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0x0574 0x3f 0x0
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0x0578 0xff 0x0
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0x057c 0x7f 0x0
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0x0580 0x14 0x0
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0x04fc 0x00 0x0
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0x04f8 0xc0 0x0
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0x0460 0x30 0x0
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0x0464 0x00 0x0
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0x05bc 0x0c 0x0
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0x04dc 0x1b 0x0
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0x0408 0x0c 0x0
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0x0414 0x03 0x0
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0x05b8 0x30 0x0
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0x09a4 0x01 0x0
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0x0c90 0x00 0x0
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0x0c40 0x01 0x0
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0x0c48 0x01 0x0
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0x0c50 0x00 0x0
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0x0cb4 0x33 0x0
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0x0cbc 0x00 0x0
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0x0ce0 0x58 0x0
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0x0ca4 0x0f 0x0
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0x0048 0x90 0x0
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0x0c1c 0xc1 0x0
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0x0988 0x77 0x0
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0x0998 0x0b 0x0
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0x08dc 0x0d 0x0
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0x09ec 0x12 0x0
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0x0800 0x00 0x0
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0x0844 0x03 0x0>;
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pcie0_rp: pcie0_rp {
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reg = <0 0 0 0 0>;
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};
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};
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pcie0_msi: qcom,pcie0_msi@17a10040 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0x17a10040 0x0>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
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};
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};
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@ -1218,6 +1218,60 @@
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};
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};
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pcie0 {
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pcie0_perst_default: pcie0_perst_default {
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mux {
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pins = "gpio87";
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function = "gpio";
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};
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config {
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pins = "gpio87";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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pcie0_clkreq_default: pcie0_clkreq_default {
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mux {
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pins = "gpio88";
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function = "pcie0_clkreqn";
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};
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config {
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pins = "gpio88";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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pcie0_wake_default: pcie0_wake_default {
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mux {
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pins = "gpio89";
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function = "gpio";
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};
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config {
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pins = "gpio89";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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pcie0_clkreq_sleep: pcie0_clkreq_sleep {
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mux {
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pins = "gpio88";
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function = "gpio";
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};
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config {
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pins = "gpio88";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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cam_sensor_mclk0_active: cam_sensor_mclk0_active {
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/* MCLK0 */
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mux {
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@ -3801,6 +3801,7 @@
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#include "ipcc-test-yupik.dtsi"
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#include "yupik-regulators.dtsi"
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#include "display/yupik-sde.dtsi"
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#include "yupik-pcie.dtsi"
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&gcc_ufs_phy_gdsc {
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qcom,support-hw-trigger;
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