mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-11 07:03:09 -04:00
clk: qcom: Add GPU clock driver for SM8150
Add driver support for GPUCC clocks frequency plan. Change-Id: Ib8e8e1d332001f8c9fd200e7494d5a0201be4937 Signed-off-by: Veera Vegivada <vvegivad@codeaurora.org>
This commit is contained in:
Veera Vegivada
parent
1de24295c3
commit
ea4cbcb847
3 changed files with 344 additions and 0 deletions
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@ -299,6 +299,15 @@ config SM_GCC_8150
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Say Y if you want to use peripheral devices such as UART,
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SPI, I2C, USB, SD/UFS, PCIe etc.
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config SM_GPUCC_8150
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tristate "SM8150 Graphics Clock Controller"
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select SM_GCC_8150
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help
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Support for the graphics clock controller on Qualcomm Technologies, Inc.
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sm8150 devices.
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Say Y if you want to support graphics controller devices and
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functionality such as 3D graphics.
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config SPMI_PMIC_CLKDIV
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tristate "SPMI PMIC clkdiv Support"
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depends on SPMI || COMPILE_TEST
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@ -73,6 +73,7 @@ obj-$(CONFIG_SM_DISPCC_SHIMA) += dispcc-shima.o
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obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
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obj-$(CONFIG_SM_GCC_HOLI) += gcc-holi.o
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obj-$(CONFIG_SM_GCC_SHIMA) += gcc-shima.o
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obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
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obj-$(CONFIG_SM_GPUCC_HOLI) += gpucc-holi.o
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obj-$(CONFIG_SM_GPUCC_SHIMA) += gpucc-shima.o
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obj-$(CONFIG_SM_VIDEOCC_SHIMA) += videocc-shima.o
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334
drivers/clk/qcom/gpucc-sm8150.c
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334
drivers/clk/qcom/gpucc-sm8150.c
Normal file
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@ -0,0 +1,334 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "common.h"
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#include "vdd-level-sm8150.h"
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static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);
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static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner);
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enum {
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P_BI_TCXO,
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P_CORE_BI_PLL_TEST_SE,
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P_GPLL0_OUT_MAIN,
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P_GPLL0_OUT_MAIN_DIV,
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P_GPU_CC_PLL0_OUT_MAIN,
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P_GPU_CC_PLL1_OUT_MAIN,
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};
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static struct pll_vco trion_vco[] = {
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{ 249600000, 2000000000, 0 },
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};
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/* 500MHz configuration */
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static struct alpha_pll_config gpu_cc_pll1_config = {
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.l = 0x1A,
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.alpha = 0xAAA,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00002267,
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.config_ctl_hi1_val = 0x00000024,
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.test_ctl_val = 0x00000000,
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.test_ctl_hi_val = 0x00000000,
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.test_ctl_hi1_val = 0x00000020,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00000805,
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.user_ctl_hi1_val = 0x000000D0,
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};
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static struct clk_alpha_pll gpu_cc_pll1 = {
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.offset = 0x100,
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.vco_table = trion_vco,
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.num_vco = ARRAY_SIZE(trion_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
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.config = &gpu_cc_pll1_config,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll1",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_trion_pll_ops,
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},
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.vdd_data = {
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.vdd_class = &vdd_mx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1600000000,
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[VDD_NOMINAL] = 2000000000},
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},
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},
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};
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static const struct parent_map gpu_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
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{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_GPLL0_OUT_MAIN_DIV, 6 },
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{ P_CORE_BI_PLL_TEST_SE, 7 },
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};
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static const struct clk_parent_data gpu_cc_parent_data_0[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "gpu_cc_pll0", .name = "gpu_cc_pll0" },
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{ .hw = &gpu_cc_pll1.clkr.hw },
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{ .fw_name = "gcc_gpu_gpll0_clk_src" },
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{ .fw_name = "gcc_gpu_gpll0_div_clk_src" },
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{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
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};
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static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
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F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 gpu_cc_gmu_clk_src = {
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.cmd_rcgr = 0x1120,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_0,
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.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
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.enable_safe_config = true,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gmu_clk_src",
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.parent_data = gpu_cc_parent_data_0,
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.num_parents = 6,
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.ops = &clk_rcg2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 200000000,
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[VDD_LOW] = 500000000},
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},
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};
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static struct clk_branch gpu_cc_ahb_clk = {
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.halt_reg = 0x1078,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1078,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_ahb_clk",
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.flags = CLK_IS_CRITICAL,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_crc_ahb_clk = {
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.halt_reg = 0x107c,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x107c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_crc_ahb_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_gmu_clk = {
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.halt_reg = 0x1098,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1098,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_gmu_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gpu_cc_gmu_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
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.halt_reg = 0x108c,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x108c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_snoc_dvm_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cxo_aon_clk = {
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.halt_reg = 0x1004,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x1004,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cxo_aon_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cxo_clk = {
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.halt_reg = 0x109c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x109c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cxo_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_gx_gmu_clk = {
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.halt_reg = 0x1064,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1064,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gx_gmu_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gpu_cc_gmu_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_sleep_clk = {
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.halt_reg = 0x1090,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x1090,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_sleep_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_regmap *gpu_cc_sm8150_clocks[] = {
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[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
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[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
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[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
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[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
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[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
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[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
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[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
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[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
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[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
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[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
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};
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static const struct regmap_config gpu_cc_sm8150_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x8008,
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.fast_io = true,
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};
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static const struct qcom_cc_desc gpu_cc_sm8150_desc = {
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.config = &gpu_cc_sm8150_regmap_config,
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.clks = gpu_cc_sm8150_clocks,
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.num_clks = ARRAY_SIZE(gpu_cc_sm8150_clocks),
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};
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static const struct of_device_id gpu_cc_sm8150_match_table[] = {
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{ .compatible = "qcom,sm8150-gpucc" },
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{ .compatible = "qcom,sa8155-gpucc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, gpu_cc_sm8150_match_table);
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static int gpu_cc_sm8150_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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int ret;
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vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx");
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if (IS_ERR(vdd_cx.regulator[0])) {
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if (PTR_ERR(vdd_cx.regulator[0]) != -EPROBE_DEFER)
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dev_err(&pdev->dev, "Unable to get vdd_cx regulator\n");
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return PTR_ERR(vdd_cx.regulator[0]);
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}
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vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx");
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if (IS_ERR(vdd_mx.regulator[0])) {
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if (PTR_ERR(vdd_mx.regulator[0]) != -EPROBE_DEFER)
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dev_err(&pdev->dev, "Unable to get vdd_mx regulator\n");
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return PTR_ERR(vdd_mx.regulator[0]);
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}
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regmap = qcom_cc_map(pdev, &gpu_cc_sm8150_desc);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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clk_trion_pll_configure(&gpu_cc_pll1, regmap, gpu_cc_pll1.config);
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ret = qcom_cc_really_probe(pdev, &gpu_cc_sm8150_desc, regmap);
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if (ret) {
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dev_err(&pdev->dev, "Failed to register GPU CC clocks\n");
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return ret;
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}
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dev_info(&pdev->dev, "Registered GPU CC clocks\n");
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return ret;
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}
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static struct platform_driver gpu_cc_sm8150_driver = {
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.probe = gpu_cc_sm8150_probe,
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.driver = {
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.name = "gpu_cc-sm8150",
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.of_match_table = gpu_cc_sm8150_match_table,
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},
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};
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static int __init gpu_cc_sm8150_init(void)
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{
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return platform_driver_register(&gpu_cc_sm8150_driver);
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}
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subsys_initcall(gpu_cc_sm8150_init);
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static void __exit gpu_cc_sm8150_exit(void)
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{
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platform_driver_unregister(&gpu_cc_sm8150_driver);
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}
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module_exit(gpu_cc_sm8150_exit);
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MODULE_DESCRIPTION("QTI GPU_CC SM8150 Driver");
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MODULE_LICENSE("GPL v2");
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