From ea9228516acc7ff5c8415d958cff9dd41fd56c10 Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Fri, 20 Nov 2020 12:31:01 +0530 Subject: [PATCH] dt-bindings: input: qpnp-power-on: Update "reg" property description Update the description of "reg" property to add the PON_PBS base address along with PON_HLOS base address. Also add "reg-names" property. Change-Id: I257950babd4b68f3ab933679bd94936813531e25 --- bindings/input/qpnp-power-on.txt | 32 ++++++++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/bindings/input/qpnp-power-on.txt b/bindings/input/qpnp-power-on.txt index d935a2a443d3..b1b16685dcb1 100644 --- a/bindings/input/qpnp-power-on.txt +++ b/bindings/input/qpnp-power-on.txt @@ -9,10 +9,18 @@ peripheral is connected to the host processor via the SPMI interface. Required properties: - compatible: Must be "qcom,qpnp-power-on" -- reg: Specifies the SPMI base address for this PON - (power-on) peripheral. +- reg: Specifies the SPMI base address for this + PON (power-on) peripheral. For PMICs that have + PON peripheral (GEN3) split into PON_HLOS and + PON_PBS, this can hold addresses of both. + PON_PBS base address needs to be specified for + such devices if "qcom,kdpwr-sw-debounce" is + specified. Optional properties: +- reg-names: For PON GEN1 and GEN2, it should be "pon". + For PON GEN3, it should include "pon_hlos" and + optionally "pon_pbs". - interrupts: Specifies the interrupts associated with PON. - interrupt-names: Specifies the interrupt names associated with the interrupts property. Must be a subset of @@ -245,3 +253,23 @@ Examples: qcom,pon-spare-reg-bit = <1>; }; }; + + pon_hlos@1300 { + compatible = "qcom,qpnp-power-on"; + reg = <0x1300>, <0x800>; + reg-names = "pon_hlos", "pon_pbs"; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "kpdpwr", "resin"; + qcom,kpdpwr-sw-debounce; + + qcom,pon_1 { + qcom,pon-type = ; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + linux,code = ; + }; + };