From eade63525a85e950f46edb681c9ac12eb5250b10 Mon Sep 17 00:00:00 2001 From: Deepak Katragadda Date: Wed, 16 May 2018 11:00:29 -0700 Subject: [PATCH] clk: qcom: gdsc-regulator: Remove polling logic when disabling GDSC HW CTL There is no mandate in hardware that the SW_COLLAPSE bit of the GDSC be cleared while disabling its hardware control. Remove the polling logic to check whether the GDSC is enabled via the SW vote on clearing the HW_CONTROL bit. Change-Id: Ib08b627a3502d1096ae7d05ef077a50b95fc80d2 Signed-off-by: Deepak Katragadda --- drivers/clk/qcom/gdsc-regulator.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/clk/qcom/gdsc-regulator.c b/drivers/clk/qcom/gdsc-regulator.c index 0b4d824447ef..a90fb87d6694 100644 --- a/drivers/clk/qcom/gdsc-regulator.c +++ b/drivers/clk/qcom/gdsc-regulator.c @@ -500,17 +500,11 @@ static int gdsc_set_mode(struct regulator_dev *rdev, unsigned int mode) /* * There may be a race with internal HW trigger signal, * that will result in GDSC going through a power down and - * up cycle. If we poll too early, status bit will - * indicate 'on' before the GDSC can finish the power cycle. - * Account for this case by waiting 1us before polling. + * up cycle. Account for this case by waiting 1us before + * proceeding. */ gdsc_mb(sc); udelay(1); - - ret = poll_gdsc_status(sc, ENABLED); - if (ret) - dev_err(&rdev->dev, "%s set_mode timed out: 0x%x\n", - sc->rdesc.name, regval); break; default: ret = -EINVAL;