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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM: dts: msm: Add Yupik trustedVM device configuration
Add device configuration for RUMI/IDP/ATP/QRD platforms for Yupik trusted VM. Change-Id: Ib62b74bcea63689218d16f4604b0373be917aaf9
This commit is contained in:
Naina Mehta
parent
a8030001d1
commit
ebb087f4de
10 changed files with 288 additions and 0 deletions
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@ -230,6 +230,15 @@ dtb-$(CONFIG_ARCH_SDXNIGHTJAR) += sdxnightjar-mtp.dtb \
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sdxnightjar-cdp.dtb \
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sdxnightjar-qrd.dtb
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ifeq ($(CONFIG_ARCH_YUPIK), y)
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ifeq ($(CONFIG_ARCH_QTI_VM), y)
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dtb-$(CONFIG_ARCH_QTI_VM) += yupik-vm-rumi.dtb \
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yupik-vm-atp.dtb \
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yupik-vm-idp.dtb \
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yupik-vm-qrd.dtb
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endif
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endif
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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clean-files := *.dtb *.dtbo
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10
qcom/yupik-vm-atp.dts
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10
qcom/yupik-vm-atp.dts
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@ -0,0 +1,10 @@
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/dts-v1/;
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#include "yupik-vm.dtsi"
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#include "yupik-vm-atp.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Yupik VM ATP";
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compatible = "qcom,yupik-atp", "qcom,yupik", "qcom,atp";
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qcom,board-id = <0x10021 0>;
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};
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2
qcom/yupik-vm-atp.dtsi
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2
qcom/yupik-vm-atp.dtsi
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@ -0,0 +1,2 @@
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&soc {
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};
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10
qcom/yupik-vm-idp.dts
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10
qcom/yupik-vm-idp.dts
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@ -0,0 +1,10 @@
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/dts-v1/;
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#include "yupik-vm.dtsi"
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#include "yupik-vm-idp.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Yupik VM IDP";
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compatible = "qcom,yupik-idp", "qcom,yupik", "qcom,idp";
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qcom,board-id = <34 0>;
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};
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2
qcom/yupik-vm-idp.dtsi
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2
qcom/yupik-vm-idp.dtsi
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@ -0,0 +1,2 @@
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&soc {
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};
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10
qcom/yupik-vm-qrd.dts
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10
qcom/yupik-vm-qrd.dts
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@ -0,0 +1,10 @@
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/dts-v1/;
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#include "yupik-vm.dtsi"
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#include "yupik-vm-qrd.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Yupik VM QRD";
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compatible = "qcom,yupik-qrd", "qcom,yupik", "qcom,qrd";
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qcom,board-id = <0x1000B 0>;
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};
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2
qcom/yupik-vm-qrd.dtsi
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2
qcom/yupik-vm-qrd.dtsi
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@ -0,0 +1,2 @@
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&soc {
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};
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11
qcom/yupik-vm-rumi.dts
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11
qcom/yupik-vm-rumi.dts
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@ -0,0 +1,11 @@
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/dts-v1/;
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/memreserve/ 0x90000000 0x00000100;
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#include "yupik-vm.dtsi"
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#include "yupik-vm-rumi.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. Yupik SVM RUMI";
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compatible = "qcom,yupik-rumi", "qcom,yupik", "qcom,rumi";
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qcom,board-id = <0x1000f 0>;
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};
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5
qcom/yupik-vm-rumi.dtsi
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5
qcom/yupik-vm-rumi.dtsi
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@ -0,0 +1,5 @@
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&soc {
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timer {
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clock-frequency = <5000000>;
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};
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};
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227
qcom/yupik-vm.dtsi
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227
qcom/yupik-vm.dtsi
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@ -0,0 +1,227 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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qcom,msm-id = <475 0x10000>;
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interrupt-parent = <&vgic>;
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qcom-mem-buf {
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compatible = "qcom,mem-buf";
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qcom,mem-buf-capabilities = "consumer";
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};
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chosen {
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bootargs = "nokaslr root=/dev/ram rw init=/init console=hvc0 loglevel=8";
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linux,initrd-start = <0x2a900000>;
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linux,initrd-end = <0x2b100000>; /* 8 MB */
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kaslr-seed = <0xfeedbeef 0xc0def00d>;
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};
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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CPU0: cpu@0 {
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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cpu-idle-states = <&CPU_PWR_DWN>;
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};
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CPU1: cpu@100 {
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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cpu-idle-states = <&CPU_PWR_DWN>;
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};
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};
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idle-states {
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CPU_PWR_DWN: c4 { /* Using Gold C4 latencies */
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <702>;
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exit-latency-us = <1061>;
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min-residency-us = <4488>;
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arm,psci-suspend-param = <0x40000004>;
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local-timer-stop;
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};
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};
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neuron-client-block {
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compatible = "qcom,neuron-service";
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#address-cells = <1>;
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#size-cells = <0>;
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protocol {
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compatible = "qcom,neuron-protocol-block";
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processes = "client";
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};
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application {
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compatible = "qcom,neuron-block-client";
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};
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channel@0 {
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reg = <0>;
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compatible = "qcom,neuron-channel-haven-shmem";
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class = "message-queue";
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direction = "send";
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max-size = <0 65536>;
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haven-label = <1>;
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};
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channel@1 {
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reg = <1>;
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compatible = "qcom,neuron-channel-haven-shmem";
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class = "message-queue";
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direction = "receive";
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max-size = <0 65536>;
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haven-label = <2>;
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};
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};
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qrtr-haven {
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compatible = "qcom,qrtr-haven";
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haven-label = <3>;
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};
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qcom,vm-config {
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compatible = "qcom,vm-1.0";
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vm-type = "aarch64-guest";
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boot-config = "fdt,unified";
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os-type = "linux";
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kernel-entry-segment = "kernel";
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kernel-entry-offset = <0x0 0x0>;
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vendor = "Qualcomm Technologies, Inc.";
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image-name = "qcom,trustedvm";
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qcom,pasid = <0x0 0x1c>;
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iomemory-ranges = <0x0 0x92c000 0x0 0x92c000 0x0 0x4000 0x0
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0x0 0xc400000 0x0 0xc400000 0x0 0x30000 0x1
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0x0 0xc440000 0x0 0xc440000 0x0 0x10000 0x1
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0x0 0xc600000 0x0 0xc600000 0x0 0x2000000 0x1
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0x0 0xe600000 0x0 0xe600000 0x0 0x100000 0x1
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0x0 0xe700000 0x0 0xe700000 0x0 0xa0000 0x1
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0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0>;
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gic-irq-ranges = <283 283>; /* PVM->SVM IRQ transfer */
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memory {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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base-address = <0x0 0xD0800000>;
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size-min = <0x0 0x76f7000>; /* 118 MB */
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};
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segments {
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ramdisk = <2>; /* 8MB */
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};
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vcpus {
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config = "/cpus";
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affinity = "static";
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affinity-map = <0x4 0x5>;
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sched-priority = <0>; /* relative to PVM */
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sched-timeslice = <2000>; /* in ms */
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};
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interrupts {
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config = &vgic;
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};
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vdevices {
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generate = "/hypervisor";
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rm-rpc {
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vdevice-type = "rm-rpc";
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generate = "/hypervisor/qcom,resource-mgr";
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console-dev;
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message-size = <0x000000f0>;
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queue-depth = <0x00000008>;
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qcom,label = <0x1>;
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};
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mem-buf-message-queue-pair {
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vdevice-type = "message-queue-pair";
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generate = "/hypervisor/membuf-msgq-pair";
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message-size = <0x000000f0>;
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queue-depth = <0x00000008>;
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peer-default;
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qcom,label = <0x0000001>;
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};
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neuron-ch1-shm {
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vdevice-type = "shm-doorbell";
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generate = "/hypervisor/neuron-ch1-shm";
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push-compatible = "qcom,neuron-channel-haven-shmem-gen";
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peer-default;
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memory {
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qcom,label = <0x1>;
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allocate-base;
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};
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};
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neuron-ch2-shm {
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vdevice-type = "shm-doorbell";
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generate = "/hypervisor/neuron-ch2-shm";
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push-compatible = "qcom,neuron-channel-haven-shmem-gen";
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peer-default;
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memory {
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qcom,label = <0x2>;
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allocate-base;
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};
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};
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qrtr-shm {
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vdevice-type = "shm-doorbell";
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generate = "/hypervisor/qrtr-shm";
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push-compatible = "qcom,qrtr-haven-gen";
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peer-default;
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memory {
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qcom,label = <0x3>;
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allocate-base;
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};
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};
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};
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};
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firmware: firmware {
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scm {
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compatible = "qcom,scm";
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};
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};
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soc: soc { };
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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vgic: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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interrupt-controller;
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#interrupt-cells = <0x3>;
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reg = <0x17a00000 0x10000>, /* GICD */
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<0x17a60000 0x100000>; /* GICR * 8 */
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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always-on;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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