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tty: serial: 8250: 8250_core: NXP SC16C2552 workaround

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NXP SC16C2552 requires that we always write a reset to the RX FIFO and
TX FIFO whenever we enable the FIFOs

Cc: [email protected]
Signed-off-by: Steve Shih <[email protected]>
Signed-off-by: David Singleton <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
This commit is contained in:
Steve Shih 2016-10-17 09:51:05 -07:00 • committed by Greg Kroah-Hartman
commit ecb988a3b7
1 changed files with 2 additions and 1 deletions
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3
drivers/tty/serial/8250/8250_port.c
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@ -83,7 +83,8 @@ static const struct serial8250_config uart_config[] = {
.name = "16550A",
.fifo_size = 16,
.tx_loadsz = 16,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
.rxtrig_bytes = {1, 4, 8, 14},
.flags = UART_CAP_FIFO,
},