mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 19:21:31 -04:00
KVM: s390: Fixes for 4.19
- Fallout from the hugetlbfs support: pfmf interpretion and locking - VSIE: fix keywrapping for nested guests -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABAgAGBQJbj40sAAoJEBF7vIC1phx8MIYQAK6TtogzCUok4nvRJZGl34Ac HvJP2OTSNcJO8MA/DkmXk6LNVgrjgLqc4Y0MCMqaz9EzM1FVM0A5cQ4Tiiwk6dlG 395Q5SbkrmVIpmxG7dSQbrj3HlMTUCz7jtAUrDS57zaWYdKhqX+AUuW45u+TPfAo DL00wS+WJxiTWB06cr0gHpHcXyctn5hK0cYUZQokMn2a1pAjLrS4TEpvoGOcu2d6 lULY6uYWCwCnma8eieiC8ssLzB8opDPedLrewBnaZFziEZZrPybYvT8uMffNfygA tj7og1/+iqnUmyAG20Fb8oM0MMcjRWhLGHVFpv1W1ph7624oDUb3Tzd7rV8bzTMC NoqHeIv+oQyhRJCsuPTe2jUcpKc/eJzA8o3ZUdu3LeDBXxNzNOIh08iRHvyFC9iM 91/YkyYcDW2cukxqYjIwPf+y/dVHRqNAmcs9+hvu8AiNeUJPGUYsmlTBABEg0V9H gubV7m/Gl5Yx95UyrlQ4UkuvkOzmtwFYsnFKE0KnqT99bbFFf2na3CZyYBJFBVOj knSl3lS9W5LLrZ3s2VaJ/4/bPc4oGjW1ADEamQCYa4K3XQoMrnqGdL0VVuALJ2dZ RVIz2DP+P6HBCoRWD0cOA0Q+MvP5hl6TrGDdpCbza3ASSF1f/eSASvHs4P4JQPqY dWQ3uIByc3wDXuErkcT5 =kgjR -----END PGP SIGNATURE----- Merge tag 'kvm-s390-master-4.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux KVM: s390: Fixes for 4.19 - Fallout from the hugetlbfs support: pfmf interpretion and locking - VSIE: fix keywrapping for nested guests
This commit is contained in:
Radim Krčmář
commit
ed2ef29100
243 changed files with 2248 additions and 1652 deletions
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@ -2843,7 +2843,7 @@ config X86_SYSFB
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This option, if enabled, marks VGA/VBE/EFI framebuffers as generic
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framebuffers so the new generic system-framebuffer drivers can be
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used on x86. If the framebuffer is not compatible with the generic
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modes, it is adverticed as fallback platform framebuffer so legacy
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modes, it is advertised as fallback platform framebuffer so legacy
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drivers like efifb, vesafb and uvesafb can pick it up.
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If this option is not selected, all system framebuffers are always
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marked as fallback platform framebuffers as usual.
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@ -175,22 +175,6 @@ ifdef CONFIG_FUNCTION_GRAPH_TRACER
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endif
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endif
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ifndef CC_HAVE_ASM_GOTO
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$(error Compiler lacks asm-goto support.)
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endif
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#
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# Jump labels need '-maccumulate-outgoing-args' for gcc < 4.5.2 to prevent a
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# GCC bug (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=46226). There's no way
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# to test for this bug at compile-time because the test case needs to execute,
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# which is a no-go for cross compilers. So check the GCC version instead.
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#
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ifdef CONFIG_JUMP_LABEL
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ifneq ($(ACCUMULATE_OUTGOING_ARGS), 1)
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ACCUMULATE_OUTGOING_ARGS = $(call cc-if-fullversion, -lt, 040502, 1)
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endif
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endif
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ifeq ($(ACCUMULATE_OUTGOING_ARGS), 1)
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# This compiler flag is not supported by Clang:
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KBUILD_CFLAGS += $(call cc-option,-maccumulate-outgoing-args,)
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@ -312,6 +296,13 @@ PHONY += vdso_install
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vdso_install:
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$(Q)$(MAKE) $(build)=arch/x86/entry/vdso $@
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archprepare: checkbin
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checkbin:
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ifndef CC_HAVE_ASM_GOTO
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@echo Compiler lacks asm-goto support.
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@exit 1
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endif
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archclean:
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$(Q)rm -rf $(objtree)/arch/i386
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$(Q)rm -rf $(objtree)/arch/x86_64
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@ -223,34 +223,34 @@ ALL_F: .octa 0xffffffffffffffffffffffffffffffff
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pcmpeqd TWOONE(%rip), \TMP2
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pand POLY(%rip), \TMP2
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pxor \TMP2, \TMP3
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movdqa \TMP3, HashKey(%arg2)
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movdqu \TMP3, HashKey(%arg2)
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movdqa \TMP3, \TMP5
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pshufd $78, \TMP3, \TMP1
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pxor \TMP3, \TMP1
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movdqa \TMP1, HashKey_k(%arg2)
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movdqu \TMP1, HashKey_k(%arg2)
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GHASH_MUL \TMP5, \TMP3, \TMP1, \TMP2, \TMP4, \TMP6, \TMP7
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# TMP5 = HashKey^2<<1 (mod poly)
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movdqa \TMP5, HashKey_2(%arg2)
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movdqu \TMP5, HashKey_2(%arg2)
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# HashKey_2 = HashKey^2<<1 (mod poly)
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pshufd $78, \TMP5, \TMP1
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pxor \TMP5, \TMP1
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movdqa \TMP1, HashKey_2_k(%arg2)
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movdqu \TMP1, HashKey_2_k(%arg2)
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GHASH_MUL \TMP5, \TMP3, \TMP1, \TMP2, \TMP4, \TMP6, \TMP7
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# TMP5 = HashKey^3<<1 (mod poly)
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movdqa \TMP5, HashKey_3(%arg2)
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movdqu \TMP5, HashKey_3(%arg2)
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pshufd $78, \TMP5, \TMP1
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pxor \TMP5, \TMP1
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movdqa \TMP1, HashKey_3_k(%arg2)
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movdqu \TMP1, HashKey_3_k(%arg2)
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GHASH_MUL \TMP5, \TMP3, \TMP1, \TMP2, \TMP4, \TMP6, \TMP7
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# TMP5 = HashKey^3<<1 (mod poly)
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movdqa \TMP5, HashKey_4(%arg2)
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movdqu \TMP5, HashKey_4(%arg2)
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pshufd $78, \TMP5, \TMP1
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pxor \TMP5, \TMP1
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movdqa \TMP1, HashKey_4_k(%arg2)
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movdqu \TMP1, HashKey_4_k(%arg2)
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.endm
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# GCM_INIT initializes a gcm_context struct to prepare for encoding/decoding.
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@ -271,7 +271,7 @@ ALL_F: .octa 0xffffffffffffffffffffffffffffffff
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movdqu %xmm0, CurCount(%arg2) # ctx_data.current_counter = iv
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PRECOMPUTE \SUBKEY, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6, %xmm7,
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movdqa HashKey(%arg2), %xmm13
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movdqu HashKey(%arg2), %xmm13
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CALC_AAD_HASH %xmm13, \AAD, \AADLEN, %xmm0, %xmm1, %xmm2, %xmm3, \
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%xmm4, %xmm5, %xmm6
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@ -997,7 +997,7 @@ TMP6 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 operation
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pshufd $78, \XMM5, \TMP6
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pxor \XMM5, \TMP6
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paddd ONE(%rip), \XMM0 # INCR CNT
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movdqa HashKey_4(%arg2), \TMP5
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movdqu HashKey_4(%arg2), \TMP5
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PCLMULQDQ 0x11, \TMP5, \TMP4 # TMP4 = a1*b1
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movdqa \XMM0, \XMM1
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paddd ONE(%rip), \XMM0 # INCR CNT
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@ -1016,7 +1016,7 @@ TMP6 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 operation
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pxor (%arg1), \XMM2
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pxor (%arg1), \XMM3
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pxor (%arg1), \XMM4
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movdqa HashKey_4_k(%arg2), \TMP5
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movdqu HashKey_4_k(%arg2), \TMP5
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PCLMULQDQ 0x00, \TMP5, \TMP6 # TMP6 = (a1+a0)*(b1+b0)
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movaps 0x10(%arg1), \TMP1
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AESENC \TMP1, \XMM1 # Round 1
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@ -1031,7 +1031,7 @@ TMP6 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 operation
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movdqa \XMM6, \TMP1
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pshufd $78, \XMM6, \TMP2
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pxor \XMM6, \TMP2
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movdqa HashKey_3(%arg2), \TMP5
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movdqu HashKey_3(%arg2), \TMP5
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PCLMULQDQ 0x11, \TMP5, \TMP1 # TMP1 = a1 * b1
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movaps 0x30(%arg1), \TMP3
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AESENC \TMP3, \XMM1 # Round 3
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@ -1044,7 +1044,7 @@ TMP6 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 operation
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AESENC \TMP3, \XMM2
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AESENC \TMP3, \XMM3
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AESENC \TMP3, \XMM4
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movdqa HashKey_3_k(%arg2), \TMP5
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movdqu HashKey_3_k(%arg2), \TMP5
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PCLMULQDQ 0x00, \TMP5, \TMP2 # TMP2 = (a1+a0)*(b1+b0)
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movaps 0x50(%arg1), \TMP3
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AESENC \TMP3, \XMM1 # Round 5
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@ -1058,7 +1058,7 @@ TMP6 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 operation
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movdqa \XMM7, \TMP1
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pshufd $78, \XMM7, \TMP2
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pxor \XMM7, \TMP2
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movdqa HashKey_2(%arg2), \TMP5
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movdqu HashKey_2(%arg2), \TMP5
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# Multiply TMP5 * HashKey using karatsuba
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@ -1074,7 +1074,7 @@ TMP6 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 operation
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AESENC \TMP3, \XMM2
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AESENC \TMP3, \XMM3
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AESENC \TMP3, \XMM4
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movdqa HashKey_2_k(%arg2), \TMP5
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movdqu HashKey_2_k(%arg2), \TMP5
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PCLMULQDQ 0x00, \TMP5, \TMP2 # TMP2 = (a1+a0)*(b1+b0)
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movaps 0x80(%arg1), \TMP3
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AESENC \TMP3, \XMM1 # Round 8
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@ -1092,7 +1092,7 @@ TMP6 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 operation
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movdqa \XMM8, \TMP1
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pshufd $78, \XMM8, \TMP2
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pxor \XMM8, \TMP2
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movdqa HashKey(%arg2), \TMP5
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movdqu HashKey(%arg2), \TMP5
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PCLMULQDQ 0x11, \TMP5, \TMP1 # TMP1 = a1*b1
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movaps 0x90(%arg1), \TMP3
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AESENC \TMP3, \XMM1 # Round 9
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@ -1121,7 +1121,7 @@ aes_loop_par_enc_done\@:
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AESENCLAST \TMP3, \XMM2
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AESENCLAST \TMP3, \XMM3
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AESENCLAST \TMP3, \XMM4
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movdqa HashKey_k(%arg2), \TMP5
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movdqu HashKey_k(%arg2), \TMP5
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PCLMULQDQ 0x00, \TMP5, \TMP2 # TMP2 = (a1+a0)*(b1+b0)
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movdqu (%arg4,%r11,1), \TMP3
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pxor \TMP3, \XMM1 # Ciphertext/Plaintext XOR EK
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@ -1205,7 +1205,7 @@ TMP6 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 operation
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pshufd $78, \XMM5, \TMP6
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pxor \XMM5, \TMP6
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paddd ONE(%rip), \XMM0 # INCR CNT
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movdqa HashKey_4(%arg2), \TMP5
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movdqu HashKey_4(%arg2), \TMP5
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PCLMULQDQ 0x11, \TMP5, \TMP4 # TMP4 = a1*b1
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movdqa \XMM0, \XMM1
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paddd ONE(%rip), \XMM0 # INCR CNT
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@ -1224,7 +1224,7 @@ TMP6 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 operation
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pxor (%arg1), \XMM2
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pxor (%arg1), \XMM3
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pxor (%arg1), \XMM4
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movdqa HashKey_4_k(%arg2), \TMP5
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movdqu HashKey_4_k(%arg2), \TMP5
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PCLMULQDQ 0x00, \TMP5, \TMP6 # TMP6 = (a1+a0)*(b1+b0)
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movaps 0x10(%arg1), \TMP1
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AESENC \TMP1, \XMM1 # Round 1
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@ -1239,7 +1239,7 @@ TMP6 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 operation
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movdqa \XMM6, \TMP1
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pshufd $78, \XMM6, \TMP2
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pxor \XMM6, \TMP2
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movdqa HashKey_3(%arg2), \TMP5
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movdqu HashKey_3(%arg2), \TMP5
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PCLMULQDQ 0x11, \TMP5, \TMP1 # TMP1 = a1 * b1
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movaps 0x30(%arg1), \TMP3
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AESENC \TMP3, \XMM1 # Round 3
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@ -1252,7 +1252,7 @@ TMP6 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 operation
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AESENC \TMP3, \XMM2
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AESENC \TMP3, \XMM3
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AESENC \TMP3, \XMM4
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movdqa HashKey_3_k(%arg2), \TMP5
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movdqu HashKey_3_k(%arg2), \TMP5
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PCLMULQDQ 0x00, \TMP5, \TMP2 # TMP2 = (a1+a0)*(b1+b0)
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movaps 0x50(%arg1), \TMP3
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AESENC \TMP3, \XMM1 # Round 5
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@ -1266,7 +1266,7 @@ TMP6 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 operation
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movdqa \XMM7, \TMP1
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pshufd $78, \XMM7, \TMP2
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pxor \XMM7, \TMP2
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movdqa HashKey_2(%arg2), \TMP5
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movdqu HashKey_2(%arg2), \TMP5
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# Multiply TMP5 * HashKey using karatsuba
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@ -1282,7 +1282,7 @@ TMP6 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 operation
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AESENC \TMP3, \XMM2
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AESENC \TMP3, \XMM3
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AESENC \TMP3, \XMM4
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movdqa HashKey_2_k(%arg2), \TMP5
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movdqu HashKey_2_k(%arg2), \TMP5
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PCLMULQDQ 0x00, \TMP5, \TMP2 # TMP2 = (a1+a0)*(b1+b0)
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movaps 0x80(%arg1), \TMP3
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AESENC \TMP3, \XMM1 # Round 8
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@ -1300,7 +1300,7 @@ TMP6 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 operation
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movdqa \XMM8, \TMP1
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pshufd $78, \XMM8, \TMP2
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pxor \XMM8, \TMP2
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movdqa HashKey(%arg2), \TMP5
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movdqu HashKey(%arg2), \TMP5
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PCLMULQDQ 0x11, \TMP5, \TMP1 # TMP1 = a1*b1
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movaps 0x90(%arg1), \TMP3
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AESENC \TMP3, \XMM1 # Round 9
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@ -1329,7 +1329,7 @@ aes_loop_par_dec_done\@:
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AESENCLAST \TMP3, \XMM2
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AESENCLAST \TMP3, \XMM3
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AESENCLAST \TMP3, \XMM4
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movdqa HashKey_k(%arg2), \TMP5
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movdqu HashKey_k(%arg2), \TMP5
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PCLMULQDQ 0x00, \TMP5, \TMP2 # TMP2 = (a1+a0)*(b1+b0)
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movdqu (%arg4,%r11,1), \TMP3
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pxor \TMP3, \XMM1 # Ciphertext/Plaintext XOR EK
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@ -1405,10 +1405,10 @@ TMP7 XMM1 XMM2 XMM3 XMM4 XMMDst
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movdqa \XMM1, \TMP6
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pshufd $78, \XMM1, \TMP2
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pxor \XMM1, \TMP2
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movdqa HashKey_4(%arg2), \TMP5
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movdqu HashKey_4(%arg2), \TMP5
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PCLMULQDQ 0x11, \TMP5, \TMP6 # TMP6 = a1*b1
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PCLMULQDQ 0x00, \TMP5, \XMM1 # XMM1 = a0*b0
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movdqa HashKey_4_k(%arg2), \TMP4
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movdqu HashKey_4_k(%arg2), \TMP4
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PCLMULQDQ 0x00, \TMP4, \TMP2 # TMP2 = (a1+a0)*(b1+b0)
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movdqa \XMM1, \XMMDst
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movdqa \TMP2, \XMM1 # result in TMP6, XMMDst, XMM1
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@ -1418,10 +1418,10 @@ TMP7 XMM1 XMM2 XMM3 XMM4 XMMDst
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movdqa \XMM2, \TMP1
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pshufd $78, \XMM2, \TMP2
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pxor \XMM2, \TMP2
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movdqa HashKey_3(%arg2), \TMP5
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movdqu HashKey_3(%arg2), \TMP5
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PCLMULQDQ 0x11, \TMP5, \TMP1 # TMP1 = a1*b1
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PCLMULQDQ 0x00, \TMP5, \XMM2 # XMM2 = a0*b0
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movdqa HashKey_3_k(%arg2), \TMP4
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movdqu HashKey_3_k(%arg2), \TMP4
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PCLMULQDQ 0x00, \TMP4, \TMP2 # TMP2 = (a1+a0)*(b1+b0)
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pxor \TMP1, \TMP6
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pxor \XMM2, \XMMDst
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@ -1433,10 +1433,10 @@ TMP7 XMM1 XMM2 XMM3 XMM4 XMMDst
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movdqa \XMM3, \TMP1
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pshufd $78, \XMM3, \TMP2
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pxor \XMM3, \TMP2
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movdqa HashKey_2(%arg2), \TMP5
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movdqu HashKey_2(%arg2), \TMP5
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PCLMULQDQ 0x11, \TMP5, \TMP1 # TMP1 = a1*b1
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PCLMULQDQ 0x00, \TMP5, \XMM3 # XMM3 = a0*b0
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movdqa HashKey_2_k(%arg2), \TMP4
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movdqu HashKey_2_k(%arg2), \TMP4
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PCLMULQDQ 0x00, \TMP4, \TMP2 # TMP2 = (a1+a0)*(b1+b0)
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pxor \TMP1, \TMP6
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pxor \XMM3, \XMMDst
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|
@ -1446,10 +1446,10 @@ TMP7 XMM1 XMM2 XMM3 XMM4 XMMDst
|
|||
movdqa \XMM4, \TMP1
|
||||
pshufd $78, \XMM4, \TMP2
|
||||
pxor \XMM4, \TMP2
|
||||
movdqa HashKey(%arg2), \TMP5
|
||||
movdqu HashKey(%arg2), \TMP5
|
||||
PCLMULQDQ 0x11, \TMP5, \TMP1 # TMP1 = a1*b1
|
||||
PCLMULQDQ 0x00, \TMP5, \XMM4 # XMM4 = a0*b0
|
||||
movdqa HashKey_k(%arg2), \TMP4
|
||||
movdqu HashKey_k(%arg2), \TMP4
|
||||
PCLMULQDQ 0x00, \TMP4, \TMP2 # TMP2 = (a1+a0)*(b1+b0)
|
||||
pxor \TMP1, \TMP6
|
||||
pxor \XMM4, \XMMDst
|
||||
|
|
|
|||
|
|
@ -2465,7 +2465,7 @@ perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs
|
|||
|
||||
perf_callchain_store(entry, regs->ip);
|
||||
|
||||
if (!current->mm)
|
||||
if (!nmi_uaccess_okay())
|
||||
return;
|
||||
|
||||
if (perf_callchain_user32(regs, entry))
|
||||
|
|
|
|||
|
|
@ -33,7 +33,8 @@ extern inline unsigned long native_save_fl(void)
|
|||
return flags;
|
||||
}
|
||||
|
||||
static inline void native_restore_fl(unsigned long flags)
|
||||
extern inline void native_restore_fl(unsigned long flags);
|
||||
extern inline void native_restore_fl(unsigned long flags)
|
||||
{
|
||||
asm volatile("push %0 ; popf"
|
||||
: /* no output */
|
||||
|
|
|
|||
|
|
@ -2,6 +2,8 @@
|
|||
#ifndef _ASM_X86_PGTABLE_3LEVEL_H
|
||||
#define _ASM_X86_PGTABLE_3LEVEL_H
|
||||
|
||||
#include <asm/atomic64_32.h>
|
||||
|
||||
/*
|
||||
* Intel Physical Address Extension (PAE) Mode - three-level page
|
||||
* tables on PPro+ CPUs.
|
||||
|
|
@ -150,10 +152,7 @@ static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
|
|||
{
|
||||
pte_t res;
|
||||
|
||||
/* xchg acts as a barrier before the setting of the high bits */
|
||||
res.pte_low = xchg(&ptep->pte_low, 0);
|
||||
res.pte_high = ptep->pte_high;
|
||||
ptep->pte_high = 0;
|
||||
res.pte = (pteval_t)arch_atomic64_xchg((atomic64_t *)ptep, 0);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -132,6 +132,8 @@ struct cpuinfo_x86 {
|
|||
/* Index into per_cpu list: */
|
||||
u16 cpu_index;
|
||||
u32 microcode;
|
||||
/* Address space bits used by the cache internally */
|
||||
u8 x86_cache_bits;
|
||||
unsigned initialized : 1;
|
||||
} __randomize_layout;
|
||||
|
||||
|
|
@ -183,7 +185,7 @@ extern void cpu_detect(struct cpuinfo_x86 *c);
|
|||
|
||||
static inline unsigned long long l1tf_pfn_limit(void)
|
||||
{
|
||||
return BIT_ULL(boot_cpu_data.x86_phys_bits - 1 - PAGE_SHIFT);
|
||||
return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT);
|
||||
}
|
||||
|
||||
extern void early_cpu_init(void);
|
||||
|
|
|
|||
|
|
@ -39,6 +39,7 @@ extern void do_signal(struct pt_regs *regs);
|
|||
|
||||
#define __ARCH_HAS_SA_RESTORER
|
||||
|
||||
#include <asm/asm.h>
|
||||
#include <uapi/asm/sigcontext.h>
|
||||
|
||||
#ifdef __i386__
|
||||
|
|
@ -86,9 +87,9 @@ static inline int __const_sigismember(sigset_t *set, int _sig)
|
|||
|
||||
static inline int __gen_sigismember(sigset_t *set, int _sig)
|
||||
{
|
||||
unsigned char ret;
|
||||
asm("btl %2,%1\n\tsetc %0"
|
||||
: "=qm"(ret) : "m"(*set), "Ir"(_sig-1) : "cc");
|
||||
bool ret;
|
||||
asm("btl %2,%1" CC_SET(c)
|
||||
: CC_OUT(c) (ret) : "m"(*set), "Ir"(_sig-1));
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -111,6 +111,6 @@ static inline unsigned long caller_frame_pointer(void)
|
|||
return (unsigned long)frame;
|
||||
}
|
||||
|
||||
void show_opcodes(u8 *rip, const char *loglvl);
|
||||
void show_opcodes(struct pt_regs *regs, const char *loglvl);
|
||||
void show_ip(struct pt_regs *regs, const char *loglvl);
|
||||
#endif /* _ASM_X86_STACKTRACE_H */
|
||||
|
|
|
|||
|
|
@ -175,8 +175,16 @@ struct tlb_state {
|
|||
* are on. This means that it may not match current->active_mm,
|
||||
* which will contain the previous user mm when we're in lazy TLB
|
||||
* mode even if we've already switched back to swapper_pg_dir.
|
||||
*
|
||||
* During switch_mm_irqs_off(), loaded_mm will be set to
|
||||
* LOADED_MM_SWITCHING during the brief interrupts-off window
|
||||
* when CR3 and loaded_mm would otherwise be inconsistent. This
|
||||
* is for nmi_uaccess_okay()'s benefit.
|
||||
*/
|
||||
struct mm_struct *loaded_mm;
|
||||
|
||||
#define LOADED_MM_SWITCHING ((struct mm_struct *)1)
|
||||
|
||||
u16 loaded_mm_asid;
|
||||
u16 next_asid;
|
||||
/* last user mm's ctx id */
|
||||
|
|
@ -246,6 +254,38 @@ struct tlb_state {
|
|||
};
|
||||
DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);
|
||||
|
||||
/*
|
||||
* Blindly accessing user memory from NMI context can be dangerous
|
||||
* if we're in the middle of switching the current user task or
|
||||
* switching the loaded mm. It can also be dangerous if we
|
||||
* interrupted some kernel code that was temporarily using a
|
||||
* different mm.
|
||||
*/
|
||||
static inline bool nmi_uaccess_okay(void)
|
||||
{
|
||||
struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
|
||||
struct mm_struct *current_mm = current->mm;
|
||||
|
||||
VM_WARN_ON_ONCE(!loaded_mm);
|
||||
|
||||
/*
|
||||
* The condition we want to check is
|
||||
* current_mm->pgd == __va(read_cr3_pa()). This may be slow, though,
|
||||
* if we're running in a VM with shadow paging, and nmi_uaccess_okay()
|
||||
* is supposed to be reasonably fast.
|
||||
*
|
||||
* Instead, we check the almost equivalent but somewhat conservative
|
||||
* condition below, and we rely on the fact that switch_mm_irqs_off()
|
||||
* sets loaded_mm to LOADED_MM_SWITCHING before writing to CR3.
|
||||
*/
|
||||
if (loaded_mm != current_mm)
|
||||
return false;
|
||||
|
||||
VM_WARN_ON_ONCE(current_mm->pgd != __va(read_cr3_pa()));
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Initialize cr4 shadow for this CPU. */
|
||||
static inline void cr4_init_shadow(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -93,7 +93,7 @@ static inline unsigned int __getcpu(void)
|
|||
*
|
||||
* If RDPID is available, use it.
|
||||
*/
|
||||
alternative_io ("lsl %[p],%[seg]",
|
||||
alternative_io ("lsl %[seg],%[p]",
|
||||
".byte 0xf3,0x0f,0xc7,0xf8", /* RDPID %eax/rax */
|
||||
X86_FEATURE_RDPID,
|
||||
[p] "=a" (p), [seg] "r" (__PER_CPU_SEG));
|
||||
|
|
|
|||
|
|
@ -684,8 +684,6 @@ void *__init_or_module text_poke_early(void *addr, const void *opcode,
|
|||
* It means the size must be writable atomically and the address must be aligned
|
||||
* in a way that permits an atomic write. It also makes sure we fit on a single
|
||||
* page.
|
||||
*
|
||||
* Note: Must be called under text_mutex.
|
||||
*/
|
||||
void *text_poke(void *addr, const void *opcode, size_t len)
|
||||
{
|
||||
|
|
@ -700,6 +698,8 @@ void *text_poke(void *addr, const void *opcode, size_t len)
|
|||
*/
|
||||
BUG_ON(!after_bootmem);
|
||||
|
||||
lockdep_assert_held(&text_mutex);
|
||||
|
||||
if (!core_kernel_text((unsigned long)addr)) {
|
||||
pages[0] = vmalloc_to_page(addr);
|
||||
pages[1] = vmalloc_to_page(addr + PAGE_SIZE);
|
||||
|
|
@ -782,8 +782,6 @@ int poke_int3_handler(struct pt_regs *regs)
|
|||
* - replace the first byte (int3) by the first byte of
|
||||
* replacing opcode
|
||||
* - sync cores
|
||||
*
|
||||
* Note: must be called under text_mutex.
|
||||
*/
|
||||
void *text_poke_bp(void *addr, const void *opcode, size_t len, void *handler)
|
||||
{
|
||||
|
|
@ -792,6 +790,9 @@ void *text_poke_bp(void *addr, const void *opcode, size_t len, void *handler)
|
|||
bp_int3_handler = handler;
|
||||
bp_int3_addr = (u8 *)addr + sizeof(int3);
|
||||
bp_patching_in_progress = true;
|
||||
|
||||
lockdep_assert_held(&text_mutex);
|
||||
|
||||
/*
|
||||
* Corresponding read barrier in int3 notifier for making sure the
|
||||
* in_progress and handler are correctly ordered wrt. patching.
|
||||
|
|
|
|||
|
|
@ -668,6 +668,45 @@ EXPORT_SYMBOL_GPL(l1tf_mitigation);
|
|||
enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
|
||||
EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
|
||||
|
||||
/*
|
||||
* These CPUs all support 44bits physical address space internally in the
|
||||
* cache but CPUID can report a smaller number of physical address bits.
|
||||
*
|
||||
* The L1TF mitigation uses the top most address bit for the inversion of
|
||||
* non present PTEs. When the installed memory reaches into the top most
|
||||
* address bit due to memory holes, which has been observed on machines
|
||||
* which report 36bits physical address bits and have 32G RAM installed,
|
||||
* then the mitigation range check in l1tf_select_mitigation() triggers.
|
||||
* This is a false positive because the mitigation is still possible due to
|
||||
* the fact that the cache uses 44bit internally. Use the cache bits
|
||||
* instead of the reported physical bits and adjust them on the affected
|
||||
* machines to 44bit if the reported bits are less than 44.
|
||||
*/
|
||||
static void override_cache_bits(struct cpuinfo_x86 *c)
|
||||
{
|
||||
if (c->x86 != 6)
|
||||
return;
|
||||
|
||||
switch (c->x86_model) {
|
||||
case INTEL_FAM6_NEHALEM:
|
||||
case INTEL_FAM6_WESTMERE:
|
||||
case INTEL_FAM6_SANDYBRIDGE:
|
||||
case INTEL_FAM6_IVYBRIDGE:
|
||||
case INTEL_FAM6_HASWELL_CORE:
|
||||
case INTEL_FAM6_HASWELL_ULT:
|
||||
case INTEL_FAM6_HASWELL_GT3E:
|
||||
case INTEL_FAM6_BROADWELL_CORE:
|
||||
case INTEL_FAM6_BROADWELL_GT3E:
|
||||
case INTEL_FAM6_SKYLAKE_MOBILE:
|
||||
case INTEL_FAM6_SKYLAKE_DESKTOP:
|
||||
case INTEL_FAM6_KABYLAKE_MOBILE:
|
||||
case INTEL_FAM6_KABYLAKE_DESKTOP:
|
||||
if (c->x86_cache_bits < 44)
|
||||
c->x86_cache_bits = 44;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void __init l1tf_select_mitigation(void)
|
||||
{
|
||||
u64 half_pa;
|
||||
|
|
@ -675,6 +714,8 @@ static void __init l1tf_select_mitigation(void)
|
|||
if (!boot_cpu_has_bug(X86_BUG_L1TF))
|
||||
return;
|
||||
|
||||
override_cache_bits(&boot_cpu_data);
|
||||
|
||||
switch (l1tf_mitigation) {
|
||||
case L1TF_MITIGATION_OFF:
|
||||
case L1TF_MITIGATION_FLUSH_NOWARN:
|
||||
|
|
@ -694,11 +735,6 @@ static void __init l1tf_select_mitigation(void)
|
|||
return;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This is extremely unlikely to happen because almost all
|
||||
* systems have far more MAX_PA/2 than RAM can be fit into
|
||||
* DIMM slots.
|
||||
*/
|
||||
half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
|
||||
if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
|
||||
pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
|
||||
|
|
|
|||
|
|
@ -919,6 +919,7 @@ void get_cpu_address_sizes(struct cpuinfo_x86 *c)
|
|||
else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
|
||||
c->x86_phys_bits = 36;
|
||||
#endif
|
||||
c->x86_cache_bits = c->x86_phys_bits;
|
||||
}
|
||||
|
||||
static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
|
||||
|
|
|
|||
|
|
@ -150,6 +150,9 @@ static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
|
|||
if (cpu_has(c, X86_FEATURE_HYPERVISOR))
|
||||
return false;
|
||||
|
||||
if (c->x86 != 6)
|
||||
return false;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
|
||||
if (c->x86_model == spectre_bad_microcodes[i].model &&
|
||||
c->x86_stepping == spectre_bad_microcodes[i].stepping)
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
#include <linux/bug.h>
|
||||
#include <linux/nmi.h>
|
||||
#include <linux/sysfs.h>
|
||||
#include <linux/kasan.h>
|
||||
|
||||
#include <asm/cpu_entry_area.h>
|
||||
#include <asm/stacktrace.h>
|
||||
|
|
@ -89,14 +90,24 @@ static void printk_stack_address(unsigned long address, int reliable,
|
|||
* Thus, the 2/3rds prologue and 64 byte OPCODE_BUFSIZE is just a random
|
||||
* guesstimate in attempt to achieve all of the above.
|
||||
*/
|
||||
void show_opcodes(u8 *rip, const char *loglvl)
|
||||
void show_opcodes(struct pt_regs *regs, const char *loglvl)
|
||||
{
|
||||
#define PROLOGUE_SIZE 42
|
||||
#define EPILOGUE_SIZE 21
|
||||
#define OPCODE_BUFSIZE (PROLOGUE_SIZE + 1 + EPILOGUE_SIZE)
|
||||
u8 opcodes[OPCODE_BUFSIZE];
|
||||
unsigned long prologue = regs->ip - PROLOGUE_SIZE;
|
||||
bool bad_ip;
|
||||
|
||||
if (probe_kernel_read(opcodes, rip - PROLOGUE_SIZE, OPCODE_BUFSIZE)) {
|
||||
/*
|
||||
* Make sure userspace isn't trying to trick us into dumping kernel
|
||||
* memory by pointing the userspace instruction pointer at it.
|
||||
*/
|
||||
bad_ip = user_mode(regs) &&
|
||||
__chk_range_not_ok(prologue, OPCODE_BUFSIZE, TASK_SIZE_MAX);
|
||||
|
||||
if (bad_ip || probe_kernel_read(opcodes, (u8 *)prologue,
|
||||
OPCODE_BUFSIZE)) {
|
||||
printk("%sCode: Bad RIP value.\n", loglvl);
|
||||
} else {
|
||||
printk("%sCode: %" __stringify(PROLOGUE_SIZE) "ph <%02x> %"
|
||||
|
|
@ -112,7 +123,7 @@ void show_ip(struct pt_regs *regs, const char *loglvl)
|
|||
#else
|
||||
printk("%sRIP: %04x:%pS\n", loglvl, (int)regs->cs, (void *)regs->ip);
|
||||
#endif
|
||||
show_opcodes((u8 *)regs->ip, loglvl);
|
||||
show_opcodes(regs, loglvl);
|
||||
}
|
||||
|
||||
void show_iret_regs(struct pt_regs *regs)
|
||||
|
|
@ -346,7 +357,10 @@ void oops_end(unsigned long flags, struct pt_regs *regs, int signr)
|
|||
* We're not going to return, but we might be on an IST stack or
|
||||
* have very little stack space left. Rewind the stack and kill
|
||||
* the task.
|
||||
* Before we rewind the stack, we have to tell KASAN that we're going to
|
||||
* reuse the task stack and that existing poisons are invalid.
|
||||
*/
|
||||
kasan_unpoison_task_stack(current);
|
||||
rewind_stack_do_exit(signr);
|
||||
}
|
||||
NOKPROBE_SYMBOL(oops_end);
|
||||
|
|
|
|||
|
|
@ -7,6 +7,8 @@
|
|||
#include <linux/uaccess.h>
|
||||
#include <linux/export.h>
|
||||
|
||||
#include <asm/tlbflush.h>
|
||||
|
||||
/*
|
||||
* We rely on the nested NMI work to allow atomic faults from the NMI path; the
|
||||
* nested NMI paths are careful to preserve CR2.
|
||||
|
|
@ -19,6 +21,9 @@ copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
|
|||
if (__range_not_ok(from, n, TASK_SIZE))
|
||||
return n;
|
||||
|
||||
if (!nmi_uaccess_okay())
|
||||
return n;
|
||||
|
||||
/*
|
||||
* Even though this function is typically called from NMI/IRQ context
|
||||
* disable pagefaults so that its behaviour is consistent even when
|
||||
|
|
|
|||
|
|
@ -837,7 +837,7 @@ show_signal_msg(struct pt_regs *regs, unsigned long error_code,
|
|||
|
||||
printk(KERN_CONT "\n");
|
||||
|
||||
show_opcodes((u8 *)regs->ip, loglvl);
|
||||
show_opcodes(regs, loglvl);
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
|
|||
|
|
@ -1420,6 +1420,29 @@ static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Machine check recovery code needs to change cache mode of poisoned
|
||||
* pages to UC to avoid speculative access logging another error. But
|
||||
* passing the address of the 1:1 mapping to set_memory_uc() is a fine
|
||||
* way to encourage a speculative access. So we cheat and flip the top
|
||||
* bit of the address. This works fine for the code that updates the
|
||||
* page tables. But at the end of the process we need to flush the cache
|
||||
* and the non-canonical address causes a #GP fault when used by the
|
||||
* CLFLUSH instruction.
|
||||
*
|
||||
* But in the common case we already have a canonical address. This code
|
||||
* will fix the top bit if needed and is a no-op otherwise.
|
||||
*/
|
||||
static inline unsigned long make_addr_canonical_again(unsigned long addr)
|
||||
{
|
||||
#ifdef CONFIG_X86_64
|
||||
return (long)(addr << 1) >> 1;
|
||||
#else
|
||||
return addr;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
static int change_page_attr_set_clr(unsigned long *addr, int numpages,
|
||||
pgprot_t mask_set, pgprot_t mask_clr,
|
||||
int force_split, int in_flag,
|
||||
|
|
@ -1465,7 +1488,7 @@ static int change_page_attr_set_clr(unsigned long *addr, int numpages,
|
|||
* Save address for cache flush. *addr is modified in the call
|
||||
* to __change_page_attr_set_clr() below.
|
||||
*/
|
||||
baddr = *addr;
|
||||
baddr = make_addr_canonical_again(*addr);
|
||||
}
|
||||
|
||||
/* Must avoid aliasing mappings in the highmem code */
|
||||
|
|
|
|||
|
|
@ -248,7 +248,7 @@ static pmd_t *pti_user_pagetable_walk_pmd(unsigned long address)
|
|||
*
|
||||
* Returns a pointer to a PTE on success, or NULL on failure.
|
||||
*/
|
||||
static __init pte_t *pti_user_pagetable_walk_pte(unsigned long address)
|
||||
static pte_t *pti_user_pagetable_walk_pte(unsigned long address)
|
||||
{
|
||||
gfp_t gfp = (GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO);
|
||||
pmd_t *pmd;
|
||||
|
|
|
|||
|
|
@ -305,6 +305,10 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
|
|||
|
||||
choose_new_asid(next, next_tlb_gen, &new_asid, &need_flush);
|
||||
|
||||
/* Let nmi_uaccess_okay() know that we're changing CR3. */
|
||||
this_cpu_write(cpu_tlbstate.loaded_mm, LOADED_MM_SWITCHING);
|
||||
barrier();
|
||||
|
||||
if (need_flush) {
|
||||
this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id);
|
||||
this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen);
|
||||
|
|
@ -335,6 +339,9 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
|
|||
if (next != &init_mm)
|
||||
this_cpu_write(cpu_tlbstate.last_ctx_id, next->context.ctx_id);
|
||||
|
||||
/* Make sure we write CR3 before loaded_mm. */
|
||||
barrier();
|
||||
|
||||
this_cpu_write(cpu_tlbstate.loaded_mm, next);
|
||||
this_cpu_write(cpu_tlbstate.loaded_mm_asid, new_asid);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -85,14 +85,10 @@ pgd_t * __init efi_call_phys_prolog(void)
|
|||
|
||||
void __init efi_call_phys_epilog(pgd_t *save_pgd)
|
||||
{
|
||||
struct desc_ptr gdt_descr;
|
||||
|
||||
gdt_descr.address = (unsigned long)get_cpu_gdt_rw(0);
|
||||
gdt_descr.size = GDT_SIZE - 1;
|
||||
load_gdt(&gdt_descr);
|
||||
|
||||
load_cr3(save_pgd);
|
||||
__flush_tlb_all();
|
||||
|
||||
load_fixmap_gdt(0);
|
||||
}
|
||||
|
||||
void __init efi_runtime_update_mappings(void)
|
||||
|
|
|
|||
|
|
@ -435,14 +435,13 @@ static void xen_set_pud(pud_t *ptr, pud_t val)
|
|||
static void xen_set_pte_atomic(pte_t *ptep, pte_t pte)
|
||||
{
|
||||
trace_xen_mmu_set_pte_atomic(ptep, pte);
|
||||
set_64bit((u64 *)ptep, native_pte_val(pte));
|
||||
__xen_set_pte(ptep, pte);
|
||||
}
|
||||
|
||||
static void xen_pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
|
||||
{
|
||||
trace_xen_mmu_pte_clear(mm, addr, ptep);
|
||||
if (!xen_batched_set_pte(ptep, native_make_pte(0)))
|
||||
native_pte_clear(mm, addr, ptep);
|
||||
__xen_set_pte(ptep, native_make_pte(0));
|
||||
}
|
||||
|
||||
static void xen_pmd_clear(pmd_t *pmdp)
|
||||
|
|
@ -1570,7 +1569,7 @@ static void __init xen_set_pte_init(pte_t *ptep, pte_t pte)
|
|||
pte = __pte_ma(((pte_val_ma(*ptep) & _PAGE_RW) | ~_PAGE_RW) &
|
||||
pte_val_ma(pte));
|
||||
#endif
|
||||
native_set_pte(ptep, pte);
|
||||
__xen_set_pte(ptep, pte);
|
||||
}
|
||||
|
||||
/* Early in boot, while setting up the initial pagetable, assume
|
||||
|
|
@ -2061,7 +2060,6 @@ void __init xen_relocate_p2m(void)
|
|||
pud_t *pud;
|
||||
pgd_t *pgd;
|
||||
unsigned long *new_p2m;
|
||||
int save_pud;
|
||||
|
||||
size = PAGE_ALIGN(xen_start_info->nr_pages * sizeof(unsigned long));
|
||||
n_pte = roundup(size, PAGE_SIZE) >> PAGE_SHIFT;
|
||||
|
|
@ -2091,7 +2089,6 @@ void __init xen_relocate_p2m(void)
|
|||
|
||||
pgd = __va(read_cr3_pa());
|
||||
new_p2m = (unsigned long *)(2 * PGDIR_SIZE);
|
||||
save_pud = n_pud;
|
||||
for (idx_pud = 0; idx_pud < n_pud; idx_pud++) {
|
||||
pud = early_memremap(pud_phys, PAGE_SIZE);
|
||||
clear_page(pud);
|
||||
|
|
|
|||
Loading…
Reference in a new issue