mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 03:01:39 -04:00
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (112 commits) sh: Move SH-4 CPU headers down one more level. sh: Only build in gpio.o when CONFIG_GENERIC_GPIO is selected. sh: Migrate common board headers to mach-common/. sh: Move the CPU definition headers from asm/ to cpu/. serial: sh-sci: Add support SCIF of SH7723 video: add sh_mobile_lcdc platform flags video: remove unused sh_mobile_lcdc platform data sh: remove consistent alloc cruft sh: add dynamic crash base address support sh: reduce Migo-R smc91x overruns sh: Fix up some merge damage. Fix debugfs_create_file's error checking method for arch/sh/mm/ Fix debugfs_create_dir's error checking method for arch/sh/kernel/ sh: ap325rxa: Add support RTC RX-8564LC in AP325RXA board sh: Use sh7720 GPIO on magicpanelr2 board sh: Add sh7720 pinmux code sh: Use sh7203 GPIO on rsk7203 board sh: Add sh7203 pinmux code sh: Use sh7723 GPIO on AP325RXA board sh: Add sh7723 pinmux code ...
This commit is contained in:
Linus Torvalds
commit
ed402af3c2
176 changed files with 13195 additions and 1219 deletions
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@ -3,7 +3,7 @@
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*
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* SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
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*
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* Copyright (C) 2002 - 2006 Paul Mundt
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* Copyright (C) 2002 - 2008 Paul Mundt
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* Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
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*
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* based off of the old drivers/char/sh-sci.c by:
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@ -46,6 +46,7 @@
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#include <linux/cpufreq.h>
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#include <linux/clk.h>
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#include <linux/ctype.h>
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#include <linux/err.h>
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#ifdef CONFIG_SUPERH
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#include <asm/clock.h>
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@ -78,7 +79,7 @@ struct sci_port {
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struct timer_list break_timer;
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int break_flag;
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#ifdef CONFIG_SUPERH
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#ifdef CONFIG_HAVE_CLK
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/* Port clock */
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struct clk *clk;
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#endif
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@ -831,7 +832,7 @@ static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
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return IRQ_HANDLED;
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}
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#ifdef CONFIG_CPU_FREQ
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#if defined(CONFIG_CPU_FREQ) && defined(CONFIG_HAVE_CLK)
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/*
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* Here we define a transistion notifier so that we can update all of our
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* ports' baud rate when the peripheral clock changes.
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@ -860,7 +861,7 @@ static int sci_notifier(struct notifier_block *self,
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* Clean this up later..
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*/
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clk = clk_get(NULL, "module_clk");
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port->uartclk = clk_get_rate(clk) * 16;
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port->uartclk = clk_get_rate(clk);
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clk_put(clk);
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}
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@ -873,7 +874,7 @@ static int sci_notifier(struct notifier_block *self,
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}
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static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
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#endif /* CONFIG_CPU_FREQ */
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#endif /* CONFIG_CPU_FREQ && CONFIG_HAVE_CLK */
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static int sci_request_irq(struct sci_port *port)
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{
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@ -1008,7 +1009,7 @@ static int sci_startup(struct uart_port *port)
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if (s->enable)
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s->enable(port);
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#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
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#ifdef CONFIG_HAVE_CLK
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s->clk = clk_get(NULL, "module_clk");
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#endif
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@ -1030,7 +1031,7 @@ static void sci_shutdown(struct uart_port *port)
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if (s->disable)
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s->disable(port);
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#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
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#ifdef CONFIG_HAVE_CLK
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clk_put(s->clk);
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s->clk = NULL;
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#endif
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@ -1041,24 +1042,11 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
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{
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struct sci_port *s = &sci_ports[port->line];
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unsigned int status, baud, smr_val;
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int t;
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int t = -1;
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baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
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switch (baud) {
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case 0:
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t = -1;
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break;
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default:
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{
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#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
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t = SCBRR_VALUE(baud, clk_get_rate(s->clk));
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#else
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t = SCBRR_VALUE(baud);
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#endif
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break;
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}
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}
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if (likely(baud))
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t = SCBRR_VALUE(baud, port->uartclk);
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do {
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status = sci_in(port, SCxSR);
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@ -1113,7 +1101,7 @@ static const char *sci_type(struct uart_port *port)
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case PORT_IRDA: return "irda";
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}
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return 0;
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return NULL;
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}
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static void sci_release_port(struct uart_port *port)
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@ -1145,12 +1133,16 @@ static void sci_config_port(struct uart_port *port, int flags)
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break;
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}
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#if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
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if (port->mapbase == 0)
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if (port->flags & UPF_IOREMAP && !port->membase) {
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#if defined(CONFIG_SUPERH64)
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port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
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port->membase = (void __iomem *)port->mapbase;
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port->membase = (void __iomem *)port->mapbase;
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#else
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port->membase = ioremap_nocache(port->mapbase, 0x40);
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#endif
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printk(KERN_ERR "sci: can't remap port#%d\n", port->line);
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}
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}
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static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
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@ -1207,17 +1199,17 @@ static void __init sci_init_ports(void)
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sci_ports[i].disable = h8300_sci_disable;
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#endif
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sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
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#elif defined(CONFIG_SUPERH64)
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sci_ports[i].port.uartclk = current_cpu_data.module_clock * 16;
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#else
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#elif defined(CONFIG_HAVE_CLK)
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/*
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* XXX: We should use a proper SCI/SCIF clock
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*/
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{
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struct clk *clk = clk_get(NULL, "module_clk");
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sci_ports[i].port.uartclk = clk_get_rate(clk) * 16;
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sci_ports[i].port.uartclk = clk_get_rate(clk);
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clk_put(clk);
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}
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#else
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#error "Need a valid uartclk"
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#endif
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sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
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@ -1285,7 +1277,7 @@ static int __init serial_console_setup(struct console *co, char *options)
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port->type = serial_console_port->type;
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#if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
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#ifdef CONFIG_HAVE_CLK
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if (!serial_console_port->clk)
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serial_console_port->clk = clk_get(NULL, "module_clk");
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#endif
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@ -1436,7 +1428,7 @@ static struct uart_driver sci_uart_driver = {
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static int __devinit sci_probe(struct platform_device *dev)
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{
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struct plat_sci_port *p = dev->dev.platform_data;
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int i;
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int i, ret = -EINVAL;
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for (i = 0; p && p->flags != 0; p++, i++) {
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struct sci_port *sciport = &sci_ports[i];
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@ -1453,12 +1445,22 @@ static int __devinit sci_probe(struct platform_device *dev)
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sciport->port.mapbase = p->mapbase;
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/*
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* For the simple (and majority of) cases where we don't need
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* to do any remapping, just cast the cookie directly.
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*/
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if (p->mapbase && !p->membase && !(p->flags & UPF_IOREMAP))
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p->membase = (void __iomem *)p->mapbase;
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if (p->mapbase && !p->membase) {
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if (p->flags & UPF_IOREMAP) {
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p->membase = ioremap_nocache(p->mapbase, 0x40);
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if (IS_ERR(p->membase)) {
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ret = PTR_ERR(p->membase);
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goto err_unreg;
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}
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} else {
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/*
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* For the simple (and majority of) cases
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* where we don't need to do any remapping,
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* just cast the cookie directly.
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*/
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p->membase = (void __iomem *)p->mapbase;
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}
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}
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sciport->port.membase = p->membase;
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@ -1479,7 +1481,7 @@ static int __devinit sci_probe(struct platform_device *dev)
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kgdb_putchar = kgdb_sci_putchar;
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#endif
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#ifdef CONFIG_CPU_FREQ
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#if defined(CONFIG_CPU_FREQ) && defined(CONFIG_HAVE_CLK)
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cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
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dev_info(&dev->dev, "CPU frequency notifier registered\n");
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#endif
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@ -1489,6 +1491,12 @@ static int __devinit sci_probe(struct platform_device *dev)
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#endif
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return 0;
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err_unreg:
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for (i = i - 1; i >= 0; i--)
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uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
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return ret;
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}
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static int __devexit sci_remove(struct platform_device *dev)
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@ -320,18 +320,16 @@
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#define SCI_EVENT_WRITE_WAKEUP 0
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#define SCI_IN(size, offset) \
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unsigned int addr = port->mapbase + (offset); \
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if ((size) == 8) { \
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return ctrl_inb(addr); \
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return ioread8(port->membase + (offset)); \
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} else { \
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return ctrl_inw(addr); \
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return ioread16(port->membase + (offset)); \
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}
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#define SCI_OUT(size, offset, value) \
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unsigned int addr = port->mapbase + (offset); \
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if ((size) == 8) { \
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ctrl_outb(value, addr); \
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iowrite8(value, port->membase + (offset)); \
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} else if ((size) == 16) { \
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ctrl_outw(value, addr); \
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iowrite16(value, port->membase + (offset)); \
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}
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#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
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@ -791,11 +789,16 @@ static inline int sci_rxd_in(struct uart_port *port)
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defined(CONFIG_CPU_SUBTYPE_SH7721)
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#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
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#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(16*bps)-1)
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static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
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{
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if (port->type == PORT_SCIF)
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return (clk+16*bps)/(32*bps)-1;
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else
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return ((clk*2)+16*bps)/(16*bps)-1;
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}
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#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
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#elif defined(__H8300H__) || defined(__H8300S__)
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#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
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#elif defined(CONFIG_SUPERH64)
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#define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
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#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
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#else /* Generic SH */
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#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
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#endif
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