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clk: gxbb: expose MPLL2 clock for use by DT
This exposes the MPLL2 clock as this is one of the input clocks of the ethernet controller's internal mux. Signed-off-by: Martin Blumenstingl <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Kevin Hilman <[email protected]>
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2 changed files with 2 additions and 1 deletions
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@ -183,7 +183,7 @@
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/* CLKID_CLK81 */
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#define CLKID_MPLL0 13
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#define CLKID_MPLL1 14
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#define CLKID_MPLL2 15
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/* CLKID_MPLL2 */
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#define CLKID_DDR 16
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#define CLKID_DOS 17
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#define CLKID_ISA 18
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