clk: gxbb: expose MPLL2 clock for use by DT

This exposes the MPLL2 clock as this is one of the input clocks of the
ethernet controller's internal mux.

Signed-off-by: Martin Blumenstingl <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Kevin Hilman <[email protected]>
This commit is contained in:
Martin Blumenstingl 2016-09-06 23:38:44 +02:00 • committed by Kevin Hilman
commit ed6f4b5180
2 changed files with 2 additions and 1 deletions

View file

@ -11,6 +11,7 @@
#define CLKID_FCLK_DIV3 5
#define CLKID_FCLK_DIV4 6
#define CLKID_CLK81 12
#define CLKID_MPLL2 15
#define CLKID_ETH 36
#define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95