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clk: gxbb: expose MPLL2 clock for use by DT
This exposes the MPLL2 clock as this is one of the input clocks of the ethernet controller's internal mux. Signed-off-by: Martin Blumenstingl <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Kevin Hilman <[email protected]>
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2 changed files with 2 additions and 1 deletions
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@ -11,6 +11,7 @@
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#define CLKID_FCLK_DIV3 5
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#define CLKID_FCLK_DIV4 6
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#define CLKID_CLK81 12
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#define CLKID_MPLL2 15
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#define CLKID_ETH 36
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#define CLKID_SD_EMMC_A 94
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#define CLKID_SD_EMMC_B 95
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