From 9a381b30f80df711f5728cfb5b5d89c1b193562c Mon Sep 17 00:00:00 2001
From: Naina Mehta <nainmeht@qti.qualcomm.com>
Date: Mon, 16 Nov 2020 12:27:36 +0530
Subject: [PATCH 1/2] ARM: dts: msm: Add scm pas node

Add scm pas node for Yupik platform.

Change-Id: Id1c1e3032a57a5aef617baa80eeacf4411bf6192
---
 qcom/yupik.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi
index cc04ff320e6e..fdb89bb4acec 100644
--- a/qcom/yupik.dtsi
+++ b/qcom/yupik.dtsi
@@ -1154,6 +1154,11 @@
 	qcom-secure-buffer {
 		compatible = "qcom,secure-buffer";
 	};
+
+	pil_scm_pas {
+		compatible = "qcom,pil-tz-scm-pas";
+		interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
+	};
 };
 
 #include "shima-gdsc.dtsi"

From e3b04e8a9de01e77dab5baac52a954be29a3e245 Mon Sep 17 00:00:00 2001
From: Naina Mehta <nainmeht@qti.qualcomm.com>
Date: Thu, 29 Oct 2020 17:50:34 +0530
Subject: [PATCH 2/2] ARM: dts: msm: Add LPASS pil node for Yupik

Add LPASS pil node to support LPASS subsystem for Yupik
platform.

Change-Id: I9d38b38f38e0fffa79844949d98fd9bf83ee6779
---
 qcom/yupik.dtsi | 47 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi
index fdb89bb4acec..5da945d70e97 100644
--- a/qcom/yupik.dtsi
+++ b/qcom/yupik.dtsi
@@ -12,6 +12,7 @@
 #include <dt-bindings/soc/qcom,ipcc.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. Yupik";
@@ -1159,6 +1160,52 @@
 		compatible = "qcom,pil-tz-scm-pas";
 		interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
 	};
+
+	qcom,lpass@3700000 {
+		compatible = "qcom,pil-tz-generic";
+		reg = <0x3700000 0x00100>;
+
+		vdd_cx-supply = <&VDD_LPI_CX_LEVEL>;
+		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+		vdd_mx-supply = <&VDD_LPI_MX_LEVEL>;
+		qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+		qcom,proxy-reg-names = "vdd_cx","vdd_mx";
+
+		clocks = <&rpmhcc RPMH_CXO_CLK>;
+		clock-names = "xo";
+		qcom,proxy-clock-names = "xo";
+
+		qcom,pas-id = <1>;
+		qcom,proxy-timeout-ms = <10000>;
+		qcom,smem-id = <423>;
+		qcom,sysmon-id = <1>;
+		qcom,ssctl-instance-id = <0x14>;
+		qcom,firmware-name = "adsp";
+		memory-region = <&pil_adsp_mem>;
+		qcom,complete-ramdump;
+
+		/* Inputs from lpass */
+		interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
+				<&adsp_smp2p_in 0 0>,
+				<&adsp_smp2p_in 2 0>,
+				<&adsp_smp2p_in 1 0>,
+				<&adsp_smp2p_in 3 0>,
+				<&adsp_smp2p_in 7 0>;
+
+		interrupt-names = "qcom,wdog",
+				"qcom,err-fatal",
+				"qcom,proxy-unvote",
+				"qcom,err-ready",
+				"qcom,stop-ack",
+				"qcom,shutdown-ack";
+
+		/* Outputs to lpass */
+		qcom,smem-states = <&adsp_smp2p_out 0>;
+		qcom,smem-state-names = "qcom,force-stop";
+
+		mboxes = <&qmp_aop 0>;
+		mbox-names = "adsp-pil";
+	};
 };
 
 #include "shima-gdsc.dtsi"