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fw-api: fig: v1 remove unused reo hw data structure files

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Remove REO hw data structures not used on fig.

Change-Id: I3c11ee11f2d69f4873dae60b0534898931556364
CRs-Fixed: 4344733
This commit is contained in:
Prakash Manjunathappa 2025-10-30 01:15:24 -07:00
commit ed981aa515
21 changed files with 0 additions and 4710 deletions
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257
hw/fig/v1/reo_descriptor_threshold_reached_status.h
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@ -1,257 +0,0 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
#include "uniform_reo_status_header.h"
#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 26
#define NUM_OF_QWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 13
struct reo_descriptor_threshold_reached_status {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct uniform_reo_status_header status_header;
uint32_t threshold_index : 2,
reserved_2 : 30;
uint32_t link_descriptor_counter0 : 24,
reserved_3 : 8;
uint32_t link_descriptor_counter1 : 24,
reserved_4 : 8;
uint32_t link_descriptor_counter2 : 24,
reserved_5 : 8;
uint32_t link_descriptor_counter_sum : 26,
reserved_6 : 6;
uint32_t reserved_7 : 32;
uint32_t reserved_8 : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t reserved_25a : 28,
looping_count : 4;
#else
struct uniform_reo_status_header status_header;
uint32_t reserved_2 : 30,
threshold_index : 2;
uint32_t reserved_3 : 8,
link_descriptor_counter0 : 24;
uint32_t reserved_4 : 8,
link_descriptor_counter1 : 24;
uint32_t reserved_5 : 8,
link_descriptor_counter2 : 24;
uint32_t reserved_6 : 6,
link_descriptor_counter_sum : 26;
uint32_t reserved_7 : 32;
uint32_t reserved_8 : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t looping_count : 4,
reserved_25a : 28;
#endif
};
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_OFFSET 0x0000000000000008
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MSB 1
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MASK 0x0000000000000003
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_OFFSET 0x0000000000000008
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_LSB 2
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MASK 0x00000000fffffffc
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000000000008
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MSB 55
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_OFFSET 0x0000000000000008
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_LSB 56
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MASK 0xff00000000000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x0000000000000010
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MSB 23
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MASK 0x0000000000ffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_OFFSET 0x0000000000000010
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_LSB 24
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MASK 0x00000000ff000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x0000000000000010
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MSB 55
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_OFFSET 0x0000000000000010
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_LSB 56
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MASK 0xff00000000000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x0000000000000018
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MSB 25
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x0000000003ffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_OFFSET 0x0000000000000018
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_LSB 26
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MASK 0x00000000fc000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_OFFSET 0x0000000000000018
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_OFFSET 0x0000000000000020
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_OFFSET 0x0000000000000020
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_OFFSET 0x0000000000000028
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_OFFSET 0x0000000000000028
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_OFFSET 0x0000000000000030
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_OFFSET 0x0000000000000030
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_OFFSET 0x0000000000000038
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_OFFSET 0x0000000000000038
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_OFFSET 0x0000000000000040
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_OFFSET 0x0000000000000040
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_OFFSET 0x0000000000000048
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_OFFSET 0x0000000000000048
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_OFFSET 0x0000000000000050
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_OFFSET 0x0000000000000058
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_OFFSET 0x0000000000000058
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MASK 0xffffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_LSB 0
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MSB 31
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MASK 0x00000000ffffffff
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_LSB 32
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MSB 59
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_LSB 60
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MSB 63
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
#endif

156
hw/fig/v1/reo_flush_cache.h
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@ -1,156 +0,0 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _REO_FLUSH_CACHE_H_
#define _REO_FLUSH_CACHE_H_
#include "uniform_reo_cmd_header.h"
#define NUM_OF_DWORDS_REO_FLUSH_CACHE 10
#define NUM_OF_QWORDS_REO_FLUSH_CACHE 5
struct reo_flush_cache {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct uniform_reo_cmd_header cmd_header;
uint32_t flush_addr_31_0 : 32;
uint32_t flush_addr_39_32 : 8,
forward_all_mpdus_in_queue : 1,
release_cache_block_index : 1,
cache_block_resource_index : 2,
flush_without_invalidate : 1,
block_cache_usage_after_flush : 1,
flush_entire_cache : 1,
flush_queue_1k_desc : 1,
reserved_2b : 16;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t tlv64_padding : 32;
#else
struct uniform_reo_cmd_header cmd_header;
uint32_t flush_addr_31_0 : 32;
uint32_t reserved_2b : 16,
flush_queue_1k_desc : 1,
flush_entire_cache : 1,
block_cache_usage_after_flush : 1,
flush_without_invalidate : 1,
cache_block_resource_index : 2,
release_cache_block_index : 1,
forward_all_mpdus_in_queue : 1,
flush_addr_39_32 : 8;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t tlv64_padding : 32;
#endif
};
#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31
#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 32
#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 63
#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0
#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7
#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x00000000000000ff
#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8
#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8
#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x0000000000000100
#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9
#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9
#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x0000000000000200
#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10
#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11
#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000c00
#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12
#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12
#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x0000000000001000
#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13
#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13
#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x0000000000002000
#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14
#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14
#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x0000000000004000
#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15
#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15
#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x0000000000008000
#define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_RESERVED_2B_LSB 16
#define REO_FLUSH_CACHE_RESERVED_2B_MSB 31
#define REO_FLUSH_CACHE_RESERVED_2B_MASK 0x00000000ffff0000
#define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_RESERVED_3A_LSB 32
#define REO_FLUSH_CACHE_RESERVED_3A_MSB 63
#define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_FLUSH_CACHE_RESERVED_4A_LSB 0
#define REO_FLUSH_CACHE_RESERVED_4A_MSB 31
#define REO_FLUSH_CACHE_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_FLUSH_CACHE_RESERVED_5A_LSB 32
#define REO_FLUSH_CACHE_RESERVED_5A_MSB 63
#define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_FLUSH_CACHE_RESERVED_6A_LSB 0
#define REO_FLUSH_CACHE_RESERVED_6A_MSB 31
#define REO_FLUSH_CACHE_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_FLUSH_CACHE_RESERVED_7A_LSB 32
#define REO_FLUSH_CACHE_RESERVED_7A_MSB 63
#define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_FLUSH_CACHE_RESERVED_8A_LSB 0
#define REO_FLUSH_CACHE_RESERVED_8A_MSB 31
#define REO_FLUSH_CACHE_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020
#define REO_FLUSH_CACHE_TLV64_PADDING_LSB 32
#define REO_FLUSH_CACHE_TLV64_PADDING_MSB 63
#define REO_FLUSH_CACHE_TLV64_PADDING_MASK 0xffffffff00000000
#endif

285
hw/fig/v1/reo_flush_cache_status.h
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@ -1,285 +0,0 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _REO_FLUSH_CACHE_STATUS_H_
#define _REO_FLUSH_CACHE_STATUS_H_
#include "uniform_reo_status_header.h"
#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 26
#define NUM_OF_QWORDS_REO_FLUSH_CACHE_STATUS 13
struct reo_flush_cache_status {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct uniform_reo_status_header status_header;
uint32_t error_detected : 1,
block_error_details : 2,
reserved_2a : 5,
cache_controller_flush_status_hit : 1,
cache_controller_flush_status_desc_type : 3,
cache_controller_flush_status_client_id : 4,
cache_controller_flush_status_error : 2,
cache_controller_flush_count : 8,
flush_queue_1k_desc : 1,
reserved_2b : 5;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t reserved_25a : 28,
looping_count : 4;
#else
struct uniform_reo_status_header status_header;
uint32_t reserved_2b : 5,
flush_queue_1k_desc : 1,
cache_controller_flush_count : 8,
cache_controller_flush_status_error : 2,
cache_controller_flush_status_client_id : 4,
cache_controller_flush_status_desc_type : 3,
cache_controller_flush_status_hit : 1,
reserved_2a : 5,
block_error_details : 2,
error_detected : 1;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t looping_count : 4,
reserved_25a : 28;
#endif
};
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB 0
#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB 0
#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001
#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB 1
#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB 2
#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK 0x0000000000000006
#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB 3
#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB 7
#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK 0x00000000000000f8
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB 8
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x0000000000000100
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB 11
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x0000000000000e00
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB 15
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x000000000000f000
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB 17
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x0000000000030000
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB 25
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x0000000003fc0000
#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB 26
#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB 26
#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK 0x0000000004000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB 27
#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK 0x00000000f8000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020
#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028
#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028
#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030
#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030
#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038
#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038
#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040
#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040
#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048
#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048
#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050
#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058
#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058
#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB 63
#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000
#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB 0
#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB 31
#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff
#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB 32
#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB 59
#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB 60
#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB 63
#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
#endif

121
hw/fig/v1/reo_flush_queue.h
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _REO_FLUSH_QUEUE_H_
#define _REO_FLUSH_QUEUE_H_
#include "uniform_reo_cmd_header.h"
#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 10
#define NUM_OF_QWORDS_REO_FLUSH_QUEUE 5
struct reo_flush_queue {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct uniform_reo_cmd_header cmd_header;
uint32_t flush_desc_addr_31_0 : 32;
uint32_t flush_desc_addr_39_32 : 8,
block_desc_addr_usage_after_flush : 1,
block_resource_index : 2,
reserved_2a : 21;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t tlv64_padding : 32;
#else
struct uniform_reo_cmd_header cmd_header;
uint32_t flush_desc_addr_31_0 : 32;
uint32_t reserved_2a : 21,
block_resource_index : 2,
block_desc_addr_usage_after_flush : 1,
flush_desc_addr_39_32 : 8;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t tlv64_padding : 32;
#endif
};
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31
#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 32
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 63
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x00000000000000ff
#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8
#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8
#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x0000000000000100
#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9
#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10
#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000600
#define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_RESERVED_2A_LSB 11
#define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31
#define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0x00000000fffff800
#define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_RESERVED_3A_LSB 32
#define REO_FLUSH_QUEUE_RESERVED_3A_MSB 63
#define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0
#define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31
#define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_FLUSH_QUEUE_RESERVED_5A_LSB 32
#define REO_FLUSH_QUEUE_RESERVED_5A_MSB 63
#define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0
#define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31
#define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_FLUSH_QUEUE_RESERVED_7A_LSB 32
#define REO_FLUSH_QUEUE_RESERVED_7A_MSB 63
#define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0
#define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31
#define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020
#define REO_FLUSH_QUEUE_TLV64_PADDING_LSB 32
#define REO_FLUSH_QUEUE_TLV64_PADDING_MSB 63
#define REO_FLUSH_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000
#endif

229
hw/fig/v1/reo_flush_queue_status.h
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _REO_FLUSH_QUEUE_STATUS_H_
#define _REO_FLUSH_QUEUE_STATUS_H_
#include "uniform_reo_status_header.h"
#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 26
#define NUM_OF_QWORDS_REO_FLUSH_QUEUE_STATUS 13
struct reo_flush_queue_status {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct uniform_reo_status_header status_header;
uint32_t error_detected : 1,
reserved_2a : 31;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t reserved_25a : 28,
looping_count : 4;
#else
struct uniform_reo_status_header status_header;
uint32_t reserved_2a : 31,
error_detected : 1;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t looping_count : 4,
reserved_25a : 28;
#endif
};
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_LSB 0
#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MSB 0
#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001
#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_LSB 1
#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000fffffffe
#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020
#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028
#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028
#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030
#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030
#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038
#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038
#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040
#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040
#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048
#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048
#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050
#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058
#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058
#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MSB 63
#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000
#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_LSB 0
#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MSB 31
#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff
#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_LSB 32
#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MSB 59
#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_LSB 60
#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MSB 63
#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
#endif

114
hw/fig/v1/reo_flush_timeout_list.h
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@ -1,114 +0,0 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _REO_FLUSH_TIMEOUT_LIST_H_
#define _REO_FLUSH_TIMEOUT_LIST_H_
#include "uniform_reo_cmd_header.h"
#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 10
#define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST 5
struct reo_flush_timeout_list {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct uniform_reo_cmd_header cmd_header;
uint32_t ac_timout_list : 2,
reserved_1 : 30;
uint32_t minimum_release_desc_count : 16,
minimum_forward_buf_count : 16;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t tlv64_padding : 32;
#else
struct uniform_reo_cmd_header cmd_header;
uint32_t reserved_1 : 30,
ac_timout_list : 2;
uint32_t minimum_forward_buf_count : 16,
minimum_release_desc_count : 16;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t tlv64_padding : 32;
#endif
};
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MSB 15
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MSB 33
#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MASK 0x0000000300000000
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_LSB 34
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MASK 0xfffffffc00000000
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MSB 15
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MASK 0x000000000000ffff
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_LSB 16
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MASK 0x00000000ffff0000
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_OFFSET 0x0000000000000020
#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MASK 0xffffffff00000000
#endif

243
hw/fig/v1/reo_flush_timeout_list_status.h
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@ -1,243 +0,0 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
#include "uniform_reo_status_header.h"
#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 26
#define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 13
struct reo_flush_timeout_list_status {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct uniform_reo_status_header status_header;
uint32_t error_detected : 1,
timout_list_empty : 1,
reserved_2a : 30;
uint32_t release_desc_count : 16,
forward_buf_count : 16;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t reserved_25a : 28,
looping_count : 4;
#else
struct uniform_reo_status_header status_header;
uint32_t reserved_2a : 30,
timout_list_empty : 1,
error_detected : 1;
uint32_t forward_buf_count : 16,
release_desc_count : 16;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t looping_count : 4,
reserved_25a : 28;
#endif
};
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MASK 0x0000000000000001
#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_LSB 1
#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MSB 1
#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MASK 0x0000000000000002
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_LSB 2
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MASK 0x00000000fffffffc
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MSB 47
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MASK 0x0000ffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008
#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_LSB 48
#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MASK 0xffff000000000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_OFFSET 0x0000000000000020
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_OFFSET 0x0000000000000028
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_OFFSET 0x0000000000000028
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_OFFSET 0x0000000000000030
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_OFFSET 0x0000000000000030
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_OFFSET 0x0000000000000038
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_OFFSET 0x0000000000000038
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_OFFSET 0x0000000000000040
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_OFFSET 0x0000000000000040
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_OFFSET 0x0000000000000048
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_OFFSET 0x0000000000000048
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_OFFSET 0x0000000000000050
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_OFFSET 0x0000000000000058
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_OFFSET 0x0000000000000058
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MASK 0xffffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_LSB 0
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MSB 31
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MASK 0x00000000ffffffff
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_LSB 32
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MSB 59
#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_LSB 60
#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MSB 63
#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
#endif

114
hw/fig/v1/reo_get_queue_stats.h
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@ -1,114 +0,0 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _REO_GET_QUEUE_STATS_H_
#define _REO_GET_QUEUE_STATS_H_
#include "uniform_reo_cmd_header.h"
#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 10
#define NUM_OF_QWORDS_REO_GET_QUEUE_STATS 5
struct reo_get_queue_stats {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct uniform_reo_cmd_header cmd_header;
uint32_t rx_reo_queue_desc_addr_31_0 : 32;
uint32_t rx_reo_queue_desc_addr_39_32 : 8,
clear_stats : 1,
reserved_2a : 23;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t tlv64_padding : 32;
#else
struct uniform_reo_cmd_header cmd_header;
uint32_t rx_reo_queue_desc_addr_31_0 : 32;
uint32_t reserved_2a : 23,
clear_stats : 1,
rx_reo_queue_desc_addr_39_32 : 8;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t tlv64_padding : 32;
#endif
};
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MSB 15
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MSB 31
#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7
#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff
#define REO_GET_QUEUE_STATS_CLEAR_STATS_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_CLEAR_STATS_LSB 8
#define REO_GET_QUEUE_STATS_CLEAR_STATS_MSB 8
#define REO_GET_QUEUE_STATS_CLEAR_STATS_MASK 0x0000000000000100
#define REO_GET_QUEUE_STATS_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_RESERVED_2A_LSB 9
#define REO_GET_QUEUE_STATS_RESERVED_2A_MSB 31
#define REO_GET_QUEUE_STATS_RESERVED_2A_MASK 0x00000000fffffe00
#define REO_GET_QUEUE_STATS_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_RESERVED_3A_LSB 32
#define REO_GET_QUEUE_STATS_RESERVED_3A_MSB 63
#define REO_GET_QUEUE_STATS_RESERVED_3A_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_GET_QUEUE_STATS_RESERVED_4A_LSB 0
#define REO_GET_QUEUE_STATS_RESERVED_4A_MSB 31
#define REO_GET_QUEUE_STATS_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_GET_QUEUE_STATS_RESERVED_5A_LSB 32
#define REO_GET_QUEUE_STATS_RESERVED_5A_MSB 63
#define REO_GET_QUEUE_STATS_RESERVED_5A_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_GET_QUEUE_STATS_RESERVED_6A_LSB 0
#define REO_GET_QUEUE_STATS_RESERVED_6A_MSB 31
#define REO_GET_QUEUE_STATS_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_GET_QUEUE_STATS_RESERVED_7A_LSB 32
#define REO_GET_QUEUE_STATS_RESERVED_7A_MSB 63
#define REO_GET_QUEUE_STATS_RESERVED_7A_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_GET_QUEUE_STATS_RESERVED_8A_LSB 0
#define REO_GET_QUEUE_STATS_RESERVED_8A_MSB 31
#define REO_GET_QUEUE_STATS_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_TLV64_PADDING_OFFSET 0x0000000000000020
#define REO_GET_QUEUE_STATS_TLV64_PADDING_LSB 32
#define REO_GET_QUEUE_STATS_TLV64_PADDING_MSB 63
#define REO_GET_QUEUE_STATS_TLV64_PADDING_MASK 0xffffffff00000000
#endif

306
hw/fig/v1/reo_get_queue_stats_status.h
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@ -1,306 +0,0 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _REO_GET_QUEUE_STATS_STATUS_H_
#define _REO_GET_QUEUE_STATS_STATUS_H_
#include "uniform_reo_status_header.h"
#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 26
#define NUM_OF_QWORDS_REO_GET_QUEUE_STATS_STATUS 13
struct reo_get_queue_stats_status {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct uniform_reo_status_header status_header;
uint32_t ssn : 12,
current_index : 10,
reserved_2 : 10;
uint32_t pn_31_0 : 32;
uint32_t pn_63_32 : 32;
uint32_t pn_95_64 : 32;
uint32_t pn_127_96 : 32;
uint32_t last_rx_enqueue_timestamp : 32;
uint32_t last_rx_dequeue_timestamp : 32;
uint32_t rx_bitmap_31_0 : 32;
uint32_t rx_bitmap_63_32 : 32;
uint32_t rx_bitmap_95_64 : 32;
uint32_t rx_bitmap_127_96 : 32;
uint32_t rx_bitmap_159_128 : 32;
uint32_t rx_bitmap_191_160 : 32;
uint32_t rx_bitmap_223_192 : 32;
uint32_t rx_bitmap_255_224 : 32;
uint32_t rx_bitmap_287_256 : 32;
uint32_t current_mpdu_count : 7,
current_msdu_count : 25;
uint32_t window_jump_2k : 4,
timeout_count : 6,
forward_due_to_bar_count : 6,
duplicate_count : 16;
uint32_t frames_in_order_count : 24,
bar_received_count : 8;
uint32_t mpdu_frames_processed_count : 32;
uint32_t msdu_frames_processed_count : 32;
uint32_t total_processed_byte_count : 32;
uint32_t late_receive_mpdu_count : 12,
hole_count : 16,
get_queue_1k_stats_status_to_follow : 1,
reserved_24a : 3;
uint32_t aging_drop_mpdu_count : 16,
aging_drop_interval : 8,
reserved_25a : 4,
looping_count : 4;
#else
struct uniform_reo_status_header status_header;
uint32_t reserved_2 : 10,
current_index : 10,
ssn : 12;
uint32_t pn_31_0 : 32;
uint32_t pn_63_32 : 32;
uint32_t pn_95_64 : 32;
uint32_t pn_127_96 : 32;
uint32_t last_rx_enqueue_timestamp : 32;
uint32_t last_rx_dequeue_timestamp : 32;
uint32_t rx_bitmap_31_0 : 32;
uint32_t rx_bitmap_63_32 : 32;
uint32_t rx_bitmap_95_64 : 32;
uint32_t rx_bitmap_127_96 : 32;
uint32_t rx_bitmap_159_128 : 32;
uint32_t rx_bitmap_191_160 : 32;
uint32_t rx_bitmap_223_192 : 32;
uint32_t rx_bitmap_255_224 : 32;
uint32_t rx_bitmap_287_256 : 32;
uint32_t current_msdu_count : 25,
current_mpdu_count : 7;
uint32_t duplicate_count : 16,
forward_due_to_bar_count : 6,
timeout_count : 6,
window_jump_2k : 4;
uint32_t bar_received_count : 8,
frames_in_order_count : 24;
uint32_t mpdu_frames_processed_count : 32;
uint32_t msdu_frames_processed_count : 32;
uint32_t total_processed_byte_count : 32;
uint32_t reserved_24a : 3,
get_queue_1k_stats_status_to_follow : 1,
hole_count : 16,
late_receive_mpdu_count : 12;
uint32_t looping_count : 4,
reserved_25a : 4,
aging_drop_interval : 8,
aging_drop_mpdu_count : 16;
#endif
};
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_SSN_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_STATUS_SSN_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_SSN_MSB 11
#define REO_GET_QUEUE_STATS_STATUS_SSN_MASK 0x0000000000000fff
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_LSB 12
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MSB 21
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MASK 0x00000000003ff000
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_LSB 22
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MASK 0x00000000ffc00000
#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_OFFSET 0x0000000000000008
#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_OFFSET 0x0000000000000010
#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_OFFSET 0x0000000000000010
#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_OFFSET 0x0000000000000018
#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x0000000000000018
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x0000000000000020
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_OFFSET 0x0000000000000020
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_OFFSET 0x0000000000000028
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_OFFSET 0x0000000000000028
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_OFFSET 0x0000000000000030
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_OFFSET 0x0000000000000030
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_OFFSET 0x0000000000000038
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_OFFSET 0x0000000000000038
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_OFFSET 0x0000000000000040
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_OFFSET 0x0000000000000040
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_OFFSET 0x0000000000000048
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MSB 6
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MASK 0x000000000000007f
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_OFFSET 0x0000000000000048
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_LSB 7
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MASK 0x00000000ffffff80
#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_OFFSET 0x0000000000000048
#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MSB 35
#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MASK 0x0000000f00000000
#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_OFFSET 0x0000000000000048
#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_LSB 36
#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MSB 41
#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MASK 0x000003f000000000
#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x0000000000000048
#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_LSB 42
#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MSB 47
#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc0000000000
#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_OFFSET 0x0000000000000048
#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_LSB 48
#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MASK 0xffff000000000000
#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_OFFSET 0x0000000000000050
#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MSB 23
#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MASK 0x0000000000ffffff
#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_OFFSET 0x0000000000000050
#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_LSB 24
#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MASK 0x00000000ff000000
#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000000000000050
#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000000000000058
#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MASK 0x00000000ffffffff
#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x0000000000000058
#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff00000000
#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x0000000000000060
#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_LSB 0
#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MSB 11
#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MASK 0x0000000000000fff
#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_OFFSET 0x0000000000000060
#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_LSB 12
#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MSB 27
#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MASK 0x000000000ffff000
#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_OFFSET 0x0000000000000060
#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_LSB 28
#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MSB 28
#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MASK 0x0000000010000000
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_LSB 29
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MSB 31
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MASK 0x00000000e0000000
#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_OFFSET 0x0000000000000060
#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_LSB 32
#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MSB 47
#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff00000000
#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_OFFSET 0x0000000000000060
#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_LSB 48
#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MSB 55
#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MASK 0x00ff000000000000
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_LSB 56
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MSB 59
#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MASK 0x0f00000000000000
#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_LSB 60
#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MSB 63
#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
#endif

114
hw/fig/v1/reo_unblock_cache.h
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@ -1,114 +0,0 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _REO_UNBLOCK_CACHE_H_
#define _REO_UNBLOCK_CACHE_H_
#include "uniform_reo_cmd_header.h"
#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 10
#define NUM_OF_QWORDS_REO_UNBLOCK_CACHE 5
struct reo_unblock_cache {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct uniform_reo_cmd_header cmd_header;
uint32_t unblock_type : 1,
cache_block_resource_index : 2,
reserved_1a : 29;
uint32_t reserved_2a : 32;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t tlv64_padding : 32;
#else
struct uniform_reo_cmd_header cmd_header;
uint32_t reserved_1a : 29,
cache_block_resource_index : 2,
unblock_type : 1;
uint32_t reserved_2a : 32;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t tlv64_padding : 32;
#endif
};
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MSB 31
#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_LSB 32
#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MSB 32
#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MASK 0x0000000100000000
#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 33
#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 34
#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000600000000
#define REO_UNBLOCK_CACHE_RESERVED_1A_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_RESERVED_1A_LSB 35
#define REO_UNBLOCK_CACHE_RESERVED_1A_MSB 63
#define REO_UNBLOCK_CACHE_RESERVED_1A_MASK 0xfffffff800000000
#define REO_UNBLOCK_CACHE_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_UNBLOCK_CACHE_RESERVED_2A_LSB 0
#define REO_UNBLOCK_CACHE_RESERVED_2A_MSB 31
#define REO_UNBLOCK_CACHE_RESERVED_2A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_UNBLOCK_CACHE_RESERVED_3A_LSB 32
#define REO_UNBLOCK_CACHE_RESERVED_3A_MSB 63
#define REO_UNBLOCK_CACHE_RESERVED_3A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_UNBLOCK_CACHE_RESERVED_4A_LSB 0
#define REO_UNBLOCK_CACHE_RESERVED_4A_MSB 31
#define REO_UNBLOCK_CACHE_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_UNBLOCK_CACHE_RESERVED_5A_LSB 32
#define REO_UNBLOCK_CACHE_RESERVED_5A_MSB 63
#define REO_UNBLOCK_CACHE_RESERVED_5A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_UNBLOCK_CACHE_RESERVED_6A_LSB 0
#define REO_UNBLOCK_CACHE_RESERVED_6A_MSB 31
#define REO_UNBLOCK_CACHE_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_UNBLOCK_CACHE_RESERVED_7A_LSB 32
#define REO_UNBLOCK_CACHE_RESERVED_7A_MSB 63
#define REO_UNBLOCK_CACHE_RESERVED_7A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_UNBLOCK_CACHE_RESERVED_8A_LSB 0
#define REO_UNBLOCK_CACHE_RESERVED_8A_MSB 31
#define REO_UNBLOCK_CACHE_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020
#define REO_UNBLOCK_CACHE_TLV64_PADDING_LSB 32
#define REO_UNBLOCK_CACHE_TLV64_PADDING_MSB 63
#define REO_UNBLOCK_CACHE_TLV64_PADDING_MASK 0xffffffff00000000
#endif

236
hw/fig/v1/reo_unblock_cache_status.h
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@ -1,236 +0,0 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _REO_UNBLOCK_CACHE_STATUS_H_
#define _REO_UNBLOCK_CACHE_STATUS_H_
#include "uniform_reo_status_header.h"
#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 26
#define NUM_OF_QWORDS_REO_UNBLOCK_CACHE_STATUS 13
struct reo_unblock_cache_status {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct uniform_reo_status_header status_header;
uint32_t error_detected : 1,
unblock_type : 1,
reserved_2a : 30;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t reserved_25a : 28,
looping_count : 4;
#else
struct uniform_reo_status_header status_header;
uint32_t reserved_2a : 30,
unblock_type : 1,
error_detected : 1;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t looping_count : 4,
reserved_25a : 28;
#endif
};
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008
#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MSB 0
#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001
#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_OFFSET 0x0000000000000008
#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_LSB 1
#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MSB 1
#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MASK 0x0000000000000002
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_LSB 2
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MASK 0x00000000fffffffc
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_LSB 0
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MSB 31
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_LSB 32
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MSB 59
#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_LSB 60
#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MSB 63
#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
#endif

422
hw/fig/v1/reo_update_rx_reo_queue.h
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@ -1,422 +0,0 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _REO_UPDATE_RX_REO_QUEUE_H_
#define _REO_UPDATE_RX_REO_QUEUE_H_
#include "uniform_reo_cmd_header.h"
#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 10
#define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE 5
struct reo_update_rx_reo_queue {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct uniform_reo_cmd_header cmd_header;
uint32_t rx_reo_queue_desc_addr_31_0 : 32;
uint32_t rx_reo_queue_desc_addr_39_32 : 8,
update_receive_queue_number : 1,
update_vld : 1,
update_associated_link_descriptor_counter : 1,
update_disable_duplicate_detection : 1,
update_soft_reorder_enable : 1,
update_ac : 1,
update_bar : 1,
update_rty : 1,
update_chk_2k_mode : 1,
update_oor_mode : 1,
update_ba_window_size : 1,
update_pn_check_needed : 1,
update_pn_shall_be_even : 1,
update_pn_shall_be_uneven : 1,
update_pn_handling_enable : 1,
update_pn_size : 1,
update_ignore_ampdu_flag : 1,
update_svld : 1,
update_ssn : 1,
update_seq_2k_error_detected_flag : 1,
update_pn_error_detected_flag : 1,
update_pn_valid : 1,
update_pn : 1,
clear_stat_counters : 1;
uint32_t receive_queue_number : 16,
vld : 1,
associated_link_descriptor_counter : 2,
disable_duplicate_detection : 1,
soft_reorder_enable : 1,
ac : 2,
bar : 1,
rty : 1,
chk_2k_mode : 1,
oor_mode : 1,
pn_check_needed : 1,
pn_shall_be_even : 1,
pn_shall_be_uneven : 1,
pn_handling_enable : 1,
ignore_ampdu_flag : 1;
uint32_t ba_window_size : 10,
pn_size : 2,
svld : 1,
ssn : 12,
seq_2k_error_detected_flag : 1,
pn_error_detected_flag : 1,
pn_valid : 1,
flush_from_cache : 1,
reserved_4a : 3;
uint32_t pn_31_0 : 32;
uint32_t pn_63_32 : 32;
uint32_t pn_95_64 : 32;
uint32_t pn_127_96 : 32;
uint32_t tlv64_padding : 32;
#else
struct uniform_reo_cmd_header cmd_header;
uint32_t rx_reo_queue_desc_addr_31_0 : 32;
uint32_t clear_stat_counters : 1,
update_pn : 1,
update_pn_valid : 1,
update_pn_error_detected_flag : 1,
update_seq_2k_error_detected_flag : 1,
update_ssn : 1,
update_svld : 1,
update_ignore_ampdu_flag : 1,
update_pn_size : 1,
update_pn_handling_enable : 1,
update_pn_shall_be_uneven : 1,
update_pn_shall_be_even : 1,
update_pn_check_needed : 1,
update_ba_window_size : 1,
update_oor_mode : 1,
update_chk_2k_mode : 1,
update_rty : 1,
update_bar : 1,
update_ac : 1,
update_soft_reorder_enable : 1,
update_disable_duplicate_detection : 1,
update_associated_link_descriptor_counter : 1,
update_vld : 1,
update_receive_queue_number : 1,
rx_reo_queue_desc_addr_39_32 : 8;
uint32_t ignore_ampdu_flag : 1,
pn_handling_enable : 1,
pn_shall_be_uneven : 1,
pn_shall_be_even : 1,
pn_check_needed : 1,
oor_mode : 1,
chk_2k_mode : 1,
rty : 1,
bar : 1,
ac : 2,
soft_reorder_enable : 1,
disable_duplicate_detection : 1,
associated_link_descriptor_counter : 2,
vld : 1,
receive_queue_number : 16;
uint32_t reserved_4a : 3,
flush_from_cache : 1,
pn_valid : 1,
pn_error_detected_flag : 1,
seq_2k_error_detected_flag : 1,
ssn : 12,
svld : 1,
pn_size : 2,
ba_window_size : 10;
uint32_t pn_31_0 : 32;
uint32_t pn_63_32 : 32;
uint32_t pn_95_64 : 32;
uint32_t pn_127_96 : 32;
uint32_t tlv64_padding : 32;
#endif
};
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7
#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MSB 8
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x0000000000000100
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_LSB 9
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MSB 9
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MASK 0x0000000000000200
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 10
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0000000000000400
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MSB 11
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x0000000000000800
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_LSB 12
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MSB 12
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MASK 0x0000000000001000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_LSB 13
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MSB 13
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MASK 0x0000000000002000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_LSB 14
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MSB 14
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MASK 0x0000000000004000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_LSB 15
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MSB 15
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MASK 0x0000000000008000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_LSB 16
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MSB 16
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MASK 0x0000000000010000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_LSB 17
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MSB 17
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MASK 0x0000000000020000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_LSB 18
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MSB 18
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MASK 0x0000000000040000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_LSB 19
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MSB 19
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MASK 0x0000000000080000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_LSB 20
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MSB 20
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MASK 0x0000000000100000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MSB 21
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x0000000000200000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_LSB 22
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MSB 22
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MASK 0x0000000000400000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_LSB 23
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MSB 23
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MASK 0x0000000000800000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_LSB 24
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MSB 24
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x0000000001000000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_LSB 25
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MSB 25
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MASK 0x0000000002000000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_LSB 26
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MSB 26
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MASK 0x0000000004000000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 27
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000008000000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MSB 28
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000010000000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_LSB 29
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MSB 29
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MASK 0x0000000020000000
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_LSB 30
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MSB 30
#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MASK 0x0000000040000000
#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_LSB 31
#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MASK 0x0000000080000000
#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 47
#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff00000000
#define REO_UPDATE_RX_REO_QUEUE_VLD_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_VLD_LSB 48
#define REO_UPDATE_RX_REO_QUEUE_VLD_MSB 48
#define REO_UPDATE_RX_REO_QUEUE_VLD_MASK 0x0001000000000000
#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 49
#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 50
#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0006000000000000
#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 51
#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 51
#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x0008000000000000
#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 52
#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 52
#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x0010000000000000
#define REO_UPDATE_RX_REO_QUEUE_AC_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_AC_LSB 53
#define REO_UPDATE_RX_REO_QUEUE_AC_MSB 54
#define REO_UPDATE_RX_REO_QUEUE_AC_MASK 0x0060000000000000
#define REO_UPDATE_RX_REO_QUEUE_BAR_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_BAR_LSB 55
#define REO_UPDATE_RX_REO_QUEUE_BAR_MSB 55
#define REO_UPDATE_RX_REO_QUEUE_BAR_MASK 0x0080000000000000
#define REO_UPDATE_RX_REO_QUEUE_RTY_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_RTY_LSB 56
#define REO_UPDATE_RX_REO_QUEUE_RTY_MSB 56
#define REO_UPDATE_RX_REO_QUEUE_RTY_MASK 0x0100000000000000
#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_LSB 57
#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MSB 57
#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MASK 0x0200000000000000
#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_LSB 58
#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MSB 58
#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MASK 0x0400000000000000
#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 59
#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 59
#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x0800000000000000
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 60
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 60
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x1000000000000000
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 61
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 61
#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x2000000000000000
#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 62
#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 62
#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x4000000000000000
#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 63
#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x8000000000000000
#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 9
#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x00000000000003ff
#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_LSB 10
#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MSB 11
#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MASK 0x0000000000000c00
#define REO_UPDATE_RX_REO_QUEUE_SVLD_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_SVLD_LSB 12
#define REO_UPDATE_RX_REO_QUEUE_SVLD_MSB 12
#define REO_UPDATE_RX_REO_QUEUE_SVLD_MASK 0x0000000000001000
#define REO_UPDATE_RX_REO_QUEUE_SSN_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_SSN_LSB 13
#define REO_UPDATE_RX_REO_QUEUE_SSN_MSB 24
#define REO_UPDATE_RX_REO_QUEUE_SSN_MASK 0x0000000001ffe000
#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 25
#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 25
#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000002000000
#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 26
#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 26
#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000004000000
#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_LSB 27
#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MSB 27
#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MASK 0x0000000008000000
#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_LSB 28
#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MSB 28
#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MASK 0x0000000010000000
#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_LSB 29
#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MASK 0x00000000e0000000
#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_OFFSET 0x0000000000000018
#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_OFFSET 0x0000000000000018
#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_OFFSET 0x0000000000000020
#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020
#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000
#endif

222
hw/fig/v1/reo_update_rx_reo_queue_status.h
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@ -1,222 +0,0 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
#include "uniform_reo_status_header.h"
#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 26
#define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 13
struct reo_update_rx_reo_queue_status {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct uniform_reo_status_header status_header;
uint32_t reserved_2a : 32;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t reserved_25a : 28,
looping_count : 4;
#else
struct uniform_reo_status_header status_header;
uint32_t reserved_2a : 32;
uint32_t reserved_3a : 32;
uint32_t reserved_4a : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 32;
uint32_t reserved_8a : 32;
uint32_t reserved_9a : 32;
uint32_t reserved_10a : 32;
uint32_t reserved_11a : 32;
uint32_t reserved_12a : 32;
uint32_t reserved_13a : 32;
uint32_t reserved_14a : 32;
uint32_t reserved_15a : 32;
uint32_t reserved_16a : 32;
uint32_t reserved_17a : 32;
uint32_t reserved_18a : 32;
uint32_t reserved_19a : 32;
uint32_t reserved_20a : 32;
uint32_t reserved_21a : 32;
uint32_t reserved_22a : 32;
uint32_t reserved_23a : 32;
uint32_t reserved_24a : 32;
uint32_t looping_count : 4,
reserved_25a : 28;
#endif
};
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_LSB 0
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MSB 31
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_LSB 32
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MSB 59
#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_LSB 60
#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MSB 63
#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
#endif

502
hw/fig/v1/rx_reo_queue.h
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@ -1,502 +0,0 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _RX_REO_QUEUE_H_
#define _RX_REO_QUEUE_H_
#include "uniform_descriptor_header.h"
#define NUM_OF_DWORDS_RX_REO_QUEUE 32
struct rx_reo_queue {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct uniform_descriptor_header descriptor_header;
uint32_t receive_queue_number : 16,
reserved_1b : 16;
uint32_t vld : 1,
associated_link_descriptor_counter : 2,
disable_duplicate_detection : 1,
soft_reorder_enable : 1,
ac : 2,
bar : 1,
rty : 1,
chk_2k_mode : 1,
oor_mode : 1,
ba_window_size : 10,
pn_check_needed : 1,
pn_shall_be_even : 1,
pn_shall_be_uneven : 1,
pn_handling_enable : 1,
pn_size : 2,
ignore_ampdu_flag : 1,
reserved_2b : 4;
uint32_t svld : 1,
ssn : 12,
current_index : 10,
seq_2k_error_detected_flag : 1,
pn_error_detected_flag : 1,
reserved_3a : 6,
pn_valid : 1;
uint32_t pn_31_0 : 32;
uint32_t pn_63_32 : 32;
uint32_t pn_95_64 : 32;
uint32_t pn_127_96 : 32;
uint32_t last_rx_enqueue_timestamp : 32;
uint32_t last_rx_dequeue_timestamp : 32;
uint32_t ptr_to_next_aging_queue_31_0 : 32;
uint32_t ptr_to_next_aging_queue_39_32 : 8,
reserved_11a : 24;
uint32_t ptr_to_previous_aging_queue_31_0 : 32;
uint32_t ptr_to_previous_aging_queue_39_32 : 8,
statistics_counter_index : 6,
reserved_13a : 18;
uint32_t rx_bitmap_31_0 : 32;
uint32_t rx_bitmap_63_32 : 32;
uint32_t rx_bitmap_95_64 : 32;
uint32_t rx_bitmap_127_96 : 32;
uint32_t rx_bitmap_159_128 : 32;
uint32_t rx_bitmap_191_160 : 32;
uint32_t rx_bitmap_223_192 : 32;
uint32_t rx_bitmap_255_224 : 32;
uint32_t rx_bitmap_287_256 : 32;
uint32_t current_mpdu_count : 7,
current_msdu_count : 25;
uint32_t last_sn_reg_index : 4,
timeout_count : 6,
forward_due_to_bar_count : 6,
duplicate_count : 16;
uint32_t frames_in_order_count : 24,
bar_received_count : 8;
uint32_t mpdu_frames_processed_count : 32;
uint32_t msdu_frames_processed_count : 32;
uint32_t total_processed_byte_count : 32;
uint32_t late_receive_mpdu_count : 12,
window_jump_2k : 4,
hole_count : 16;
uint32_t aging_drop_mpdu_count : 16,
aging_drop_interval : 8,
reserved_30 : 8;
uint32_t reserved_31 : 32;
#else
struct uniform_descriptor_header descriptor_header;
uint32_t reserved_1b : 16,
receive_queue_number : 16;
uint32_t reserved_2b : 4,
ignore_ampdu_flag : 1,
pn_size : 2,
pn_handling_enable : 1,
pn_shall_be_uneven : 1,
pn_shall_be_even : 1,
pn_check_needed : 1,
ba_window_size : 10,
oor_mode : 1,
chk_2k_mode : 1,
rty : 1,
bar : 1,
ac : 2,
soft_reorder_enable : 1,
disable_duplicate_detection : 1,
associated_link_descriptor_counter : 2,
vld : 1;
uint32_t pn_valid : 1,
reserved_3a : 6,
pn_error_detected_flag : 1,
seq_2k_error_detected_flag : 1,
current_index : 10,
ssn : 12,
svld : 1;
uint32_t pn_31_0 : 32;
uint32_t pn_63_32 : 32;
uint32_t pn_95_64 : 32;
uint32_t pn_127_96 : 32;
uint32_t last_rx_enqueue_timestamp : 32;
uint32_t last_rx_dequeue_timestamp : 32;
uint32_t ptr_to_next_aging_queue_31_0 : 32;
uint32_t reserved_11a : 24,
ptr_to_next_aging_queue_39_32 : 8;
uint32_t ptr_to_previous_aging_queue_31_0 : 32;
uint32_t reserved_13a : 18,
statistics_counter_index : 6,
ptr_to_previous_aging_queue_39_32 : 8;
uint32_t rx_bitmap_31_0 : 32;
uint32_t rx_bitmap_63_32 : 32;
uint32_t rx_bitmap_95_64 : 32;
uint32_t rx_bitmap_127_96 : 32;
uint32_t rx_bitmap_159_128 : 32;
uint32_t rx_bitmap_191_160 : 32;
uint32_t rx_bitmap_223_192 : 32;
uint32_t rx_bitmap_255_224 : 32;
uint32_t rx_bitmap_287_256 : 32;
uint32_t current_msdu_count : 25,
current_mpdu_count : 7;
uint32_t duplicate_count : 16,
forward_due_to_bar_count : 6,
timeout_count : 6,
last_sn_reg_index : 4;
uint32_t bar_received_count : 8,
frames_in_order_count : 24;
uint32_t mpdu_frames_processed_count : 32;
uint32_t msdu_frames_processed_count : 32;
uint32_t total_processed_byte_count : 32;
uint32_t hole_count : 16,
window_jump_2k : 4,
late_receive_mpdu_count : 12;
uint32_t reserved_30 : 8,
aging_drop_interval : 8,
aging_drop_mpdu_count : 16;
uint32_t reserved_31 : 32;
#endif
};
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_LSB 0
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MSB 3
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000
#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004
#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0
#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15
#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff
#define RX_REO_QUEUE_RESERVED_1B_OFFSET 0x00000004
#define RX_REO_QUEUE_RESERVED_1B_LSB 16
#define RX_REO_QUEUE_RESERVED_1B_MSB 31
#define RX_REO_QUEUE_RESERVED_1B_MASK 0xffff0000
#define RX_REO_QUEUE_VLD_OFFSET 0x00000008
#define RX_REO_QUEUE_VLD_LSB 0
#define RX_REO_QUEUE_VLD_MSB 0
#define RX_REO_QUEUE_VLD_MASK 0x00000001
#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008
#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1
#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 2
#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006
#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008
#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 3
#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 3
#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008
#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x00000008
#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 4
#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 4
#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00000010
#define RX_REO_QUEUE_AC_OFFSET 0x00000008
#define RX_REO_QUEUE_AC_LSB 5
#define RX_REO_QUEUE_AC_MSB 6
#define RX_REO_QUEUE_AC_MASK 0x00000060
#define RX_REO_QUEUE_BAR_OFFSET 0x00000008
#define RX_REO_QUEUE_BAR_LSB 7
#define RX_REO_QUEUE_BAR_MSB 7
#define RX_REO_QUEUE_BAR_MASK 0x00000080
#define RX_REO_QUEUE_RTY_OFFSET 0x00000008
#define RX_REO_QUEUE_RTY_LSB 8
#define RX_REO_QUEUE_RTY_MSB 8
#define RX_REO_QUEUE_RTY_MASK 0x00000100
#define RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x00000008
#define RX_REO_QUEUE_CHK_2K_MODE_LSB 9
#define RX_REO_QUEUE_CHK_2K_MODE_MSB 9
#define RX_REO_QUEUE_CHK_2K_MODE_MASK 0x00000200
#define RX_REO_QUEUE_OOR_MODE_OFFSET 0x00000008
#define RX_REO_QUEUE_OOR_MODE_LSB 10
#define RX_REO_QUEUE_OOR_MODE_MSB 10
#define RX_REO_QUEUE_OOR_MODE_MASK 0x00000400
#define RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000008
#define RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 11
#define RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 20
#define RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x001ff800
#define RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x00000008
#define RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 21
#define RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 21
#define RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x00200000
#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x00000008
#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 22
#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 22
#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x00400000
#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008
#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 23
#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 23
#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x00800000
#define RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x00000008
#define RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 24
#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 24
#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x01000000
#define RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000008
#define RX_REO_QUEUE_PN_SIZE_LSB 25
#define RX_REO_QUEUE_PN_SIZE_MSB 26
#define RX_REO_QUEUE_PN_SIZE_MASK 0x06000000
#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008
#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 27
#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 27
#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x08000000
#define RX_REO_QUEUE_RESERVED_2B_OFFSET 0x00000008
#define RX_REO_QUEUE_RESERVED_2B_LSB 28
#define RX_REO_QUEUE_RESERVED_2B_MSB 31
#define RX_REO_QUEUE_RESERVED_2B_MASK 0xf0000000
#define RX_REO_QUEUE_SVLD_OFFSET 0x0000000c
#define RX_REO_QUEUE_SVLD_LSB 0
#define RX_REO_QUEUE_SVLD_MSB 0
#define RX_REO_QUEUE_SVLD_MASK 0x00000001
#define RX_REO_QUEUE_SSN_OFFSET 0x0000000c
#define RX_REO_QUEUE_SSN_LSB 1
#define RX_REO_QUEUE_SSN_MSB 12
#define RX_REO_QUEUE_SSN_MASK 0x00001ffe
#define RX_REO_QUEUE_CURRENT_INDEX_OFFSET 0x0000000c
#define RX_REO_QUEUE_CURRENT_INDEX_LSB 13
#define RX_REO_QUEUE_CURRENT_INDEX_MSB 22
#define RX_REO_QUEUE_CURRENT_INDEX_MASK 0x007fe000
#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c
#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23
#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 23
#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000
#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c
#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 24
#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 24
#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x01000000
#define RX_REO_QUEUE_RESERVED_3A_OFFSET 0x0000000c
#define RX_REO_QUEUE_RESERVED_3A_LSB 25
#define RX_REO_QUEUE_RESERVED_3A_MSB 30
#define RX_REO_QUEUE_RESERVED_3A_MASK 0x7e000000
#define RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000c
#define RX_REO_QUEUE_PN_VALID_LSB 31
#define RX_REO_QUEUE_PN_VALID_MSB 31
#define RX_REO_QUEUE_PN_VALID_MASK 0x80000000
#define RX_REO_QUEUE_PN_31_0_OFFSET 0x00000010
#define RX_REO_QUEUE_PN_31_0_LSB 0
#define RX_REO_QUEUE_PN_31_0_MSB 31
#define RX_REO_QUEUE_PN_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_PN_63_32_OFFSET 0x00000014
#define RX_REO_QUEUE_PN_63_32_LSB 0
#define RX_REO_QUEUE_PN_63_32_MSB 31
#define RX_REO_QUEUE_PN_63_32_MASK 0xffffffff
#define RX_REO_QUEUE_PN_95_64_OFFSET 0x00000018
#define RX_REO_QUEUE_PN_95_64_LSB 0
#define RX_REO_QUEUE_PN_95_64_MSB 31
#define RX_REO_QUEUE_PN_95_64_MASK 0xffffffff
#define RX_REO_QUEUE_PN_127_96_OFFSET 0x0000001c
#define RX_REO_QUEUE_PN_127_96_LSB 0
#define RX_REO_QUEUE_PN_127_96_MSB 31
#define RX_REO_QUEUE_PN_127_96_MASK 0xffffffff
#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020
#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0
#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MSB 31
#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff
#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024
#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0
#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31
#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff
#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028
#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0
#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MSB 31
#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c
#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0
#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MSB 7
#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_RESERVED_11A_OFFSET 0x0000002c
#define RX_REO_QUEUE_RESERVED_11A_LSB 8
#define RX_REO_QUEUE_RESERVED_11A_MSB 31
#define RX_REO_QUEUE_RESERVED_11A_MASK 0xffffff00
#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030
#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0
#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MSB 31
#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034
#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0
#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MSB 7
#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_OFFSET 0x00000034
#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_LSB 8
#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MSB 13
#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MASK 0x00003f00
#define RX_REO_QUEUE_RESERVED_13A_OFFSET 0x00000034
#define RX_REO_QUEUE_RESERVED_13A_LSB 14
#define RX_REO_QUEUE_RESERVED_13A_MSB 31
#define RX_REO_QUEUE_RESERVED_13A_MASK 0xffffc000
#define RX_REO_QUEUE_RX_BITMAP_31_0_OFFSET 0x00000038
#define RX_REO_QUEUE_RX_BITMAP_31_0_LSB 0
#define RX_REO_QUEUE_RX_BITMAP_31_0_MSB 31
#define RX_REO_QUEUE_RX_BITMAP_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_RX_BITMAP_63_32_OFFSET 0x0000003c
#define RX_REO_QUEUE_RX_BITMAP_63_32_LSB 0
#define RX_REO_QUEUE_RX_BITMAP_63_32_MSB 31
#define RX_REO_QUEUE_RX_BITMAP_63_32_MASK 0xffffffff
#define RX_REO_QUEUE_RX_BITMAP_95_64_OFFSET 0x00000040
#define RX_REO_QUEUE_RX_BITMAP_95_64_LSB 0
#define RX_REO_QUEUE_RX_BITMAP_95_64_MSB 31
#define RX_REO_QUEUE_RX_BITMAP_95_64_MASK 0xffffffff
#define RX_REO_QUEUE_RX_BITMAP_127_96_OFFSET 0x00000044
#define RX_REO_QUEUE_RX_BITMAP_127_96_LSB 0
#define RX_REO_QUEUE_RX_BITMAP_127_96_MSB 31
#define RX_REO_QUEUE_RX_BITMAP_127_96_MASK 0xffffffff
#define RX_REO_QUEUE_RX_BITMAP_159_128_OFFSET 0x00000048
#define RX_REO_QUEUE_RX_BITMAP_159_128_LSB 0
#define RX_REO_QUEUE_RX_BITMAP_159_128_MSB 31
#define RX_REO_QUEUE_RX_BITMAP_159_128_MASK 0xffffffff
#define RX_REO_QUEUE_RX_BITMAP_191_160_OFFSET 0x0000004c
#define RX_REO_QUEUE_RX_BITMAP_191_160_LSB 0
#define RX_REO_QUEUE_RX_BITMAP_191_160_MSB 31
#define RX_REO_QUEUE_RX_BITMAP_191_160_MASK 0xffffffff
#define RX_REO_QUEUE_RX_BITMAP_223_192_OFFSET 0x00000050
#define RX_REO_QUEUE_RX_BITMAP_223_192_LSB 0
#define RX_REO_QUEUE_RX_BITMAP_223_192_MSB 31
#define RX_REO_QUEUE_RX_BITMAP_223_192_MASK 0xffffffff
#define RX_REO_QUEUE_RX_BITMAP_255_224_OFFSET 0x00000054
#define RX_REO_QUEUE_RX_BITMAP_255_224_LSB 0
#define RX_REO_QUEUE_RX_BITMAP_255_224_MSB 31
#define RX_REO_QUEUE_RX_BITMAP_255_224_MASK 0xffffffff
#define RX_REO_QUEUE_RX_BITMAP_287_256_OFFSET 0x00000058
#define RX_REO_QUEUE_RX_BITMAP_287_256_LSB 0
#define RX_REO_QUEUE_RX_BITMAP_287_256_MSB 31
#define RX_REO_QUEUE_RX_BITMAP_287_256_MASK 0xffffffff
#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_OFFSET 0x0000005c
#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_LSB 0
#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MSB 6
#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MASK 0x0000007f
#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_OFFSET 0x0000005c
#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_LSB 7
#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MSB 31
#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MASK 0xffffff80
#define RX_REO_QUEUE_LAST_SN_REG_INDEX_OFFSET 0x00000060
#define RX_REO_QUEUE_LAST_SN_REG_INDEX_LSB 0
#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MSB 3
#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MASK 0x0000000f
#define RX_REO_QUEUE_TIMEOUT_COUNT_OFFSET 0x00000060
#define RX_REO_QUEUE_TIMEOUT_COUNT_LSB 4
#define RX_REO_QUEUE_TIMEOUT_COUNT_MSB 9
#define RX_REO_QUEUE_TIMEOUT_COUNT_MASK 0x000003f0
#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000060
#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_LSB 10
#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MSB 15
#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00
#define RX_REO_QUEUE_DUPLICATE_COUNT_OFFSET 0x00000060
#define RX_REO_QUEUE_DUPLICATE_COUNT_LSB 16
#define RX_REO_QUEUE_DUPLICATE_COUNT_MSB 31
#define RX_REO_QUEUE_DUPLICATE_COUNT_MASK 0xffff0000
#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000064
#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_LSB 0
#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MSB 23
#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff
#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_OFFSET 0x00000064
#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_LSB 24
#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MSB 31
#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MASK 0xff000000
#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068
#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_LSB 0
#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MSB 31
#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000006c
#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_LSB 0
#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MSB 31
#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000070
#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_LSB 0
#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MSB 31
#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff
#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000074
#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_LSB 0
#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MSB 11
#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff
#define RX_REO_QUEUE_WINDOW_JUMP_2K_OFFSET 0x00000074
#define RX_REO_QUEUE_WINDOW_JUMP_2K_LSB 12
#define RX_REO_QUEUE_WINDOW_JUMP_2K_MSB 15
#define RX_REO_QUEUE_WINDOW_JUMP_2K_MASK 0x0000f000
#define RX_REO_QUEUE_HOLE_COUNT_OFFSET 0x00000074
#define RX_REO_QUEUE_HOLE_COUNT_LSB 16
#define RX_REO_QUEUE_HOLE_COUNT_MSB 31
#define RX_REO_QUEUE_HOLE_COUNT_MASK 0xffff0000
#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_OFFSET 0x00000078
#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_LSB 0
#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MSB 15
#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff
#define RX_REO_QUEUE_AGING_DROP_INTERVAL_OFFSET 0x00000078
#define RX_REO_QUEUE_AGING_DROP_INTERVAL_LSB 16
#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MSB 23
#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MASK 0x00ff0000
#define RX_REO_QUEUE_RESERVED_30_OFFSET 0x00000078
#define RX_REO_QUEUE_RESERVED_30_LSB 24
#define RX_REO_QUEUE_RESERVED_30_MSB 31
#define RX_REO_QUEUE_RESERVED_30_MASK 0xff000000
#define RX_REO_QUEUE_RESERVED_31_OFFSET 0x0000007c
#define RX_REO_QUEUE_RESERVED_31_LSB 0
#define RX_REO_QUEUE_RESERVED_31_MSB 31
#define RX_REO_QUEUE_RESERVED_31_MASK 0xffffffff
#endif

257
hw/fig/v1/rx_reo_queue_1k.h
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@ -1,257 +0,0 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _RX_REO_QUEUE_1K_H_
#define _RX_REO_QUEUE_1K_H_
#include "uniform_descriptor_header.h"
#define NUM_OF_DWORDS_RX_REO_QUEUE_1K 32
struct rx_reo_queue_1k {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct uniform_descriptor_header descriptor_header;
uint32_t rx_bitmap_319_288 : 32;
uint32_t rx_bitmap_351_320 : 32;
uint32_t rx_bitmap_383_352 : 32;
uint32_t rx_bitmap_415_384 : 32;
uint32_t rx_bitmap_447_416 : 32;
uint32_t rx_bitmap_479_448 : 32;
uint32_t rx_bitmap_511_480 : 32;
uint32_t rx_bitmap_543_512 : 32;
uint32_t rx_bitmap_575_544 : 32;
uint32_t rx_bitmap_607_576 : 32;
uint32_t rx_bitmap_639_608 : 32;
uint32_t rx_bitmap_671_640 : 32;
uint32_t rx_bitmap_703_672 : 32;
uint32_t rx_bitmap_735_704 : 32;
uint32_t rx_bitmap_767_736 : 32;
uint32_t rx_bitmap_799_768 : 32;
uint32_t rx_bitmap_831_800 : 32;
uint32_t rx_bitmap_863_832 : 32;
uint32_t rx_bitmap_895_864 : 32;
uint32_t rx_bitmap_927_896 : 32;
uint32_t rx_bitmap_959_928 : 32;
uint32_t rx_bitmap_991_960 : 32;
uint32_t rx_bitmap_1023_992 : 32;
uint32_t reserved_24 : 32;
uint32_t reserved_25 : 32;
uint32_t reserved_26 : 32;
uint32_t reserved_27 : 32;
uint32_t reserved_28 : 32;
uint32_t reserved_29 : 32;
uint32_t reserved_30 : 32;
uint32_t reserved_31 : 32;
#else
struct uniform_descriptor_header descriptor_header;
uint32_t rx_bitmap_319_288 : 32;
uint32_t rx_bitmap_351_320 : 32;
uint32_t rx_bitmap_383_352 : 32;
uint32_t rx_bitmap_415_384 : 32;
uint32_t rx_bitmap_447_416 : 32;
uint32_t rx_bitmap_479_448 : 32;
uint32_t rx_bitmap_511_480 : 32;
uint32_t rx_bitmap_543_512 : 32;
uint32_t rx_bitmap_575_544 : 32;
uint32_t rx_bitmap_607_576 : 32;
uint32_t rx_bitmap_639_608 : 32;
uint32_t rx_bitmap_671_640 : 32;
uint32_t rx_bitmap_703_672 : 32;
uint32_t rx_bitmap_735_704 : 32;
uint32_t rx_bitmap_767_736 : 32;
uint32_t rx_bitmap_799_768 : 32;
uint32_t rx_bitmap_831_800 : 32;
uint32_t rx_bitmap_863_832 : 32;
uint32_t rx_bitmap_895_864 : 32;
uint32_t rx_bitmap_927_896 : 32;
uint32_t rx_bitmap_959_928 : 32;
uint32_t rx_bitmap_991_960 : 32;
uint32_t rx_bitmap_1023_992 : 32;
uint32_t reserved_24 : 32;
uint32_t reserved_25 : 32;
uint32_t reserved_26 : 32;
uint32_t reserved_27 : 32;
uint32_t reserved_28 : 32;
uint32_t reserved_29 : 32;
uint32_t reserved_30 : 32;
uint32_t reserved_31 : 32;
#endif
};
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_LSB 0
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MSB 3
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000
#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_OFFSET 0x00000004
#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_OFFSET 0x00000008
#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_OFFSET 0x0000000c
#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_OFFSET 0x00000010
#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_OFFSET 0x00000014
#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_OFFSET 0x00000018
#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_OFFSET 0x0000001c
#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_OFFSET 0x00000020
#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_OFFSET 0x00000024
#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_OFFSET 0x00000028
#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_OFFSET 0x0000002c
#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_OFFSET 0x00000030
#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_OFFSET 0x00000034
#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_OFFSET 0x00000038
#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_OFFSET 0x0000003c
#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_OFFSET 0x00000040
#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_OFFSET 0x00000044
#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_OFFSET 0x00000048
#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_OFFSET 0x0000004c
#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_OFFSET 0x00000050
#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_OFFSET 0x00000054
#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_OFFSET 0x00000058
#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_OFFSET 0x0000005c
#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_LSB 0
#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MSB 31
#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RESERVED_24_OFFSET 0x00000060
#define RX_REO_QUEUE_1K_RESERVED_24_LSB 0
#define RX_REO_QUEUE_1K_RESERVED_24_MSB 31
#define RX_REO_QUEUE_1K_RESERVED_24_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RESERVED_25_OFFSET 0x00000064
#define RX_REO_QUEUE_1K_RESERVED_25_LSB 0
#define RX_REO_QUEUE_1K_RESERVED_25_MSB 31
#define RX_REO_QUEUE_1K_RESERVED_25_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RESERVED_26_OFFSET 0x00000068
#define RX_REO_QUEUE_1K_RESERVED_26_LSB 0
#define RX_REO_QUEUE_1K_RESERVED_26_MSB 31
#define RX_REO_QUEUE_1K_RESERVED_26_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RESERVED_27_OFFSET 0x0000006c
#define RX_REO_QUEUE_1K_RESERVED_27_LSB 0
#define RX_REO_QUEUE_1K_RESERVED_27_MSB 31
#define RX_REO_QUEUE_1K_RESERVED_27_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RESERVED_28_OFFSET 0x00000070
#define RX_REO_QUEUE_1K_RESERVED_28_LSB 0
#define RX_REO_QUEUE_1K_RESERVED_28_MSB 31
#define RX_REO_QUEUE_1K_RESERVED_28_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RESERVED_29_OFFSET 0x00000074
#define RX_REO_QUEUE_1K_RESERVED_29_LSB 0
#define RX_REO_QUEUE_1K_RESERVED_29_MSB 31
#define RX_REO_QUEUE_1K_RESERVED_29_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RESERVED_30_OFFSET 0x00000078
#define RX_REO_QUEUE_1K_RESERVED_30_LSB 0
#define RX_REO_QUEUE_1K_RESERVED_30_MSB 31
#define RX_REO_QUEUE_1K_RESERVED_30_MASK 0xffffffff
#define RX_REO_QUEUE_1K_RESERVED_31_OFFSET 0x0000007c
#define RX_REO_QUEUE_1K_RESERVED_31_LSB 0
#define RX_REO_QUEUE_1K_RESERVED_31_MSB 31
#define RX_REO_QUEUE_1K_RESERVED_31_MASK 0xffffffff
#endif

378
hw/fig/v1/rx_reo_queue_ext.h
View file

@ -1,378 +0,0 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _RX_REO_QUEUE_EXT_H_
#define _RX_REO_QUEUE_EXT_H_
#include "rx_mpdu_link_ptr.h"
#include "uniform_descriptor_header.h"
#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32
struct rx_reo_queue_ext {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct uniform_descriptor_header descriptor_header;
uint32_t reserved_1a : 32;
struct rx_mpdu_link_ptr mpdu_link_pointer_0;
struct rx_mpdu_link_ptr mpdu_link_pointer_1;
struct rx_mpdu_link_ptr mpdu_link_pointer_2;
struct rx_mpdu_link_ptr mpdu_link_pointer_3;
struct rx_mpdu_link_ptr mpdu_link_pointer_4;
struct rx_mpdu_link_ptr mpdu_link_pointer_5;
struct rx_mpdu_link_ptr mpdu_link_pointer_6;
struct rx_mpdu_link_ptr mpdu_link_pointer_7;
struct rx_mpdu_link_ptr mpdu_link_pointer_8;
struct rx_mpdu_link_ptr mpdu_link_pointer_9;
struct rx_mpdu_link_ptr mpdu_link_pointer_10;
struct rx_mpdu_link_ptr mpdu_link_pointer_11;
struct rx_mpdu_link_ptr mpdu_link_pointer_12;
struct rx_mpdu_link_ptr mpdu_link_pointer_13;
struct rx_mpdu_link_ptr mpdu_link_pointer_14;
#else
struct uniform_descriptor_header descriptor_header;
uint32_t reserved_1a : 32;
struct rx_mpdu_link_ptr mpdu_link_pointer_0;
struct rx_mpdu_link_ptr mpdu_link_pointer_1;
struct rx_mpdu_link_ptr mpdu_link_pointer_2;
struct rx_mpdu_link_ptr mpdu_link_pointer_3;
struct rx_mpdu_link_ptr mpdu_link_pointer_4;
struct rx_mpdu_link_ptr mpdu_link_pointer_5;
struct rx_mpdu_link_ptr mpdu_link_pointer_6;
struct rx_mpdu_link_ptr mpdu_link_pointer_7;
struct rx_mpdu_link_ptr mpdu_link_pointer_8;
struct rx_mpdu_link_ptr mpdu_link_pointer_9;
struct rx_mpdu_link_ptr mpdu_link_pointer_10;
struct rx_mpdu_link_ptr mpdu_link_pointer_11;
struct rx_mpdu_link_ptr mpdu_link_pointer_12;
struct rx_mpdu_link_ptr mpdu_link_pointer_13;
struct rx_mpdu_link_ptr mpdu_link_pointer_14;
#endif
};
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_LSB 0
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MSB 3
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000
#define RX_REO_QUEUE_EXT_RESERVED_1A_OFFSET 0x00000004
#define RX_REO_QUEUE_EXT_RESERVED_1A_LSB 0
#define RX_REO_QUEUE_EXT_RESERVED_1A_MSB 31
#define RX_REO_QUEUE_EXT_RESERVED_1A_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#endif

278
hw/fig/v1/tcl_data_cmd.h
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _TCL_DATA_CMD_H_
#define _TCL_DATA_CMD_H_
#include "buffer_addr_info.h"
#define NUM_OF_DWORDS_TCL_DATA_CMD 8
struct tcl_data_cmd {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
struct buffer_addr_info buf_addr_info;
uint32_t tcl_cmd_type : 1,
buf_or_ext_desc_type : 1,
bank_id : 6,
tx_notify_frame : 3,
header_length_read_sel : 1,
buffer_timestamp : 19,
buffer_timestamp_valid : 1;
uint32_t reserved_3a : 16,
tcl_cmd_number : 16;
uint32_t data_length : 16,
ipv4_checksum_en : 1,
udp_over_ipv4_checksum_en : 1,
udp_over_ipv6_checksum_en : 1,
tcp_over_ipv4_checksum_en : 1,
tcp_over_ipv6_checksum_en : 1,
to_fw : 1,
reserved_4a : 1,
packet_offset : 9;
uint32_t hlos_tid_overwrite : 1,
flow_override_enable : 1,
who_classify_info_sel : 2,
hlos_tid : 4,
flow_override : 1,
pmac_id : 2,
msdu_color : 2,
reserved_5a : 11,
vdev_id : 8;
uint32_t search_index : 20,
cache_set_num : 4,
index_lookup_override : 1,
reserved_6a : 7;
uint32_t reserved_7a : 20,
ring_id : 8,
looping_count : 4;
#else
struct buffer_addr_info buf_addr_info;
uint32_t buffer_timestamp_valid : 1,
buffer_timestamp : 19,
header_length_read_sel : 1,
tx_notify_frame : 3,
bank_id : 6,
buf_or_ext_desc_type : 1,
tcl_cmd_type : 1;
uint32_t tcl_cmd_number : 16,
reserved_3a : 16;
uint32_t packet_offset : 9,
reserved_4a : 1,
to_fw : 1,
tcp_over_ipv6_checksum_en : 1,
tcp_over_ipv4_checksum_en : 1,
udp_over_ipv6_checksum_en : 1,
udp_over_ipv4_checksum_en : 1,
ipv4_checksum_en : 1,
data_length : 16;
uint32_t vdev_id : 8,
reserved_5a : 11,
msdu_color : 2,
pmac_id : 2,
flow_override : 1,
hlos_tid : 4,
who_classify_info_sel : 2,
flow_override_enable : 1,
hlos_tid_overwrite : 1;
uint32_t reserved_6a : 7,
index_lookup_override : 1,
cache_set_num : 4,
search_index : 20;
uint32_t looping_count : 4,
ring_id : 8,
reserved_7a : 20;
#endif
};
#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
#define TCL_DATA_CMD_TCL_CMD_TYPE_OFFSET 0x00000008
#define TCL_DATA_CMD_TCL_CMD_TYPE_LSB 0
#define TCL_DATA_CMD_TCL_CMD_TYPE_MSB 0
#define TCL_DATA_CMD_TCL_CMD_TYPE_MASK 0x00000001
#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008
#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 1
#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MSB 1
#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 0x00000002
#define TCL_DATA_CMD_BANK_ID_OFFSET 0x00000008
#define TCL_DATA_CMD_BANK_ID_LSB 2
#define TCL_DATA_CMD_BANK_ID_MSB 7
#define TCL_DATA_CMD_BANK_ID_MASK 0x000000fc
#define TCL_DATA_CMD_TX_NOTIFY_FRAME_OFFSET 0x00000008
#define TCL_DATA_CMD_TX_NOTIFY_FRAME_LSB 8
#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MSB 10
#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MASK 0x00000700
#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_OFFSET 0x00000008
#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_LSB 11
#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MSB 11
#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MASK 0x00000800
#define TCL_DATA_CMD_BUFFER_TIMESTAMP_OFFSET 0x00000008
#define TCL_DATA_CMD_BUFFER_TIMESTAMP_LSB 12
#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MSB 30
#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MASK 0x7ffff000
#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000008
#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_LSB 31
#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MSB 31
#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MASK 0x80000000
#define TCL_DATA_CMD_RESERVED_3A_OFFSET 0x0000000c
#define TCL_DATA_CMD_RESERVED_3A_LSB 0
#define TCL_DATA_CMD_RESERVED_3A_MSB 15
#define TCL_DATA_CMD_RESERVED_3A_MASK 0x0000ffff
#define TCL_DATA_CMD_TCL_CMD_NUMBER_OFFSET 0x0000000c
#define TCL_DATA_CMD_TCL_CMD_NUMBER_LSB 16
#define TCL_DATA_CMD_TCL_CMD_NUMBER_MSB 31
#define TCL_DATA_CMD_TCL_CMD_NUMBER_MASK 0xffff0000
#define TCL_DATA_CMD_DATA_LENGTH_OFFSET 0x00000010
#define TCL_DATA_CMD_DATA_LENGTH_LSB 0
#define TCL_DATA_CMD_DATA_LENGTH_MSB 15
#define TCL_DATA_CMD_DATA_LENGTH_MASK 0x0000ffff
#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_OFFSET 0x00000010
#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB 16
#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MSB 16
#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MASK 0x00010000
#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010
#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17
#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MSB 17
#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000
#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010
#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18
#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MSB 18
#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000
#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010
#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19
#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MSB 19
#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000
#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010
#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20
#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MSB 20
#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000
#define TCL_DATA_CMD_TO_FW_OFFSET 0x00000010
#define TCL_DATA_CMD_TO_FW_LSB 21
#define TCL_DATA_CMD_TO_FW_MSB 21
#define TCL_DATA_CMD_TO_FW_MASK 0x00200000
#define TCL_DATA_CMD_RESERVED_4A_OFFSET 0x00000010
#define TCL_DATA_CMD_RESERVED_4A_LSB 22
#define TCL_DATA_CMD_RESERVED_4A_MSB 22
#define TCL_DATA_CMD_RESERVED_4A_MASK 0x00400000
#define TCL_DATA_CMD_PACKET_OFFSET_OFFSET 0x00000010
#define TCL_DATA_CMD_PACKET_OFFSET_LSB 23
#define TCL_DATA_CMD_PACKET_OFFSET_MSB 31
#define TCL_DATA_CMD_PACKET_OFFSET_MASK 0xff800000
#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_OFFSET 0x00000014
#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_LSB 0
#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MSB 0
#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MASK 0x00000001
#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_OFFSET 0x00000014
#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_LSB 1
#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MSB 1
#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MASK 0x00000002
#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_OFFSET 0x00000014
#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_LSB 2
#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MSB 3
#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MASK 0x0000000c
#define TCL_DATA_CMD_HLOS_TID_OFFSET 0x00000014
#define TCL_DATA_CMD_HLOS_TID_LSB 4
#define TCL_DATA_CMD_HLOS_TID_MSB 7
#define TCL_DATA_CMD_HLOS_TID_MASK 0x000000f0
#define TCL_DATA_CMD_FLOW_OVERRIDE_OFFSET 0x00000014
#define TCL_DATA_CMD_FLOW_OVERRIDE_LSB 8
#define TCL_DATA_CMD_FLOW_OVERRIDE_MSB 8
#define TCL_DATA_CMD_FLOW_OVERRIDE_MASK 0x00000100
#define TCL_DATA_CMD_PMAC_ID_OFFSET 0x00000014
#define TCL_DATA_CMD_PMAC_ID_LSB 9
#define TCL_DATA_CMD_PMAC_ID_MSB 10
#define TCL_DATA_CMD_PMAC_ID_MASK 0x00000600
#define TCL_DATA_CMD_MSDU_COLOR_OFFSET 0x00000014
#define TCL_DATA_CMD_MSDU_COLOR_LSB 11
#define TCL_DATA_CMD_MSDU_COLOR_MSB 12
#define TCL_DATA_CMD_MSDU_COLOR_MASK 0x00001800
#define TCL_DATA_CMD_RESERVED_5A_OFFSET 0x00000014
#define TCL_DATA_CMD_RESERVED_5A_LSB 13
#define TCL_DATA_CMD_RESERVED_5A_MSB 23
#define TCL_DATA_CMD_RESERVED_5A_MASK 0x00ffe000
#define TCL_DATA_CMD_VDEV_ID_OFFSET 0x00000014
#define TCL_DATA_CMD_VDEV_ID_LSB 24
#define TCL_DATA_CMD_VDEV_ID_MSB 31
#define TCL_DATA_CMD_VDEV_ID_MASK 0xff000000
#define TCL_DATA_CMD_SEARCH_INDEX_OFFSET 0x00000018
#define TCL_DATA_CMD_SEARCH_INDEX_LSB 0
#define TCL_DATA_CMD_SEARCH_INDEX_MSB 19
#define TCL_DATA_CMD_SEARCH_INDEX_MASK 0x000fffff
#define TCL_DATA_CMD_CACHE_SET_NUM_OFFSET 0x00000018
#define TCL_DATA_CMD_CACHE_SET_NUM_LSB 20
#define TCL_DATA_CMD_CACHE_SET_NUM_MSB 23
#define TCL_DATA_CMD_CACHE_SET_NUM_MASK 0x00f00000
#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_OFFSET 0x00000018
#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_LSB 24
#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MSB 24
#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MASK 0x01000000
#define TCL_DATA_CMD_RESERVED_6A_OFFSET 0x00000018
#define TCL_DATA_CMD_RESERVED_6A_LSB 25
#define TCL_DATA_CMD_RESERVED_6A_MSB 31
#define TCL_DATA_CMD_RESERVED_6A_MASK 0xfe000000
#define TCL_DATA_CMD_RESERVED_7A_OFFSET 0x0000001c
#define TCL_DATA_CMD_RESERVED_7A_LSB 0
#define TCL_DATA_CMD_RESERVED_7A_MSB 19
#define TCL_DATA_CMD_RESERVED_7A_MASK 0x000fffff
#define TCL_DATA_CMD_RING_ID_OFFSET 0x0000001c
#define TCL_DATA_CMD_RING_ID_LSB 20
#define TCL_DATA_CMD_RING_ID_MSB 27
#define TCL_DATA_CMD_RING_ID_MASK 0x0ff00000
#define TCL_DATA_CMD_LOOPING_COUNT_OFFSET 0x0000001c
#define TCL_DATA_CMD_LOOPING_COUNT_LSB 28
#define TCL_DATA_CMD_LOOPING_COUNT_MSB 31
#define TCL_DATA_CMD_LOOPING_COUNT_MASK 0xf0000000
#endif

143
hw/fig/v1/tcl_gse_cmd.h
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _TCL_GSE_CMD_H_
#define _TCL_GSE_CMD_H_
#define NUM_OF_DWORDS_TCL_GSE_CMD 8
struct tcl_gse_cmd {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t control_buffer_addr_31_0 : 32;
uint32_t control_buffer_addr_39_32 : 8,
gse_ctrl : 4,
gse_sel : 1,
status_destination_ring_id : 1,
swap : 1,
index_search_en : 1,
cache_set_num : 4,
reserved_1a : 12;
uint32_t tcl_cmd_type : 1,
reserved_2a : 31;
uint32_t cmd_meta_data_31_0 : 32;
uint32_t cmd_meta_data_63_32 : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t reserved_7a : 20,
ring_id : 8,
looping_count : 4;
#else
uint32_t control_buffer_addr_31_0 : 32;
uint32_t reserved_1a : 12,
cache_set_num : 4,
index_search_en : 1,
swap : 1,
status_destination_ring_id : 1,
gse_sel : 1,
gse_ctrl : 4,
control_buffer_addr_39_32 : 8;
uint32_t reserved_2a : 31,
tcl_cmd_type : 1;
uint32_t cmd_meta_data_31_0 : 32;
uint32_t cmd_meta_data_63_32 : 32;
uint32_t reserved_5a : 32;
uint32_t reserved_6a : 32;
uint32_t looping_count : 4,
ring_id : 8,
reserved_7a : 20;
#endif
};
#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000
#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB 0
#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB 31
#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff
#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004
#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB 0
#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB 7
#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff
#define TCL_GSE_CMD_GSE_CTRL_OFFSET 0x00000004
#define TCL_GSE_CMD_GSE_CTRL_LSB 8
#define TCL_GSE_CMD_GSE_CTRL_MSB 11
#define TCL_GSE_CMD_GSE_CTRL_MASK 0x00000f00
#define TCL_GSE_CMD_GSE_SEL_OFFSET 0x00000004
#define TCL_GSE_CMD_GSE_SEL_LSB 12
#define TCL_GSE_CMD_GSE_SEL_MSB 12
#define TCL_GSE_CMD_GSE_SEL_MASK 0x00001000
#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004
#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB 13
#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB 13
#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK 0x00002000
#define TCL_GSE_CMD_SWAP_OFFSET 0x00000004
#define TCL_GSE_CMD_SWAP_LSB 14
#define TCL_GSE_CMD_SWAP_MSB 14
#define TCL_GSE_CMD_SWAP_MASK 0x00004000
#define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET 0x00000004
#define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB 15
#define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB 15
#define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK 0x00008000
#define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET 0x00000004
#define TCL_GSE_CMD_CACHE_SET_NUM_LSB 16
#define TCL_GSE_CMD_CACHE_SET_NUM_MSB 19
#define TCL_GSE_CMD_CACHE_SET_NUM_MASK 0x000f0000
#define TCL_GSE_CMD_RESERVED_1A_OFFSET 0x00000004
#define TCL_GSE_CMD_RESERVED_1A_LSB 20
#define TCL_GSE_CMD_RESERVED_1A_MSB 31
#define TCL_GSE_CMD_RESERVED_1A_MASK 0xfff00000
#define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET 0x00000008
#define TCL_GSE_CMD_TCL_CMD_TYPE_LSB 0
#define TCL_GSE_CMD_TCL_CMD_TYPE_MSB 0
#define TCL_GSE_CMD_TCL_CMD_TYPE_MASK 0x00000001
#define TCL_GSE_CMD_RESERVED_2A_OFFSET 0x00000008
#define TCL_GSE_CMD_RESERVED_2A_LSB 1
#define TCL_GSE_CMD_RESERVED_2A_MSB 31
#define TCL_GSE_CMD_RESERVED_2A_MASK 0xfffffffe
#define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET 0x0000000c
#define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB 0
#define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB 31
#define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK 0xffffffff
#define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET 0x00000010
#define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB 0
#define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB 31
#define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK 0xffffffff
#define TCL_GSE_CMD_RESERVED_5A_OFFSET 0x00000014
#define TCL_GSE_CMD_RESERVED_5A_LSB 0
#define TCL_GSE_CMD_RESERVED_5A_MSB 31
#define TCL_GSE_CMD_RESERVED_5A_MASK 0xffffffff
#define TCL_GSE_CMD_RESERVED_6A_OFFSET 0x00000018
#define TCL_GSE_CMD_RESERVED_6A_LSB 0
#define TCL_GSE_CMD_RESERVED_6A_MSB 31
#define TCL_GSE_CMD_RESERVED_6A_MASK 0xffffffff
#define TCL_GSE_CMD_RESERVED_7A_OFFSET 0x0000001c
#define TCL_GSE_CMD_RESERVED_7A_LSB 0
#define TCL_GSE_CMD_RESERVED_7A_MSB 19
#define TCL_GSE_CMD_RESERVED_7A_MASK 0x000fffff
#define TCL_GSE_CMD_RING_ID_OFFSET 0x0000001c
#define TCL_GSE_CMD_RING_ID_LSB 20
#define TCL_GSE_CMD_RING_ID_MSB 27
#define TCL_GSE_CMD_RING_ID_MASK 0x0ff00000
#define TCL_GSE_CMD_LOOPING_COUNT_OFFSET 0x0000001c
#define TCL_GSE_CMD_LOOPING_COUNT_LSB 28
#define TCL_GSE_CMD_LOOPING_COUNT_MSB 31
#define TCL_GSE_CMD_LOOPING_COUNT_MASK 0xf0000000
#endif

38
hw/fig/v1/uniform_reo_cmd_header.h
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _UNIFORM_REO_CMD_HEADER_H_
#define _UNIFORM_REO_CMD_HEADER_H_
#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1
struct uniform_reo_cmd_header {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t reo_cmd_number : 16,
reo_status_required : 1,
reserved_0a : 15;
#else
uint32_t reserved_0a : 15,
reo_status_required : 1,
reo_cmd_number : 16;
#endif
};
#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_LSB 0
#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MSB 15
#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_LSB 17
#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MSB 31
#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
#endif

52
hw/fig/v1/uniform_reo_status_header.h
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/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _UNIFORM_REO_STATUS_HEADER_H_
#define _UNIFORM_REO_STATUS_HEADER_H_
#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2
struct uniform_reo_status_header {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t reo_status_number : 16,
cmd_execution_time : 10,
reo_cmd_execution_status : 2,
reserved_0a : 4;
uint32_t timestamp : 32;
#else
uint32_t reserved_0a : 4,
reo_cmd_execution_status : 2,
cmd_execution_time : 10,
reo_status_number : 16;
uint32_t timestamp : 32;
#endif
};
#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_LSB 28
#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MSB 31
#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_LSB 0
#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MSB 31
#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
#endif

243
hw/fig/v1/wbm2sw_completion_ring_tx.h
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@ -1,243 +0,0 @@
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
* SPDX-License-Identifier: ISC
*/
#ifndef _WBM2SW_COMPLETION_RING_TX_H_
#define _WBM2SW_COMPLETION_RING_TX_H_
#include "tx_rate_stats_info.h"
#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_TX 8
struct wbm2sw_completion_ring_tx {
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
uint32_t buffer_virt_addr_31_0 : 32;
uint32_t buffer_virt_addr_63_32 : 32;
uint32_t release_source_module : 3,
cache_id : 1,
reserved_2a : 2,
buffer_or_desc_type : 3,
return_buffer_manager : 4,
tqm_release_reason : 4,
rbm_override_valid : 1,
sw_buffer_cookie_11_0 : 12,
cookie_conversion_status : 1,
wbm_internal_error : 1;
uint32_t tqm_status_number : 24,
transmit_count : 7,
sw_release_details_valid : 1;
uint32_t ack_frame_rssi : 8,
first_msdu : 1,
last_msdu : 1,
fw_tx_notify_frame : 3,
buffer_timestamp : 19;
struct tx_rate_stats_info tx_rate_stats;
uint32_t sw_peer_id : 16,
tid : 4,
sw_buffer_cookie_19_12 : 8,
looping_count : 4;
#else
uint32_t buffer_virt_addr_31_0 : 32;
uint32_t buffer_virt_addr_63_32 : 32;
uint32_t wbm_internal_error : 1,
cookie_conversion_status : 1,
sw_buffer_cookie_11_0 : 12,
rbm_override_valid : 1,
tqm_release_reason : 4,
return_buffer_manager : 4,
buffer_or_desc_type : 3,
reserved_2a : 2,
cache_id : 1,
release_source_module : 3;
uint32_t sw_release_details_valid : 1,
transmit_count : 7,
tqm_status_number : 24;
uint32_t buffer_timestamp : 19,
fw_tx_notify_frame : 3,
last_msdu : 1,
first_msdu : 1,
ack_frame_rssi : 8;
struct tx_rate_stats_info tx_rate_stats;
uint32_t looping_count : 4,
sw_buffer_cookie_19_12 : 8,
tid : 4,
sw_peer_id : 16;
#endif
};
#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000
#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_LSB 0
#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MSB 31
#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff
#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004
#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_LSB 0
#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MSB 31
#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff
#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008
#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_LSB 0
#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MSB 2
#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007
#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_OFFSET 0x00000008
#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_LSB 3
#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MSB 3
#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MASK 0x00000008
#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_OFFSET 0x00000008
#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_LSB 4
#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MSB 5
#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MASK 0x00000030
#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008
#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6
#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8
#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0
#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008
#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_LSB 9
#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MSB 12
#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MASK 0x00001e00
#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008
#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB 13
#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MSB 16
#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000
#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008
#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_LSB 17
#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MSB 17
#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000
#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_OFFSET 0x00000008
#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_LSB 18
#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MSB 29
#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MASK 0x3ffc0000
#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008
#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30
#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30
#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000
#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008
#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_LSB 31
#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MSB 31
#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000
#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c
#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_LSB 0
#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MSB 23
#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff
#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c
#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_LSB 24
#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MSB 30
#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000
#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c
#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31
#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31
#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000
#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010
#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_LSB 0
#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MSB 7
#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff
#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_OFFSET 0x00000010
#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_LSB 8
#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MSB 8
#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MASK 0x00000100
#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_OFFSET 0x00000010
#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_LSB 9
#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MSB 9
#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MASK 0x00000200
#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010
#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10
#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12
#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00
#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010
#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_LSB 13
#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MSB 31
#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB 29
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB 31
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31
#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff
#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_OFFSET 0x0000001c
#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_LSB 0
#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MSB 15
#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MASK 0x0000ffff
#define WBM2SW_COMPLETION_RING_TX_TID_OFFSET 0x0000001c
#define WBM2SW_COMPLETION_RING_TX_TID_LSB 16
#define WBM2SW_COMPLETION_RING_TX_TID_MSB 19
#define WBM2SW_COMPLETION_RING_TX_TID_MASK 0x000f0000
#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_OFFSET 0x0000001c
#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_LSB 20
#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MSB 27
#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MASK 0x0ff00000
#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c
#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_LSB 28
#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MSB 31
#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MASK 0xf0000000
#endif