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arm64: dts: qcom: sm8150: Add cpufreq HW device node

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Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+ cores
on SM8150 SoCs.

Change-Id: I37fe076fbcc66b04183939ef555381f02825f387
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/20191219120633.20723-1-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Git-commit: fea8930bd55e6d88e43ce44cd058aee3b85de274
Git-repo: https://kernel.googlesource.com/pub/scm/linux/kernel/git/next/linux-next
[vvegivad@codeaurora.org: minor modifications needed to handle as per cpufreq-hw driver]
Signed-off-by: Veera Vegivada <vvegivad@qti.qualcomm.com>
This commit is contained in:
Veera Vegivada 2020-11-06 09:23:45 +05:30
commit ee17ea5be7
1 changed files with 22 additions and 0 deletions
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22
qcom/sm8150.dtsi
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@ -42,6 +42,7 @@
cpu-idle-states = <&SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@ -76,6 +77,7 @@
cpu-idle-states = <&SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@ -105,6 +107,7 @@
cpu-idle-states = <&SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_2>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@ -134,6 +137,7 @@
cpu-idle-states = <&SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_3>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@ -163,6 +167,7 @@
cpu-idle-states = <&GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1740>;
next-level-cache = <&L2_4>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@ -201,6 +206,7 @@
cpu-idle-states = <&GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1740>;
next-level-cache = <&L2_5>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@ -239,6 +245,7 @@
cpu-idle-states = <&GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1740>;
next-level-cache = <&L2_6>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@ -277,6 +284,7 @@
cpu-idle-states = <&GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1740>;
next-level-cache = <&L2_7>;
qcom,freq-domain = <&cpufreq_hw 2 4>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@ -849,6 +857,20 @@
#clock-cells = <1>;
};
cpufreq_hw: cpufreq@18323000 {
compatible = "qcom,cpufreq-hw";
reg = <0x18323000 0x1400>, <0x18325800 0x1400>,
<0x18327800 0x1400>;
reg-names = "freq-domain0", "freq-domain1",
"freq-domain2";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <2>;
};
osm_l3: interconnect@0x18321000 {
reg = <0x18321000 0x1400>;
compatible = "qcom,sm8150-osm-l3";