mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-30 11:41:38 -04:00
ARM SoC device tree changes
These changes from 30 individual branches for the most part update device tree files, but there are also a few source code changes that have crept in this time, usually in order to atomically move over a driver from using hardcoded data to DT probing. A number of platforms change their DT files to use the C preprocessor, which is causing a bit of churn, but that is hopefully only this once. There are a few conflicts with the other branches unfortunately: * in exynos5440.dtsi and kirkwood-6281.dtsi, device nodes are added from multiple branches. Need to be careful to have the right set of closing braces as git gets this one wrong. * In kirkwood.dtsi, one 'ranges' line got split into two lines, while another line got added. Order of the lines does not matter. * in sama5d3.dtsi, some cleanup was merged the wrong way, causing a bogus conflict. We want the 'dmas' and 'dma-names' properties to get added here. * Two lines got removed independently in arch/arm/mach-mxs/mach-mxs.c * Contents get added independently in arch/arm/mach-omap2/cclock33xx_data.c -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAUdLnpGCrR//JCVInAQI50RAAsXbH1SGvjKJemXhRkFloPDYpCbgdDUFr ChUbjNV1xsY/jaNCfMa5/Qo7lgz/Ot7BpJef9fZn7ret+dc7nchqe/4iIkAokAUh E4ao9D1dP5aAA0ihdbSQHCZtR/0SUR81h6BoOVuo/1mvEiBaFbWAeYe8/6LJd9II OU1w9bDmjfZWYFUXs+j2VF76ueZQ+kz69XDKZUGtkqN76m1AL8lGDurj5jxvyllF VJns8d9q2nr2q9PferfajK6rkOIPaTpwKblxZHUgobCyOitZaiZM0NgF733TsNM6 HXmhDhkcn7T81+SiHVfigJ/nxo9UgU4zNJCODF3WZIwGIj3FbxvCOpdCYi2NhCO8 oLcgDk57tpoKpB3gvAmYVQHP9FIepFa/WAWyPIADA7PkpYrwgc4v+cLEHXpd8SRv viLLIa5QuNdMeaK+Md9OKmKZFd7uFD9jiMtmdm6IpEVDDjMgoteb2XSoEtNebmtY MfbW4okn118a2dFKKaPTKcXVW/a5FRp2JGfB0A58RQHaJWj3JsY1bFn/xWPEpTOA IWB/HHMln0LYTL2AXN9HcaL1jnGI1Wq5eWBurX+cXQ/ij1A6jfoRKYglx7AQqOHj iWcGYtKLLJCgiWFnLSwcljZhfoYr0/z7rhns6yo7/vhN0riy+M84OgN4HbAmUzc1 Bgy9PnJTNo8= =8PtJ -----END PGP SIGNATURE----- Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device tree changes from Arnd Bergmann: "These changes from 30 individual branches for the most part update device tree files, but there are also a few source code changes that have crept in this time, usually in order to atomically move over a driver from using hardcoded data to DT probing. A number of platforms change their DT files to use the C preprocessor, which is causing a bit of churn, but that is hopefully only this once" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (372 commits) ARM: at91: dt: rm9200ek: add spi support ARM: at91: dt: rm9200: add spi support ARM: at91/DT: at91sam9n12: add SPI DMA client infos ARM: at91/DT: sama5d3: add SPI DMA client infos ARM: at91/DT: fix SPI compatibility string ARM: Kirkwood: Fix the internal register ranges translation ARM: dts: bcm281xx: change comment to C89 style ARM: mmc: bcm281xx SDHCI driver (dt mods) ARM: nomadik: add the new clocks to the device tree clk: nomadik: implement the Nomadik clocks properly ARM: dts: omap5-uevm: Provide USB Host PHY clock frequency ARM: dts: omap4-panda: Fix DVI EDID reads ARM: dts: omap4-panda: Add USB Host support arm: mvebu: enable mini-PCIe connectors on Armada 370 RD ARM: shmobile: irqpin: add a DT property to enable masking on parent ARM: dts: AM43x EPOS EVM support ARM: dts: OMAP5: Add bandgap DT entry ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone ...
This commit is contained in:
Linus Torvalds
commit
ee1a8d402e
297 changed files with 15464 additions and 3271 deletions
|
|
@ -1,48 +1,566 @@
|
|||
/*
|
||||
* Nomadik clock implementation
|
||||
* Copyright (C) 2013 ST-Ericsson AB
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
* Author: Linus Walleij <linus.walleij@linaro.org>
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) "Nomadik SRC clocks: " fmt
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/reboot.h>
|
||||
|
||||
/*
|
||||
* The Nomadik clock tree is described in the STN8815A12 DB V4.2
|
||||
* reference manual for the chip, page 94 ff.
|
||||
* Clock IDs are in the STn8815 Reference Manual table 3, page 27.
|
||||
*/
|
||||
|
||||
#define SRC_CR 0x00U
|
||||
#define SRC_XTALCR 0x0CU
|
||||
#define SRC_XTALCR_XTALTIMEN BIT(20)
|
||||
#define SRC_XTALCR_SXTALDIS BIT(19)
|
||||
#define SRC_XTALCR_MXTALSTAT BIT(2)
|
||||
#define SRC_XTALCR_MXTALEN BIT(1)
|
||||
#define SRC_XTALCR_MXTALOVER BIT(0)
|
||||
#define SRC_PLLCR 0x10U
|
||||
#define SRC_PLLCR_PLLTIMEN BIT(29)
|
||||
#define SRC_PLLCR_PLL2EN BIT(28)
|
||||
#define SRC_PLLCR_PLL1STAT BIT(2)
|
||||
#define SRC_PLLCR_PLL1EN BIT(1)
|
||||
#define SRC_PLLCR_PLL1OVER BIT(0)
|
||||
#define SRC_PLLFR 0x14U
|
||||
#define SRC_PCKEN0 0x24U
|
||||
#define SRC_PCKDIS0 0x28U
|
||||
#define SRC_PCKENSR0 0x2CU
|
||||
#define SRC_PCKSR0 0x30U
|
||||
#define SRC_PCKEN1 0x34U
|
||||
#define SRC_PCKDIS1 0x38U
|
||||
#define SRC_PCKENSR1 0x3CU
|
||||
#define SRC_PCKSR1 0x40U
|
||||
|
||||
/* Lock protecting the SRC_CR register */
|
||||
static DEFINE_SPINLOCK(src_lock);
|
||||
/* Base address of the SRC */
|
||||
static void __iomem *src_base;
|
||||
|
||||
/**
|
||||
* struct clk_pll1 - Nomadik PLL1 clock
|
||||
* @hw: corresponding clock hardware entry
|
||||
* @id: PLL instance: 1 or 2
|
||||
*/
|
||||
struct clk_pll {
|
||||
struct clk_hw hw;
|
||||
int id;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct clk_src - Nomadik src clock
|
||||
* @hw: corresponding clock hardware entry
|
||||
* @id: the clock ID
|
||||
* @group1: true if the clock is in group1, else it is in group0
|
||||
* @clkbit: bit 0...31 corresponding to the clock in each clock register
|
||||
*/
|
||||
struct clk_src {
|
||||
struct clk_hw hw;
|
||||
int id;
|
||||
bool group1;
|
||||
u32 clkbit;
|
||||
};
|
||||
|
||||
#define to_pll(_hw) container_of(_hw, struct clk_pll, hw)
|
||||
#define to_src(_hw) container_of(_hw, struct clk_src, hw)
|
||||
|
||||
static int pll_clk_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_pll *pll = to_pll(hw);
|
||||
u32 val;
|
||||
|
||||
spin_lock(&src_lock);
|
||||
val = readl(src_base + SRC_PLLCR);
|
||||
if (pll->id == 1) {
|
||||
if (val & SRC_PLLCR_PLL1OVER) {
|
||||
val |= SRC_PLLCR_PLL1EN;
|
||||
writel(val, src_base + SRC_PLLCR);
|
||||
}
|
||||
} else if (pll->id == 2) {
|
||||
val |= SRC_PLLCR_PLL2EN;
|
||||
writel(val, src_base + SRC_PLLCR);
|
||||
}
|
||||
spin_unlock(&src_lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void pll_clk_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_pll *pll = to_pll(hw);
|
||||
u32 val;
|
||||
|
||||
spin_lock(&src_lock);
|
||||
val = readl(src_base + SRC_PLLCR);
|
||||
if (pll->id == 1) {
|
||||
if (val & SRC_PLLCR_PLL1OVER) {
|
||||
val &= ~SRC_PLLCR_PLL1EN;
|
||||
writel(val, src_base + SRC_PLLCR);
|
||||
}
|
||||
} else if (pll->id == 2) {
|
||||
val &= ~SRC_PLLCR_PLL2EN;
|
||||
writel(val, src_base + SRC_PLLCR);
|
||||
}
|
||||
spin_unlock(&src_lock);
|
||||
}
|
||||
|
||||
static int pll_clk_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_pll *pll = to_pll(hw);
|
||||
u32 val;
|
||||
|
||||
val = readl(src_base + SRC_PLLCR);
|
||||
if (pll->id == 1) {
|
||||
if (val & SRC_PLLCR_PLL1OVER)
|
||||
return !!(val & SRC_PLLCR_PLL1EN);
|
||||
} else if (pll->id == 2) {
|
||||
return !!(val & SRC_PLLCR_PLL2EN);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_pll *pll = to_pll(hw);
|
||||
u32 val;
|
||||
|
||||
val = readl(src_base + SRC_PLLFR);
|
||||
|
||||
if (pll->id == 1) {
|
||||
u8 mul;
|
||||
u8 div;
|
||||
|
||||
mul = (val >> 8) & 0x3FU;
|
||||
mul += 2;
|
||||
div = val & 0x07U;
|
||||
return (parent_rate * mul) >> div;
|
||||
}
|
||||
|
||||
if (pll->id == 2) {
|
||||
u8 mul;
|
||||
|
||||
mul = (val >> 24) & 0x3FU;
|
||||
mul += 2;
|
||||
return (parent_rate * mul);
|
||||
}
|
||||
|
||||
/* Unknown PLL */
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static const struct clk_ops pll_clk_ops = {
|
||||
.enable = pll_clk_enable,
|
||||
.disable = pll_clk_disable,
|
||||
.is_enabled = pll_clk_is_enabled,
|
||||
.recalc_rate = pll_clk_recalc_rate,
|
||||
};
|
||||
|
||||
static struct clk * __init
|
||||
pll_clk_register(struct device *dev, const char *name,
|
||||
const char *parent_name, u32 id)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_pll *pll;
|
||||
struct clk_init_data init;
|
||||
|
||||
if (id != 1 && id != 2) {
|
||||
pr_err("%s: the Nomadik has only PLL 1 & 2\n", __func__);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
|
||||
if (!pll) {
|
||||
pr_err("%s: could not allocate PLL clk\n", __func__);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
init.name = name;
|
||||
init.ops = &pll_clk_ops;
|
||||
init.parent_names = (parent_name ? &parent_name : NULL);
|
||||
init.num_parents = (parent_name ? 1 : 0);
|
||||
pll->hw.init = &init;
|
||||
pll->id = id;
|
||||
|
||||
pr_debug("register PLL1 clock \"%s\"\n", name);
|
||||
|
||||
clk = clk_register(dev, &pll->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(pll);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
/*
|
||||
* The Nomadik SRC clocks are gated, but not in the sense that
|
||||
* you read-modify-write a register. Instead there are separate
|
||||
* clock enable and clock disable registers. Writing a '1' bit in
|
||||
* the enable register for a certain clock ungates that clock without
|
||||
* affecting the other clocks. The disable register works the opposite
|
||||
* way.
|
||||
*/
|
||||
|
||||
static int src_clk_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_src *sclk = to_src(hw);
|
||||
u32 enreg = sclk->group1 ? SRC_PCKEN1 : SRC_PCKEN0;
|
||||
u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
|
||||
|
||||
writel(sclk->clkbit, src_base + enreg);
|
||||
/* spin until enabled */
|
||||
while (!(readl(src_base + sreg) & sclk->clkbit))
|
||||
cpu_relax();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void src_clk_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_src *sclk = to_src(hw);
|
||||
u32 disreg = sclk->group1 ? SRC_PCKDIS1 : SRC_PCKDIS0;
|
||||
u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
|
||||
|
||||
writel(sclk->clkbit, src_base + disreg);
|
||||
/* spin until disabled */
|
||||
while (readl(src_base + sreg) & sclk->clkbit)
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
static int src_clk_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_src *sclk = to_src(hw);
|
||||
u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
|
||||
u32 val = readl(src_base + sreg);
|
||||
|
||||
return !!(val & sclk->clkbit);
|
||||
}
|
||||
|
||||
static unsigned long
|
||||
src_clk_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
return parent_rate;
|
||||
}
|
||||
|
||||
static const struct clk_ops src_clk_ops = {
|
||||
.enable = src_clk_enable,
|
||||
.disable = src_clk_disable,
|
||||
.is_enabled = src_clk_is_enabled,
|
||||
.recalc_rate = src_clk_recalc_rate,
|
||||
};
|
||||
|
||||
static struct clk * __init
|
||||
src_clk_register(struct device *dev, const char *name,
|
||||
const char *parent_name, u8 id)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_src *sclk;
|
||||
struct clk_init_data init;
|
||||
|
||||
sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);
|
||||
if (!sclk) {
|
||||
pr_err("could not allocate SRC clock %s\n",
|
||||
name);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
init.name = name;
|
||||
init.ops = &src_clk_ops;
|
||||
/* Do not force-disable the static SDRAM controller */
|
||||
if (id == 2)
|
||||
init.flags = CLK_IGNORE_UNUSED;
|
||||
else
|
||||
init.flags = 0;
|
||||
init.parent_names = (parent_name ? &parent_name : NULL);
|
||||
init.num_parents = (parent_name ? 1 : 0);
|
||||
sclk->hw.init = &init;
|
||||
sclk->id = id;
|
||||
sclk->group1 = (id > 31);
|
||||
sclk->clkbit = BIT(id & 0x1f);
|
||||
|
||||
pr_debug("register clock \"%s\" ID: %d group: %d bits: %08x\n",
|
||||
name, id, sclk->group1, sclk->clkbit);
|
||||
|
||||
clk = clk_register(dev, &sclk->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(sclk);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
|
||||
static u32 src_pcksr0_boot;
|
||||
static u32 src_pcksr1_boot;
|
||||
|
||||
static const char * const src_clk_names[] = {
|
||||
"HCLKDMA0 ",
|
||||
"HCLKSMC ",
|
||||
"HCLKSDRAM ",
|
||||
"HCLKDMA1 ",
|
||||
"HCLKCLCD ",
|
||||
"PCLKIRDA ",
|
||||
"PCLKSSP ",
|
||||
"PCLKUART0 ",
|
||||
"PCLKSDI ",
|
||||
"PCLKI2C0 ",
|
||||
"PCLKI2C1 ",
|
||||
"PCLKUART1 ",
|
||||
"PCLMSP0 ",
|
||||
"HCLKUSB ",
|
||||
"HCLKDIF ",
|
||||
"HCLKSAA ",
|
||||
"HCLKSVA ",
|
||||
"PCLKHSI ",
|
||||
"PCLKXTI ",
|
||||
"PCLKUART2 ",
|
||||
"PCLKMSP1 ",
|
||||
"PCLKMSP2 ",
|
||||
"PCLKOWM ",
|
||||
"HCLKHPI ",
|
||||
"PCLKSKE ",
|
||||
"PCLKHSEM ",
|
||||
"HCLK3D ",
|
||||
"HCLKHASH ",
|
||||
"HCLKCRYP ",
|
||||
"PCLKMSHC ",
|
||||
"HCLKUSBM ",
|
||||
"HCLKRNG ",
|
||||
"RESERVED ",
|
||||
"RESERVED ",
|
||||
"RESERVED ",
|
||||
"RESERVED ",
|
||||
"CLDCLK ",
|
||||
"IRDACLK ",
|
||||
"SSPICLK ",
|
||||
"UART0CLK ",
|
||||
"SDICLK ",
|
||||
"I2C0CLK ",
|
||||
"I2C1CLK ",
|
||||
"UART1CLK ",
|
||||
"MSPCLK0 ",
|
||||
"USBCLK ",
|
||||
"DIFCLK ",
|
||||
"IPI2CCLK ",
|
||||
"IPBMCCLK ",
|
||||
"HSICLKRX ",
|
||||
"HSICLKTX ",
|
||||
"UART2CLK ",
|
||||
"MSPCLK1 ",
|
||||
"MSPCLK2 ",
|
||||
"OWMCLK ",
|
||||
"RESERVED ",
|
||||
"SKECLK ",
|
||||
"RESERVED ",
|
||||
"3DCLK ",
|
||||
"PCLKMSP3 ",
|
||||
"MSPCLK3 ",
|
||||
"MSHCCLK ",
|
||||
"USBMCLK ",
|
||||
"RNGCCLK ",
|
||||
};
|
||||
|
||||
static int nomadik_src_clk_show(struct seq_file *s, void *what)
|
||||
{
|
||||
int i;
|
||||
u32 src_pcksr0 = readl(src_base + SRC_PCKSR0);
|
||||
u32 src_pcksr1 = readl(src_base + SRC_PCKSR1);
|
||||
u32 src_pckensr0 = readl(src_base + SRC_PCKENSR0);
|
||||
u32 src_pckensr1 = readl(src_base + SRC_PCKENSR1);
|
||||
|
||||
seq_printf(s, "Clock: Boot: Now: Request: ASKED:\n");
|
||||
for (i = 0; i < ARRAY_SIZE(src_clk_names); i++) {
|
||||
u32 pcksrb = (i < 0x20) ? src_pcksr0_boot : src_pcksr1_boot;
|
||||
u32 pcksr = (i < 0x20) ? src_pcksr0 : src_pcksr1;
|
||||
u32 pckreq = (i < 0x20) ? src_pckensr0 : src_pckensr1;
|
||||
u32 mask = BIT(i & 0x1f);
|
||||
|
||||
seq_printf(s, "%s %s %s %s\n",
|
||||
src_clk_names[i],
|
||||
(pcksrb & mask) ? "on " : "off",
|
||||
(pcksr & mask) ? "on " : "off",
|
||||
(pckreq & mask) ? "on " : "off");
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nomadik_src_clk_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
return single_open(file, nomadik_src_clk_show, NULL);
|
||||
}
|
||||
|
||||
static const struct file_operations nomadik_src_clk_debugfs_ops = {
|
||||
.open = nomadik_src_clk_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = single_release,
|
||||
};
|
||||
|
||||
static int __init nomadik_src_clk_init_debugfs(void)
|
||||
{
|
||||
src_pcksr0_boot = readl(src_base + SRC_PCKSR0);
|
||||
src_pcksr1_boot = readl(src_base + SRC_PCKSR1);
|
||||
debugfs_create_file("nomadik-src-clk", S_IFREG | S_IRUGO,
|
||||
NULL, NULL, &nomadik_src_clk_debugfs_ops);
|
||||
return 0;
|
||||
}
|
||||
|
||||
module_init(nomadik_src_clk_init_debugfs);
|
||||
|
||||
#endif
|
||||
|
||||
static void __init of_nomadik_pll_setup(struct device_node *np)
|
||||
{
|
||||
struct clk *clk = ERR_PTR(-EINVAL);
|
||||
const char *clk_name = np->name;
|
||||
const char *parent_name;
|
||||
u32 pll_id;
|
||||
|
||||
if (of_property_read_u32(np, "pll-id", &pll_id)) {
|
||||
pr_err("%s: PLL \"%s\" missing pll-id property\n",
|
||||
__func__, clk_name);
|
||||
return;
|
||||
}
|
||||
parent_name = of_clk_get_parent_name(np, 0);
|
||||
clk = pll_clk_register(NULL, clk_name, parent_name, pll_id);
|
||||
if (!IS_ERR(clk))
|
||||
of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
||||
}
|
||||
|
||||
static void __init of_nomadik_hclk_setup(struct device_node *np)
|
||||
{
|
||||
struct clk *clk = ERR_PTR(-EINVAL);
|
||||
const char *clk_name = np->name;
|
||||
const char *parent_name;
|
||||
|
||||
parent_name = of_clk_get_parent_name(np, 0);
|
||||
/*
|
||||
* The HCLK divides PLL1 with 1 (passthru), 2, 3 or 4.
|
||||
*/
|
||||
clk = clk_register_divider(NULL, clk_name, parent_name,
|
||||
0, src_base + SRC_CR,
|
||||
13, 2,
|
||||
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
|
||||
&src_lock);
|
||||
if (!IS_ERR(clk))
|
||||
of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
||||
}
|
||||
|
||||
static void __init of_nomadik_src_clk_setup(struct device_node *np)
|
||||
{
|
||||
struct clk *clk = ERR_PTR(-EINVAL);
|
||||
const char *clk_name = np->name;
|
||||
const char *parent_name;
|
||||
u32 clk_id;
|
||||
|
||||
if (of_property_read_u32(np, "clock-id", &clk_id)) {
|
||||
pr_err("%s: SRC clock \"%s\" missing clock-id property\n",
|
||||
__func__, clk_name);
|
||||
return;
|
||||
}
|
||||
parent_name = of_clk_get_parent_name(np, 0);
|
||||
clk = src_clk_register(NULL, clk_name, parent_name, clk_id);
|
||||
if (!IS_ERR(clk))
|
||||
of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
||||
}
|
||||
|
||||
static const __initconst struct of_device_id nomadik_src_match[] = {
|
||||
{ .compatible = "stericsson,nomadik-src" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const __initconst struct of_device_id nomadik_src_clk_match[] = {
|
||||
{
|
||||
.compatible = "fixed-clock",
|
||||
.data = of_fixed_clk_setup,
|
||||
},
|
||||
{
|
||||
.compatible = "fixed-factor-clock",
|
||||
.data = of_fixed_factor_clk_setup,
|
||||
},
|
||||
{
|
||||
.compatible = "st,nomadik-pll-clock",
|
||||
.data = of_nomadik_pll_setup,
|
||||
},
|
||||
{
|
||||
.compatible = "st,nomadik-hclk-clock",
|
||||
.data = of_nomadik_hclk_setup,
|
||||
},
|
||||
{
|
||||
.compatible = "st,nomadik-src-clock",
|
||||
.data = of_nomadik_src_clk_setup,
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int nomadik_clk_reboot_handler(struct notifier_block *this,
|
||||
unsigned long code,
|
||||
void *unused)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/* The main chrystal need to be enabled for reboot to work */
|
||||
val = readl(src_base + SRC_XTALCR);
|
||||
val &= ~SRC_XTALCR_MXTALOVER;
|
||||
val |= SRC_XTALCR_MXTALEN;
|
||||
pr_crit("force-enabling MXTALO\n");
|
||||
writel(val, src_base + SRC_XTALCR);
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
static struct notifier_block nomadik_clk_reboot_notifier = {
|
||||
.notifier_call = nomadik_clk_reboot_handler,
|
||||
};
|
||||
|
||||
void __init nomadik_clk_init(void)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct device_node *np;
|
||||
u32 val;
|
||||
|
||||
clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
|
||||
clk_register_clkdev(clk, "apb_pclk", NULL);
|
||||
clk_register_clkdev(clk, NULL, "gpio.0");
|
||||
clk_register_clkdev(clk, NULL, "gpio.1");
|
||||
clk_register_clkdev(clk, NULL, "gpio.2");
|
||||
clk_register_clkdev(clk, NULL, "gpio.3");
|
||||
clk_register_clkdev(clk, NULL, "rng");
|
||||
clk_register_clkdev(clk, NULL, "fsmc-nand");
|
||||
np = of_find_matching_node(NULL, nomadik_src_match);
|
||||
if (!np) {
|
||||
pr_crit("no matching node for SRC, aborting clock init\n");
|
||||
return;
|
||||
}
|
||||
src_base = of_iomap(np, 0);
|
||||
if (!src_base) {
|
||||
pr_err("%s: must have src parent node with REGS (%s)\n",
|
||||
__func__, np->name);
|
||||
return;
|
||||
}
|
||||
val = readl(src_base + SRC_XTALCR);
|
||||
pr_info("SXTALO is %s\n",
|
||||
(val & SRC_XTALCR_SXTALDIS) ? "disabled" : "enabled");
|
||||
pr_info("MXTAL is %s\n",
|
||||
(val & SRC_XTALCR_MXTALSTAT) ? "enabled" : "disabled");
|
||||
if (of_property_read_bool(np, "disable-sxtalo")) {
|
||||
/* The machine uses an external oscillator circuit */
|
||||
val |= SRC_XTALCR_SXTALDIS;
|
||||
pr_info("disabling SXTALO\n");
|
||||
}
|
||||
if (of_property_read_bool(np, "disable-mxtalo")) {
|
||||
/* Disable this too: also run by external oscillator */
|
||||
val |= SRC_XTALCR_MXTALOVER;
|
||||
val &= ~SRC_XTALCR_MXTALEN;
|
||||
pr_info("disabling MXTALO\n");
|
||||
}
|
||||
writel(val, src_base + SRC_XTALCR);
|
||||
register_reboot_notifier(&nomadik_clk_reboot_notifier);
|
||||
|
||||
/*
|
||||
* The 2.4 MHz TIMCLK reference clock is active at boot time, this is
|
||||
* actually the MXTALCLK @19.2 MHz divided by 8. This clock is used
|
||||
* by the timers and watchdog. See page 105 ff.
|
||||
*/
|
||||
clk = clk_register_fixed_rate(NULL, "TIMCLK", NULL, CLK_IS_ROOT,
|
||||
2400000);
|
||||
clk_register_clkdev(clk, NULL, "mtu0");
|
||||
clk_register_clkdev(clk, NULL, "mtu1");
|
||||
|
||||
/*
|
||||
* At boot time, PLL2 is set to generate a set of fixed clocks,
|
||||
* one of them is CLK48, the 48 MHz clock, routed to the UART, MMC/SD
|
||||
* I2C, IrDA, USB and SSP blocks.
|
||||
*/
|
||||
clk = clk_register_fixed_rate(NULL, "CLK48", NULL, CLK_IS_ROOT,
|
||||
48000000);
|
||||
clk_register_clkdev(clk, NULL, "uart0");
|
||||
clk_register_clkdev(clk, NULL, "uart1");
|
||||
clk_register_clkdev(clk, NULL, "mmci");
|
||||
clk_register_clkdev(clk, NULL, "ssp");
|
||||
clk_register_clkdev(clk, NULL, "nmk-i2c.0");
|
||||
clk_register_clkdev(clk, NULL, "nmk-i2c.1");
|
||||
of_clk_init(nomadik_src_clk_match);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -151,7 +151,7 @@ enum exynos4_clks {
|
|||
sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
|
||||
sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
|
||||
sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp,
|
||||
sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp,
|
||||
sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, sclk_fimg2d,
|
||||
|
||||
/* gate clocks */
|
||||
fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
|
||||
|
|
@ -484,6 +484,9 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
|
|||
MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
|
||||
MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
|
||||
MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
|
||||
MUX(none, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
|
||||
MUX(none, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
|
||||
MUX(none, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
|
||||
};
|
||||
|
||||
/* list of divider clocks supported in all exynos4 soc's */
|
||||
|
|
@ -552,7 +555,7 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
|
|||
/* list of divider clocks supported in exynos4210 soc */
|
||||
struct samsung_div_clock exynos4210_div_clks[] __initdata = {
|
||||
DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
|
||||
DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4),
|
||||
DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
|
||||
DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
|
||||
DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
|
||||
DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
|
||||
|
|
@ -582,6 +585,7 @@ struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
|
|||
DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
|
||||
DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3),
|
||||
DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3),
|
||||
DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
|
||||
};
|
||||
|
||||
/* list of gate clocks supported in all exynos4 soc's */
|
||||
|
|
@ -909,6 +913,7 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
|
|||
CLK_IGNORE_UNUSED, 0),
|
||||
GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
|
||||
CLK_IGNORE_UNUSED, 0),
|
||||
GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
|||
Loading…
Reference in a new issue