From ee63b78dc085edfa8563a0ba22fcc342eb8dfb81 Mon Sep 17 00:00:00 2001
From: Manuel Gomez <gomez@quicinc.com>
Date: Mon, 30 Aug 2021 11:47:55 -0700
Subject: [PATCH] ARM: dts: msm: Pin config for AQR and Napa INTN_WOL

Enable pin control for qps615 that is necessary to configure
the SDX65 GPIO pins for Wake on LAN support.

Change-Id: Ic5d6d76677e195fc3dec7780d99b5cf50718b8b1
---
 qcom/sdxlemur-mtp-cpe.dtsi |  6 ++++++
 qcom/sdxlemur-pinctrl.dtsi | 28 ++++++++++++++++++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi
index d6e2e5f91010..266d6df33c5c 100644
--- a/qcom/sdxlemur-mtp-cpe.dtsi
+++ b/qcom/sdxlemur-mtp-cpe.dtsi
@@ -139,6 +139,9 @@
 			qps615_eth0,qps615_eth0@pcie0_rp {
 				reg = <0x0 0x0 0x0 0x0 0x0>;
 
+				pinctrl-names = "default";
+				pinctrl-0 = <&aqr_intn_wol_sig>;
+
 				compatible = "qcom,ioss-v2-device";
 				qcom,ioss = <&ioss>;
 				qcom,ioss_interfaces = <&ioss_qps615_eth0>;
@@ -161,6 +164,9 @@
 			qps615_eth1,qps615_eth1@pcie0_rp {
 				reg = <0x100 0x0 0x0 0x0 0x0>;
 
+				pinctrl-names = "default";
+				pinctrl-0 = <&napa_intn_wol_sig>;
+
 				compatible = "qcom,ioss-v2-device";
 				qcom,ioss = <&ioss>;
 				qcom,ioss_interfaces = <&ioss_qps615_eth1>;
diff --git a/qcom/sdxlemur-pinctrl.dtsi b/qcom/sdxlemur-pinctrl.dtsi
index 60534b7cb2bb..4f5fb3392076 100644
--- a/qcom/sdxlemur-pinctrl.dtsi
+++ b/qcom/sdxlemur-pinctrl.dtsi
@@ -1699,5 +1699,33 @@
 				};
 			};
 		};
+
+		qps615_intn_wol {
+			aqr_intn_wol_sig: aqr_intn_wol_sig {
+				mux {
+					pins = "gpio103";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio103";
+					input-enable;
+					bias-disable;
+				};
+			};
+
+			napa_intn_wol_sig: napa_intn_wol_sig {
+				mux {
+					pins = "gpio81";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio81";
+					input-enable;
+					bias-disable;
+				};
+			};
+		};
 	};
 };