From ace3e120a2bc83d3a5047f1169b9b3012a1ac235 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Thu, 11 Jun 2020 16:08:03 -0700 Subject: [PATCH] ARM: dts: msm: Update PCIe0 PHY settings to v0.99 for lahaina v1 Update PCIe0 PHY settings to version 0.99 based on hardware recommendation for lahaina v1. Change-Id: I8b5bf41d88f7296bfdb4bc89a5415a803cbaafc2 --- qcom/lahaina-pcie.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi index 890c4584c6d7..fceeb83905f9 100644 --- a/qcom/lahaina-pcie.dtsi +++ b/qcom/lahaina-pcie.dtsi @@ -114,7 +114,7 @@ qcom,phy-core-pll-en-mux = <7>; qcom,phy-c-ready-status = <0x178>; - qcom,pcie-phy-ver = <10971>; + qcom,pcie-phy-ver = <10099>; qcom,phy-status-offset = <0x214>; qcom,phy-status-bit = <6>; qcom,phy-power-down-offset = <0x240>; @@ -185,11 +185,11 @@ 0x0654 0x00 0x0 0x06a8 0x0f 0x0 0x0044 0x04 0x0 - 0x0048 0xb0 0x0 + 0x0048 0xf0 0x0 + 0x0608 0x0f 0x0 0x0620 0xc1 0x0 0x0388 0xa8 0x0 0x10b0 0x18 0x0 - 0x0608 0x0f 0x0 0x0398 0x0b 0x0 0x02dc 0x05 0x0 0x0200 0x00 0x0