From 120ad4aa0d59cb89b8554184cfd072c175d5a88b Mon Sep 17 00:00:00 2001 From: Alok Pandey Date: Wed, 10 Feb 2021 11:09:39 +0530 Subject: [PATCH 1/6] ARM: dts: msm: Enable io-coherency for camera devices on Shima Enable io-coherency to avoid cache flush operations when a buffer generated by CPU module is given to a HW as input. CRs-Fixed: 2882101 Change-Id: Ibbc89c10ab8e2f89d1af1568478bafd979f42d7d --- shima-camera.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/shima-camera.dtsi b/shima-camera.dtsi index 3b923c783d9e..c7957c3b07f6 100644 --- a/shima-camera.dtsi +++ b/shima-camera.dtsi @@ -412,6 +412,7 @@ <&apps_smmu 0x1400 0x440>, <&apps_smmu 0x1440 0x440>; qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + dma-coherent-hint-cached; cam-smmu-label = "ife", "ife-cdm"; multiple-client-devices; ife_iova_mem_map: iova-mem-map { @@ -432,6 +433,7 @@ <&apps_smmu 0x2C40 0x400>; cam-smmu-label = "jpeg"; qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + dma-coherent-hint-cached; jpeg_iova_mem_map: iova-mem-map { /* IO region is approximately 3.4 GB */ iova-mem-region-io { @@ -461,6 +463,7 @@ <&apps_smmu 0x2820 0x400>, <&apps_smmu 0x2C20 0x400>; qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>; + dma-coherent-hint-cached; iova-region-discard = <0xdff00000 0x300000>; cam-smmu-label = "icp"; icp_iova_mem_map: iova-mem-map { @@ -519,6 +522,7 @@ <&apps_smmu 0x2CC0 0x400>; cam-smmu-label = "cpas-cdm"; qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + dma-coherent-hint-cached; cpas_cdm_iova_mem_map: iova-mem-map { iova-mem-region-io { /* IO region is approximately 3.4 GB */ From e03188b3f20cfd762f1021d9255e3624255b3607 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Tue, 22 Dec 2020 20:21:32 +0530 Subject: [PATCH 2/6] ARM: dts: msm: camera: Add hw pid and mid info to jpeg nodes Jpeg enc and dma hardware has unique pid values. Add pid values to each jpeg node instances. These are used to find the jpeg instance that caused page fault. Added read and write mid values for jpeg enc and dma nodes. CRs-Fixed: 2878371 Change-Id: I96f83874e59b803772a5ca8d76f1f6ebfbbfa2d9 --- bindings/msm-cam-jpeg.txt | 15 +++++++++++++++ lahaina-camera.dtsi | 6 ++++++ shima-camera.dtsi | 6 ++++++ yupik-camera.dtsi | 6 ++++++ 4 files changed, 33 insertions(+) diff --git a/bindings/msm-cam-jpeg.txt b/bindings/msm-cam-jpeg.txt index 73e99b25cd8f..edab1d95e34b 100644 --- a/bindings/msm-cam-jpeg.txt +++ b/bindings/msm-cam-jpeg.txt @@ -122,6 +122,21 @@ the device register map, interrupt map, clocks and regulators. Definition: List of strings corresponds clock-rates levels. Supported strings: minsvs, lowsvs, svs, svs_l1, nominal, turbo. +- cam_hw_pid: + Usage: optional + Value type: + Definition: HW unique Pid values + +- cam_hw_rd_mid: + Usage: optional + Value type: + Definition: HW port read mid value + +- cam_hw_wr_mid: + Usage: optional + Value type: + Definition: HW port write mid value + Examples: cam_jpeg_enc: qcom,jpegenc@ac4e000 { cell-index = <0>; diff --git a/lahaina-camera.dtsi b/lahaina-camera.dtsi index 5c273a422233..d3c50b69a3fc 100644 --- a/lahaina-camera.dtsi +++ b/lahaina-camera.dtsi @@ -1899,6 +1899,9 @@ clock-rates = <600000000 0>; src-clock-name = "jpegenc_clk_src"; clock-cntl-level = "nominal"; + cam_hw_pid = <25 26>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; status = "ok"; }; @@ -1922,6 +1925,9 @@ clock-rates = <600000000 0>; src-clock-name = "jpegdma_clk_src"; clock-cntl-level = "nominal"; + cam_hw_pid = <24 27>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; status = "ok"; }; }; diff --git a/shima-camera.dtsi b/shima-camera.dtsi index 269ed5d32abb..7b2f62e37432 100644 --- a/shima-camera.dtsi +++ b/shima-camera.dtsi @@ -1281,6 +1281,9 @@ clock-rates = <600000000 0>; src-clock-name = "jpegenc_clk_src"; clock-cntl-level = "nominal"; + cam_hw_pid = <25 26>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; status = "ok"; }; @@ -1304,6 +1307,9 @@ clock-rates = <600000000 0>; src-clock-name = "jpegdma_clk_src"; clock-cntl-level = "nominal"; + cam_hw_pid = <24 27>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <1>; status = "ok"; }; diff --git a/yupik-camera.dtsi b/yupik-camera.dtsi index 13aa22a16bfb..34a8e6be3fa5 100644 --- a/yupik-camera.dtsi +++ b/yupik-camera.dtsi @@ -1065,6 +1065,9 @@ clock-rates = <600000000 0>; src-clock-name = "jpegenc_clk_src"; clock-cntl-level = "nominal"; + cam_hw_pid = <22 23>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <2>; status = "ok"; }; @@ -1088,6 +1091,9 @@ clock-rates = <600000000 0>; src-clock-name = "jpegdma_clk_src"; clock-cntl-level = "nominal"; + cam_hw_pid = <20 21>; + cam_hw_rd_mid = <0>; + cam_hw_wr_mid = <2>; status = "ok"; }; From a70ecee4df01553add576f1ba7e1b2497f9600ec Mon Sep 17 00:00:00 2001 From: Ayush Kumar Date: Thu, 18 Feb 2021 03:43:44 +0530 Subject: [PATCH 3/6] ARM: dts: msm: Enable io-coherency for camera devices on Yupik Enable io-coherency to avoid cache flush operations when a buffer generated by CPU module is given to a HW as input. CRs-Fixed: 2882101 Change-Id: Ib8720070cd7e907a077241d5f0ad72fb4df538dd --- yupik-camera.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/yupik-camera.dtsi b/yupik-camera.dtsi index 13aa22a16bfb..64b361ef84ed 100644 --- a/yupik-camera.dtsi +++ b/yupik-camera.dtsi @@ -391,6 +391,7 @@ <&apps_smmu 0xCE0 0x4E0>; qcom,iommu-faults = "non-fatal"; qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent-hint-cached; cam-smmu-label = "ife"; multiple-client-devices; ife_iova_mem_map: iova-mem-map { @@ -412,6 +413,7 @@ cam-smmu-label = "jpeg"; qcom,iommu-faults = "non-fatal"; qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent-hint-cached; jpeg_iova_mem_map: iova-mem-map { /* IO region is approximately 3.4 GB */ iova-mem-region-io { @@ -441,6 +443,7 @@ cam-smmu-label = "icp"; qcom,iommu-faults = "non-fatal"; qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>; + dma-coherent-hint-cached; iova-region-discard = <0xdff00000 0x300000>; icp_iova_mem_map: iova-mem-map { iova-mem-region-firmware { @@ -498,6 +501,7 @@ cam-smmu-label = "cpas-cdm"; qcom,iommu-faults = "non-fatal"; qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent-hint-cached; cpas_cdm_iova_mem_map: iova-mem-map { iova-mem-region-io { /* IO region is approximately 3.4 GB */ @@ -523,6 +527,7 @@ cam-smmu-label = "lrme"; qcom,iommu-faults = "non-fatal"; qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent-hint-cached; lrme_iova_mem_map: iova-mem-map { iova-mem-region-shared { /* Shared region is 100MB long */ From c16d7e2389b0890e104ce05c6f0208928b50fd9a Mon Sep 17 00:00:00 2001 From: Pengfei Liu Date: Fri, 19 Feb 2021 10:56:49 +0800 Subject: [PATCH 4/6] ARM: dts: msm: Override eeprom front for HHG camera device Delete eeprom front node cuase failed, so override eeprom front directly in HHG platform. Change-Id: Ib8253147f1b78caa2aea628bf6f733cd3f68aec6 CRs-Fixed: 2853048 --- lahaina-camera-sensor-hhg.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/lahaina-camera-sensor-hhg.dtsi b/lahaina-camera-sensor-hhg.dtsi index 52fbf46d4e32..1fb8607cd36a 100644 --- a/lahaina-camera-sensor-hhg.dtsi +++ b/lahaina-camera-sensor-hhg.dtsi @@ -1,5 +1,4 @@ &cam_cci1 { -/delete-node/ qcom,eeprom5; /delete-node/ qcom,cam-sensor5; qcom,eeprom5 { From e312fcd8f7de2794a1eecac66d0636c774149026 Mon Sep 17 00:00:00 2001 From: Alok Pandey Date: Thu, 18 Feb 2021 17:07:32 +0530 Subject: [PATCH 5/6] ARM: dts: msm: Updating QoS for ICP Updating QoS for a5 to 0xA0A CRs-Fixed: 2880707 Change-Id: I401b61278fa95dc389f0be603b07304a0b76aba8 --- shima-camera.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/shima-camera.dtsi b/shima-camera.dtsi index 3b923c783d9e..7f89fd591b3c 100644 --- a/shima-camera.dtsi +++ b/shima-camera.dtsi @@ -1181,6 +1181,7 @@ ubwc-ipe-write-cfg = <0x161cf 0x161ef>; ubwc-bps-fetch-cfg = <0x7073 0x707b>; ubwc-bps-write-cfg = <0x161cf 0x161ef>; + qos-val = <0x00000A0A>; status = "ok"; }; From db2bf3235834196b9d5776ce949ef126cfb1e8f4 Mon Sep 17 00:00:00 2001 From: Alok Pandey Date: Wed, 27 Jan 2021 22:31:37 +0530 Subject: [PATCH 6/6] ARM: dts: msm: fix for Shima-CAMNOC RDI latency buffer corruption This is a fix to handle line corruption on RDI stream by capping IPE clock to SVS. It will help to avoid back pressure on CAMNOC dur to IPE traffic. This gives more room to IFE RDI stream and hence avoid corruption. CRs-Fixed: 2887253 Change-Id: I8880c08d507ebb90b447815a241870d03fd24bec --- shima-camera.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/shima-camera.dtsi b/shima-camera.dtsi index b8d06d5f711e..7571aa22b285 100644 --- a/shima-camera.dtsi +++ b/shima-camera.dtsi @@ -1215,9 +1215,9 @@ clock-rates = <0 0 0 300000000 0>, <0 0 0 450000000 0>, - <0 0 0 525000000 0>, - <0 0 0 700000000 0>, - <0 0 0 700000000 0>; + <0 0 0 450000000 0>, + <0 0 0 450000000 0>, + <0 0 0 450000000 0>; clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; status = "ok";