From 4fc6531b64650815177f88f5db17ba14011499c2 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Thu, 10 Sep 2020 12:50:29 +0530 Subject: [PATCH 01/66] ARM: dts: msm: Change to auto-specific config for SA8155 Change to auto-specific config for SA8155. Change-Id: Ia13ef5ac78757a3548f7b02493d067685c1e824d --- qcom/Makefile | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/qcom/Makefile b/qcom/Makefile index 1a1c6f058bd8..778cf0fcf1d6 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -132,12 +132,12 @@ dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) - dtbo-$(CONFIG_ARCH_SM8150) += \ - sm8150-cdp-overlay.dtbo \ - sa8155-adp-star-overlay.dtbo \ - sa8155p-adp-star-overlay.dtbo \ - sa8155-v2-adp-air-overlay.dtbo \ - sa8155p-v2-adp-air-overlay.dtbo + dtbo-$(CONFIG_ARCH_SA8155) += \ + sm8150-cdp-overlay.dtbo \ + sa8155-adp-star-overlay.dtbo \ + sa8155p-adp-star-overlay.dtbo \ + sa8155-v2-adp-air-overlay.dtbo \ + sa8155p-v2-adp-air-overlay.dtbo sm8150-cdp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb sa8155-adp-star-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb @@ -145,13 +145,13 @@ sa8155p-adp-star-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb sa8155-v2-adp-air-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb sa8155p-v2-adp-air-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb else -dtb-$(CONFIG_ARCH_SM8150) += sm8150-cdp.dtb \ - sa8155-adp-star.dtb \ - sa8155p-adp-star.dtb \ - sa8155-v2-adp-star.dtb \ - sa8155p-v2-adp-star.dtb \ - sa8155-v2-adp-air.dtb \ - sa8155p-v2-adp-air.dtb +dtb-$(CONFIG_ARCH_SA8155) += sm8150-cdp.dtb \ + sa8155-adp-star.dtb \ + sa8155p-adp-star.dtb \ + sa8155-v2-adp-star.dtb \ + sa8155p-v2-adp-star.dtb \ + sa8155-v2-adp-air.dtb \ + sa8155p-v2-adp-air.dtb endif endif From 41feb8e993fbaa633e9e2c8bde4a79c310cb1e7b Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Thu, 17 Sep 2020 21:02:12 +0530 Subject: [PATCH 02/66] ARM: dts: msm: Add interconnect bus voting values to Holi Currently the driver has bus voting hard coded. Adding interconnect vote values and interconnect names to do bus voting with dtsi file. Change-Id: I96cd119fdba17b7c46fc8c1642a3c28d44197c14 --- qcom/holi-usb.dtsi | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/qcom/holi-usb.dtsi b/qcom/holi-usb.dtsi index c65f56ad8dd5..a2114fc7e0b4 100644 --- a/qcom/holi-usb.dtsi +++ b/qcom/holi-usb.dtsi @@ -35,13 +35,21 @@ qcom,core-clk-rate = <133333333>; qcom,core-clk-rate-hs = <66666667>; - qcom,default-bus-vote = <2>; /* use svs bus voting */ interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; interconnects = <&system_noc MASTER_USB3_0 &bimc SLAVE_EBI>, <&system_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>, <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>; + qcom,interconnect-values-nom = /* NOMINAL Votes */ + <1000000 1550000>, + <0 2400>, + <0 40000>; + qcom,interconnect-values-svs = /* SVS Votes */ + <240000 700000>, + <0 2400>, + <0 40000>; + qcom,num-gsi-evt-buffs = <0x3>; qcom,gsi-reg-offset = <0x0fc /* GSI_GENERAL_CFG */ From 23c3661bdced1ce38ff9c3e2813e5efb1125db69 Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Wed, 7 Oct 2020 13:35:30 +0530 Subject: [PATCH 03/66] ARM: dts: msm: Remove CDP DT for SA8155 Auto targets do not use CDP boards. Remove CDP device tree for ARCH_SA8155. Change-Id: Ia5495f62770b5f81fb30de0993dbca66d1b897e7 --- qcom/Makefile | 5 +---- qcom/sm8150-cdp-overlay.dts | 14 -------------- qcom/sm8150-cdp.dts | 10 ---------- qcom/sm8150-cdp.dtsi | 2 -- 4 files changed, 1 insertion(+), 30 deletions(-) delete mode 100644 qcom/sm8150-cdp-overlay.dts delete mode 100644 qcom/sm8150-cdp.dts delete mode 100644 qcom/sm8150-cdp.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 778cf0fcf1d6..572f4f02fb0c 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -133,20 +133,17 @@ endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_SA8155) += \ - sm8150-cdp-overlay.dtbo \ sa8155-adp-star-overlay.dtbo \ sa8155p-adp-star-overlay.dtbo \ sa8155-v2-adp-air-overlay.dtbo \ sa8155p-v2-adp-air-overlay.dtbo -sm8150-cdp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb sa8155-adp-star-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb sa8155p-adp-star-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb sa8155-v2-adp-air-overlay.dtbo-base := sa8155.dtb sa8155-v2.dtb sa8155p-v2-adp-air-overlay.dtbo-base := sa8155p.dtb sa8155p-v2.dtb else -dtb-$(CONFIG_ARCH_SA8155) += sm8150-cdp.dtb \ - sa8155-adp-star.dtb \ +dtb-$(CONFIG_ARCH_SA8155) += sa8155-adp-star.dtb \ sa8155p-adp-star.dtb \ sa8155-v2-adp-star.dtb \ sa8155p-v2-adp-star.dtb \ diff --git a/qcom/sm8150-cdp-overlay.dts b/qcom/sm8150-cdp-overlay.dts deleted file mode 100644 index c4665280aa59..000000000000 --- a/qcom/sm8150-cdp-overlay.dts +++ /dev/null @@ -1,14 +0,0 @@ -/dts-v1/; -/plugin/; - -#include -#include -#include - -#include "sm8150-cdp.dtsi" - -/ { - model = "CDP"; - compatible = "qcom,sm8150-cdp", "qcom,sm8150", "qcom,cdp"; - qcom,board-id = <1 0>; -}; diff --git a/qcom/sm8150-cdp.dts b/qcom/sm8150-cdp.dts deleted file mode 100644 index ece66075cd39..000000000000 --- a/qcom/sm8150-cdp.dts +++ /dev/null @@ -1,10 +0,0 @@ -/dts-v1/; - -#include "sm8150.dtsi" -#include "sm8150-cdp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. SM8150 CDP"; - compatible = "qcom,sm8150-cdp", "qcom,sm8150", "qcom,cdp"; - qcom,board-id = <1 0>; -}; diff --git a/qcom/sm8150-cdp.dtsi b/qcom/sm8150-cdp.dtsi deleted file mode 100644 index 44b2ac0d79b8..000000000000 --- a/qcom/sm8150-cdp.dtsi +++ /dev/null @@ -1,2 +0,0 @@ -#include -#include From e7746b39c973c36816b66d30b9dc4fd3f695048c Mon Sep 17 00:00:00 2001 From: Shreyas K K Date: Wed, 1 Jul 2020 13:40:53 +0530 Subject: [PATCH 04/66] ARM: dts: msm: Add initial device tree for SA8195 Add initial device tree to support SA8195 chipset on automotive platforms. Change-Id: I30e73ea78334bbe7cd247a8f3fa556e44a722606 --- bindings/arm/msm/msm.txt | 3 + qcom/Makefile | 12 + qcom/sa8195p-adp-common.dtsi | 5 + qcom/sa8195p-adp-star-overlay.dts | 12 + qcom/sa8195p-adp-star.dts | 11 + qcom/sa8195p-adp-star.dtsi | 1 + qcom/sa8195p-v2-adp-air-overlay.dts | 13 + qcom/sa8195p-v2-adp-air.dts | 10 + qcom/sa8195p-v2-adp-air.dtsi | 1 + qcom/sa8195p.dts | 10 + qcom/sa8195p.dtsi | 8 + qcom/sdmshrike-v2.dts | 10 + qcom/sdmshrike-v2.dtsi | 8 + qcom/sdmshrike.dts | 10 + qcom/sdmshrike.dtsi | 655 ++++++++++++++++++++++++++++ 15 files changed, 769 insertions(+) create mode 100644 qcom/sa8195p-adp-common.dtsi create mode 100644 qcom/sa8195p-adp-star-overlay.dts create mode 100644 qcom/sa8195p-adp-star.dts create mode 100644 qcom/sa8195p-adp-star.dtsi create mode 100644 qcom/sa8195p-v2-adp-air-overlay.dts create mode 100644 qcom/sa8195p-v2-adp-air.dts create mode 100644 qcom/sa8195p-v2-adp-air.dtsi create mode 100644 qcom/sa8195p.dts create mode 100644 qcom/sa8195p.dtsi create mode 100644 qcom/sdmshrike-v2.dts create mode 100644 qcom/sdmshrike-v2.dtsi create mode 100644 qcom/sdmshrike.dts create mode 100644 qcom/sdmshrike.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 93709ab8e29b..259059b7f344 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -189,6 +189,9 @@ compatible = "qcom,sa8155p-adp-star" compatible = "qcom,sa8155-adp-air" compatible = "qcom,sa8155-v2-adp-air" compatible = "qcom,sa8155p-v2-adp-air" +compatible = "qcom,sa8195p-adp-star" +compatible = "qcom,sa8195p-v2-adp-air" +compatible = "qcom,sa8195p" compatible = "qcom,adp-air" compatible = "qcom,kona-rumi" compatible = "qcom,kona-mtp" diff --git a/qcom/Makefile b/qcom/Makefile index 572f4f02fb0c..02eb8a08e588 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -150,6 +150,18 @@ dtb-$(CONFIG_ARCH_SA8155) += sa8155-adp-star.dtb \ sa8155-v2-adp-air.dtb \ sa8155p-v2-adp-air.dtb endif + +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) + dtbo-$(CONFIG_ARCH_SA8195) += \ + sa8195p-adp-star-overlay.dtbo \ + sa8195p-v2-adp-air-overlay.dtbo + +sa8195p-adp-star-overlay.dtbo-base := sa8195p.dtb +sa8195p-v2-adp-air-overlay.dtbo-base := sa8195p.dtb +else +dtb-$(CONFIG_ARCH_SA8195) += sa8195p-adp-star.dtb \ + sa8195p-v2-adp-air.dtb +endif endif ifeq ($(CONFIG_ARCH_LAHAINA), y) diff --git a/qcom/sa8195p-adp-common.dtsi b/qcom/sa8195p-adp-common.dtsi new file mode 100644 index 000000000000..195d8d5a96dc --- /dev/null +++ b/qcom/sa8195p-adp-common.dtsi @@ -0,0 +1,5 @@ +#include + +&qupv3_id_1 { + status = "ok"; +}; diff --git a/qcom/sa8195p-adp-star-overlay.dts b/qcom/sa8195p-adp-star-overlay.dts new file mode 100644 index 000000000000..e6ae85d95bf7 --- /dev/null +++ b/qcom/sa8195p-adp-star-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "sa8195p-adp-star.dtsi" + +/ { + model = "ADP-STAR"; + compatible = "qcom,sa8195p-adp-star", "qcom,sa8195p", + "qcom,adp-star"; + qcom,msm-id = <405 0x20000>; + qcom,board-id = <0x010019 0>; +}; diff --git a/qcom/sa8195p-adp-star.dts b/qcom/sa8195p-adp-star.dts new file mode 100644 index 000000000000..6183b7cb3c68 --- /dev/null +++ b/qcom/sa8195p-adp-star.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sa8195p.dtsi" +#include "sa8195p-adp-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195P ADP-STAR"; + compatible = "qcom,sa8195p-adp-star", "qcom,sa8195p", + "qcom,adp-star"; + qcom,board-id = <25 0>; +}; diff --git a/qcom/sa8195p-adp-star.dtsi b/qcom/sa8195p-adp-star.dtsi new file mode 100644 index 000000000000..ec4afde21db4 --- /dev/null +++ b/qcom/sa8195p-adp-star.dtsi @@ -0,0 +1 @@ +#include "sa8195p-adp-common.dtsi" diff --git a/qcom/sa8195p-v2-adp-air-overlay.dts b/qcom/sa8195p-v2-adp-air-overlay.dts new file mode 100644 index 000000000000..dd8060574532 --- /dev/null +++ b/qcom/sa8195p-v2-adp-air-overlay.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +#include "sa8195p-v2-adp-air.dtsi" + +/ { + model = "ADP-AIR"; + compatible = "qcom,sa8195p-v2-adp-air", "qcom,sa8195p", + "qcom,adp-air"; + qcom,msm-id = <405 0x20000>; + qcom,board-id = <0x02010019 0>; +}; + diff --git a/qcom/sa8195p-v2-adp-air.dts b/qcom/sa8195p-v2-adp-air.dts new file mode 100644 index 000000000000..398606ccb6e2 --- /dev/null +++ b/qcom/sa8195p-v2-adp-air.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sa8195p.dtsi" +#include "sa8195p-adp-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195P V2 ADP AIR"; + compatible = "qcom,sa8195p-v2-adp-air", "qcom,sa8195p", "qcom,adp-air"; + qcom,board-id = <0x02010019 0>; +}; diff --git a/qcom/sa8195p-v2-adp-air.dtsi b/qcom/sa8195p-v2-adp-air.dtsi new file mode 100644 index 000000000000..ec4afde21db4 --- /dev/null +++ b/qcom/sa8195p-v2-adp-air.dtsi @@ -0,0 +1 @@ +#include "sa8195p-adp-common.dtsi" diff --git a/qcom/sa8195p.dts b/qcom/sa8195p.dts new file mode 100644 index 000000000000..baf7d97a3691 --- /dev/null +++ b/qcom/sa8195p.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sa8195p.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195P AU SoC"; + compatible = "qcom,sa8195"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/sa8195p.dtsi b/qcom/sa8195p.dtsi new file mode 100644 index 000000000000..0032ea7d78af --- /dev/null +++ b/qcom/sa8195p.dtsi @@ -0,0 +1,8 @@ +#include "sdmshrike-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195P"; + qcom,msm-name = "SA8195P"; + qcom,msm-id = <405 0x20000>; +}; + diff --git a/qcom/sdmshrike-v2.dts b/qcom/sdmshrike-v2.dts new file mode 100644 index 000000000000..39ff556db0ec --- /dev/null +++ b/qcom/sdmshrike-v2.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sdmshrike-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8195 v2 SoC"; + compatible = "qcom,sa8195"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/sdmshrike-v2.dtsi b/qcom/sdmshrike-v2.dtsi new file mode 100644 index 000000000000..863f841f4398 --- /dev/null +++ b/qcom/sdmshrike-v2.dtsi @@ -0,0 +1,8 @@ + +#include "sdmshrike.dtsi" +/ { + model = "Qualcomm Technologies, Inc. SA8195 V2"; + qcom,msm-name = "SA8195 V2"; + qcom,msm-id = <340 0x20000>; +}; + diff --git a/qcom/sdmshrike.dts b/qcom/sdmshrike.dts new file mode 100644 index 000000000000..7a80770520b2 --- /dev/null +++ b/qcom/sdmshrike.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "sdmshrike.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDMSHRIKE SoC"; + compatible = "qcom,sdmshrike"; + qcom,pmic-name = "PM8150"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi new file mode 100644 index 000000000000..a2722edeb2e9 --- /dev/null +++ b/qcom/sdmshrike.dtsi @@ -0,0 +1,655 @@ +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. SDMSHRIKE"; + compatible = "qcom,sdmshrike"; + qcom,msm-name = "SDMSHRIKE"; + qcom,msm-id = <340 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + aliases { + serial0 = &uart2; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-size = <0x400000>; + cache-level = <3>; + }; + }; + + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_2>; + #cooling-cells = <2>; + L2_2: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_200: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + + L1_D_200: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + cache-size = <0x8000>; + next-level-cache = <&L2_3>; + #cooling-cells = <2>; + L2_3: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x20000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_300: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + + L1_D_300: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0xa000>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + cache-size = <0x20000>; + next-level-cache = <&L2_4>; + #cooling-cells = <2>; + L2_4: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x80000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_400: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + + L1_D_400: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + cache-size = <0x20000>; + next-level-cache = <&L2_5>; + #cooling-cells = <2>; + L2_5: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x80000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_500: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + + L1_D_500: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + cache-size = <0x20000>; + next-level-cache = <&L2_6>; + #cooling-cells = <2>; + L2_6: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x80000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_600: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + + L1_D_600: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1740>; + cache-size = <0x20000>; + next-level-cache = <&L2_7>; + #cooling-cells = <2>; + L2_7: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x80000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_700: l1-icache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + + L1_D_700: l1-dcache { + compatible = "arm,arch-cache"; + qcom,dump-size = <0x14000>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + firmware: firmware { + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp_mem@85700000 { + no-map; + reg = <0x0 0x85700000 0x0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem@85e00000 { + no-map; + reg = <0x0 0x85e00000 0x0 0x140000>; + }; + + flex_sec_apps_mem: flex_sec_apps_regions@85ffd000 { + no-map; + reg = <0x0 0x85ffd000 0x0 0x3000>; + }; + + smem_region: smem@86000000 { + no-map; + reg = <0x0 0x86000000 0x0 0x200000>; + }; + + removed_regions: removed_regions@86200000 { + no-map; + reg = <0x0 0x86200000 0x0 0x5500000>; + }; + + pil_camera_mem: camera_region@8b700000 { + no-map; + reg = <0x0 0x8b700000 0x0 0x500000>; + }; + + pil_wlan_fw_mem: pil_wlan_fw_region@8bc00000 { + no-map; + reg = <0x0 0x8bc00000 0x0 0x180000>; + }; + + pil_npu_mem: pil_npu_region@0x8bd80000 { + no-map; + reg = <0x0 0x8bd80000 0x0 0x80000>; + }; + + pil_adsp_mem: pil_adsp_region@0x8be00000 { + no-map; + reg = <0x0 0x8be00000 0x0 0x1a00000>; + }; + + pil_modem_mem: modem_region@0x8d800000 { + no-map; + reg = <0x0 0x8d800000 0x0 0x9600000>; + }; + + pil_video_mem: pil_video_region@0x96e00000 { + no-map; + reg = <0x0 0x96e00000 0x0 0x500000>; + }; + + pil_slpi_mem: pil_slpi_region@0x97300000 { + no-map; + reg = <0x0 0x97300000 0x0 0x1400000>; + }; + + pil_ipa_fw_mem: pil_ipa_fw_region@0x98700000 { + no-map; + reg = <0x0 0x98700000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: pil_ipa_gsi_region@0x98710000 { + no-map; + reg = <0x0 0x98710000 0x0 0x5000>; + }; + + pil_gpu_mem: pil_gpu_region@0x98715000 { + no-map; + reg = <0x0 0x98715000 0x0 0x2000>; + }; + + pil_spss_mem: pil_spss_region@0x98800000 { + no-map; + reg = <0x0 0x98800000 0x0 0x100000>; + }; + + pil_cdsp_mem: cdsp_regions@0x98900000 { + no-map; + reg = <0x0 0x98900000 0x0 0x1400000>; + }; + + qseecom_mem: qseecom_region@0x9e400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0x0 0x9e400000 0x0 0x1400000>; + }; + + + cont_splash_memory: cont_splash_region@0x9c000000 { + reg = <0x0 0x9c000000 0x0 0x02400000>; + label = "cont_splash_region"; + }; + + disp_rdump_memory: disp_rdump_region@0x9c000000 { + reg = <0x0 0x9c000000 0x0 0x02400000>; + label = "disp_rdump_region"; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + cdsp_mem: cdsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x400000>; + }; + + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + }; + + secure_display_memory: secure_display_region { /* Secure UI */ + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xA000000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x2400000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2800000>; + linux,cma-default; + }; + }; + + vendor: vendor { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + }; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17a60000 0x100000>; /* GICR * 8 */ + interrupts = <1 9 4>; + interrupt-parent = <&intc>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 1 0xf08>, + <1 2 0xf08>, + <1 3 0xf08>, + <1 0 0xf08>; + clock-frequency = <19200000>; + }; + + timer@0x17c20000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17c20000 0x1000>; + clock-frequency = <19200000>; + + frame@0x17c21000 { + frame-number = <0>; + interrupts = <0 7 0x4>, + <0 6 0x4>; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = <0 8 0x4>; + reg = <0x17c23000 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = <0 9 0x4>; + reg = <0x17c25000 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = <0 10 0x4>; + reg = <0x17c26000 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = <0 11 0x4>; + reg = <0x17c29000 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = <0 12 0x4>; + reg = <0x17c2b000 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = <0 13 0x4>; + reg = <0x17c2d000 0x1000>; + status = "disabled"; + }; + }; + + qcom,msm-imem@146bf000 { + compatible = "qcom,msm-imem"; + reg = <0x146bf000 0x1000>; + ranges = <0x0 0x146bf000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + qcom,mpm2-sleep-counter@c221000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0xc221000 0x1000>; + clock-frequency = <32768>; + }; + + apps_rsc: rsc@18200000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x18200000 0x10000>, + <0x18210000 0x10000>, + <0x18220000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x00ac0000 0x6000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + uart2: serial@a90000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00a90000 0x0 0x4000>; + interrupts = ; + status = "ok"; + }; + }; + +}; + From 766b8be48c227cbe8fde02c29add83009a6f6ac2 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Wed, 1 Jul 2020 08:33:50 +0530 Subject: [PATCH 05/66] ARM: dts: msm: Add tlmm pinctrl support for SA8195 Add support for pinctrl node for SA8195 platform. Change-Id: Ie23e29845ecaad9588b32d67ed7d47b9bbcf5062 --- bindings/pinctrl/qcom,sdmshrike-pinctrl.txt | 185 + qcom/sdmshrike-pinctrl.dtsi | 5155 +++++++++++++++++++ qcom/sdmshrike.dtsi | 1 + 3 files changed, 5341 insertions(+) create mode 100644 bindings/pinctrl/qcom,sdmshrike-pinctrl.txt create mode 100644 qcom/sdmshrike-pinctrl.dtsi diff --git a/bindings/pinctrl/qcom,sdmshrike-pinctrl.txt b/bindings/pinctrl/qcom,sdmshrike-pinctrl.txt new file mode 100644 index 000000000000..4fdbfe177a33 --- /dev/null +++ b/bindings/pinctrl/qcom,sdmshrike-pinctrl.txt @@ -0,0 +1,185 @@ +Qualcomm Technologies, Inc. SDMSHRIKE TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +sdmshrike platform. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,sdmshrike-pinctrl" + +- reg: + Usage: required + Value type: + Definition: the base address and size of the north, south, west + and east TLMM tiles. + +- reg-names: + Usage: required + Value type: + Defintiion: names for the cells of reg, must contain "north", "south" + "west" and "east". + +- interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- gpio-ranges: + Usage: required + Value type: + Definition: see ../gpio/gpio.txt + +- gpio-reserved-ranges: + Usage: optional + Value type: + Definition: see ../gpio/gpio.txt + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins are: + gpio0-gpio149 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + + ufs_reset + Supports bias and drive-strength + +- function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + + adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char, + atest_char0, atest_char1, atest_char2, atest_char3, + audio_ref, atest_usb1, atest_usb2, atest_usb10, + atest_usb11, atest_usb12, atest_usb13, atest_usb20, + atest_usb21, atest_usb22, atest_usb2, atest_usb23, + btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0, + cci_timer1, cci_timer2, cci_timer3, cci_timer4, + cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, + ddr_pxi0, ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd, + emac_phy, emac_pps, gcc_gp1, gcc_gp2, gcc_gp3, gpio, + hs1_mi2s, hs2_mi2s, hs3_mi2s, jitter_bist, + lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1, + mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps, + pa_indicator, pci_e0, phase_flag, pll_bypassnl, + pll_bist, pci_e1, pll_reset, pri_mi2s, pri_mi2s_ws, + prng_rosc, qdss, qdss_cti, qlink_request, qlink_enable, + qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qua_mi2s, + qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8, + qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, + qup17, qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii, + sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu, ter_mi2s, + tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, + tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt, + usb2phy_ac, usb_phy, vfr_1, vsense_trigger, wlan1_adc0, + wlan1_adc1, wlan2_adc0, wlan2_adc1, wmss_reset + +- bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configured as no pull. + +- bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull down. + +- bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull up. + +- output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + high. + Not valid for sdc pins. + +- output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + low. + Not valid for sdc pins. + +- drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 + +Example: + + tlmm: pinctrl@3000000 { + compatible = "qcom,sdmshrike-pinctrl"; + reg = <0x03000000 0xddc000>, <0x17c000f0 0x60>; + reg-names = "pinctrl", "spi_cfg"; + interrupts = <0 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/qcom/sdmshrike-pinctrl.dtsi b/qcom/sdmshrike-pinctrl.dtsi new file mode 100644 index 000000000000..e4af602e1c7a --- /dev/null +++ b/qcom/sdmshrike-pinctrl.dtsi @@ -0,0 +1,5155 @@ +&soc { + tlmm: pinctrl@3000000 { + compatible = "qcom,sdmshrike-pinctrl"; + reg = <0x03000000 0xddc000>, <0x17c000f0 0x60>; + reg-names = "pinctrl", "spi_cfg"; + interrupts =; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + ufs_dev_reset_assert: ufs_dev_reset_assert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * UFS_RESET driver strengths are having + * different values/steps compared to typical + * GPIO drive strengths. + * + * Following table clarifies: + * + * HDRV value | UFS_RESET | Typical GPIO + * (dec) | (mA) | (mA) + * 0 | 0.8 | 2 + * 1 | 1.55 | 4 + * 2 | 2.35 | 6 + * 3 | 3.1 | 8 + * 4 | 3.9 | 10 + * 5 | 4.65 | 12 + * 6 | 5.4 | 14 + * 7 | 6.15 | 16 + * + * POR value for UFS_RESET HDRV is 3 which means + * 3.1mA and we want to use that. Hence just + * specify 8mA to "drive-strength" binding and + * that should result into writing 3 to HDRV + * field. + */ + drive-strength = <8>; /* default: 3.1 mA */ + output-low; /* active low reset */ + }; + }; + + ufs_dev_reset_deassert: ufs_dev_reset_deassert { + config { + pins = "ufs_reset"; + bias-pull-down; /* default: pull down */ + /* + * default: 3.1 mA + * check comments under ufs_dev_reset_assert + */ + drive-strength = <8>; + output-high; /* active low reset */ + }; + }; + + ufs0_dev_reset_assert: ufs0_dev_reset_assert { + config { + pins = "ufs0_reset"; + bias-pull-down; /* default: pull down */ + /* + * UFS_RESET driver strengths are having + * different values/steps compared to typical + * GPIO drive strengths. + * + * Following table clarifies: + * + * HDRV value | UFS_RESET | Typical GPIO + * (dec) | (mA) | (mA) + * 0 | 0.8 | 2 + * 1 | 1.55 | 4 + * 2 | 2.35 | 6 + * 3 | 3.1 | 8 + * 4 | 3.9 | 10 + * 5 | 4.65 | 12 + * 6 | 5.4 | 14 + * 7 | 6.15 | 16 + * + * POR value for UFS_RESET HDRV is 3 which means + * 3.1mA and we want to use that. Hence just + * specify 8mA to "drive-strength" binding and + * that should result into writing 3 to HDRV + * field. + */ + drive-strength = <8>; /* default: 3.1 mA */ + output-low; /* active low reset */ + }; + }; + + ufs0_dev_reset_deassert: ufs0_dev_reset_deassert { + config { + pins = "ufs0_reset"; + bias-pull-down; /* default: pull down */ + /* + * default: 3.1 mA + * check comments under ufs_dev_reset_assert + */ + drive-strength = <8>; + output-high; /* active low reset */ + }; + }; + + aqt_intr { + aqt_intr_default: aqt_intr_default { + mux { + pins = "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio125"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + wcd9xxx_intr { + wcd_intr_default: wcd_intr_default { + mux { + pins = "gpio123"; + function = "gpio"; + }; + + config { + pins = "gpio123"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + cdc_reset_ctrl { + cdc_reset_sleep: cdc_reset_sleep { + mux { + pins = "gpio143"; + function = "gpio"; + }; + + config { + pins = "gpio143"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_reset_active:cdc_reset_active { + mux { + pins = "gpio143"; + function = "gpio"; + }; + + config { + pins = "gpio143"; + drive-strength = <8>; + bias-pull-down; + output-high; + }; + }; + }; + + sec_aux_pcm { + sec_aux_pcm_sleep: sec_aux_pcm_sleep { + mux { + pins = "gpio126", "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_active: sec_aux_pcm_active { + mux { + pins = "gpio126", "gpio127"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_aux_pcm_din { + sec_aux_pcm_din_sleep: sec_aux_pcm_din_sleep { + mux { + pins = "gpio128"; + function = "gpio"; + }; + + config { + pins = "gpio128"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_din_active: sec_aux_pcm_din_active { + mux { + pins = "gpio128"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio128"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_aux_pcm_dout { + sec_aux_pcm_dout_sleep: sec_aux_pcm_dout_sleep { + mux { + pins = "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio129"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_aux_pcm_dout_active: sec_aux_pcm_dout_active { + mux { + pins = "gpio129"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio129"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_aux_pcm { + tert_aux_pcm_sleep: tert_aux_pcm_sleep { + mux { + pins = "gpio133", "gpio134"; + function = "gpio"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_active: tert_aux_pcm_active { + mux { + pins = "gpio133", "gpio134"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_aux_pcm_din { + tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep { + mux { + pins = "gpio135"; + function = "gpio"; + }; + + config { + pins = "gpio135"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_din_active: tert_aux_pcm_din_active { + mux { + pins = "gpio135"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio135"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_aux_pcm_dout { + tert_aux_pcm_dout_sleep: tert_aux_pcm_dout_sleep { + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_aux_pcm_dout_active: tert_aux_pcm_dout_active { + mux { + pins = "gpio131"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio131"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_aux_pcm { + quat_aux_pcm_sleep: quat_aux_pcm_sleep { + mux { + pins = "gpio137", "gpio138"; + function = "gpio"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_pcm_active: quat_aux_pcm_active { + mux { + pins = "gpio137", "gpio138"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_aux_pcm_din { + quat_aux_pcm_din_sleep: quat_aux_pcm_din_sleep { + mux { + pins = "gpio139"; + function = "gpio"; + }; + + config { + pins = "gpio139"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_pcm_din_active: quat_aux_pcm_din_active { + mux { + pins = "gpio139"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio139"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_aux_pcm_dout { + quat_aux_pcm_dout_sleep: quat_aux_pcm_dout_sleep { + mux { + pins = "gpio140"; + function = "gpio"; + }; + + config { + pins = "gpio140"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_aux_pcm_dout_active: quat_aux_pcm_dout_active { + mux { + pins = "gpio140"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio140"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_aux_pcm_clk { + pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep { + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_clk_active: pri_aux_pcm_clk_active { + mux { + pins = "gpio144"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio144"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_aux_pcm_sync { + pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep { + mux { + pins = "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio145"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_sync_active: pri_aux_pcm_sync_active { + mux { + pins = "gpio145"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio145"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_aux_pcm_din { + pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep { + mux { + pins = "gpio146"; + function = "gpio"; + }; + + config { + pins = "gpio146"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_din_active: pri_aux_pcm_din_active { + mux { + pins = "gpio146"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio146"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_aux_pcm_dout { + pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep { + mux { + pins = "gpio147"; + function = "gpio"; + }; + + config { + pins = "gpio147"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_aux_pcm_dout_active: pri_aux_pcm_dout_active { + mux { + pins = "gpio147"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio147"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_aux_pcm { + quin_aux_pcm_sleep: quin_aux_pcm_sleep { + mux { + pins = "gpio149", "gpio151"; + function = "gpio"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_aux_pcm_active: quin_aux_pcm_active { + mux { + pins = "gpio149", "gpio151"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quin_aux_pcm_din { + quin_aux_pcm_din_sleep: quin_aux_pcm_din_sleep { + mux { + pins = "gpio150"; + function = "gpio"; + }; + + config { + pins = "gpio150"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_aux_pcm_din_active: quin_aux_pcm_din_active { + mux { + pins = "gpio150"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio150"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_aux_pcm_dout { + quin_aux_pcm_dout_sleep: quin_aux_pcm_dout_sleep { + mux { + pins = "gpio152"; + function = "gpio"; + }; + + config { + pins = "gpio152"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_aux_pcm_dout_active: quin_aux_pcm_dout_active { + mux { + pins = "gpio152"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio152"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio8"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio8"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + sec_tdm { + sec_tdm_sleep: sec_tdm_sleep { + mux { + pins = "gpio126", "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_active: sec_tdm_active { + mux { + pins = "gpio126", "gpio127"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_tdm_din { + sec_tdm_din_sleep: sec_tdm_din_sleep { + mux { + pins = "gpio128"; + function = "gpio"; + }; + + config { + pins = "gpio128"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_din_active: sec_tdm_din_active { + mux { + pins = "gpio128"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio128"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_tdm_dout { + sec_tdm_dout_sleep: sec_tdm_dout_sleep { + mux { + pins = "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio129"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_tdm_dout_active: sec_tdm_dout_active { + mux { + pins = "gpio129"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio129"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_tdm { + tert_tdm_sleep: tert_tdm_sleep { + mux { + pins = "gpio133", "gpio134"; + function = "gpio"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_active: tert_tdm_active { + mux { + pins = "gpio133", "gpio134"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_tdm_din { + tert_tdm_din_sleep: tert_tdm_din_sleep { + mux { + pins = "gpio135"; + function = "gpio"; + }; + + config { + pins = "gpio135"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_din_active: tert_tdm_din_active { + mux { + pins = "gpio135"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio135"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_tdm_dout { + tert_tdm_dout_sleep: tert_tdm_dout_sleep { + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_tdm_dout_active: tert_tdm_dout_active { + mux { + pins = "gpio131"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio131"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_tdm { + quat_tdm_sleep: quat_tdm_sleep { + mux { + pins = "gpio137", "gpio138"; + function = "gpio"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_active: quat_tdm_active { + mux { + pins = "gpio137", "gpio138"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_tdm_din { + quat_tdm_din_sleep: quat_tdm_din_sleep { + mux { + pins = "gpio139"; + function = "gpio"; + }; + + config { + pins = "gpio139"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_din_active: quat_tdm_din_active { + mux { + pins = "gpio139"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio139"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_tdm_dout { + quat_tdm_dout_sleep: quat_tdm_dout_sleep { + mux { + pins = "gpio140"; + function = "gpio"; + }; + + config { + pins = "gpio140"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_tdm_dout_active: quat_tdm_dout_active { + mux { + pins = "gpio140"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio140"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_tdm_clk { + pri_tdm_clk_sleep: pri_tdm_clk_sleep { + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_clk_active: pri_tdm_clk_active { + mux { + pins = "gpio144"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio144"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_tdm_sync { + pri_tdm_sync_sleep: pri_tdm_sync_sleep { + mux { + pins = "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio145"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_sync_active: pri_tdm_sync_active { + mux { + pins = "gpio145"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio145"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_tdm_din { + pri_tdm_din_sleep: pri_tdm_din_sleep { + mux { + pins = "gpio146"; + function = "gpio"; + }; + + config { + pins = "gpio146"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_din_active: pri_tdm_din_active { + mux { + pins = "gpio146"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio146"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_tdm_dout { + pri_tdm_dout_sleep: pri_tdm_dout_sleep { + mux { + pins = "gpio147"; + function = "gpio"; + }; + + config { + pins = "gpio147"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_tdm_dout_active: pri_tdm_dout_active { + mux { + pins = "gpio147"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio147"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_tdm { + quin_tdm_sleep: quin_tdm_sleep { + mux { + pins = "gpio149", "gpio151"; + function = "gpio"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_tdm_active: quin_tdm_active { + mux { + pins = "gpio149", "gpio151"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quin_tdm_din { + quin_tdm_din_sleep: quin_tdm_din_sleep { + mux { + pins = "gpio150"; + function = "gpio"; + }; + + config { + pins = "gpio150"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_tdm_din_active: quin_tdm_din_active { + mux { + pins = "gpio150"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio150"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_tdm_dout { + quin_tdm_dout_sleep: quin_tdm_dout_sleep { + mux { + pins = "gpio152"; + function = "gpio"; + }; + + config { + pins = "gpio152"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_tdm_dout_active: quin_tdm_dout_active { + mux { + pins = "gpio152"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio152"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_mclk { + sec_mi2s_mclk_sleep: sec_mi2s_mclk_sleep { + mux { + pins = "gpio130"; + function = "gpio"; + }; + + config { + pins = "gpio130"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_mclk_active: sec_mi2s_mclk_active { + mux { + pins = "gpio130"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio130"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s { + sec_mi2s_sleep: sec_mi2s_sleep { + mux { + pins = "gpio126", "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO PULL */ + input-enable; + }; + }; + + sec_mi2s_active: sec_mi2s_active { + mux { + pins = "gpio126", "gpio127"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_sd0 { + sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep { + mux { + pins = "gpio128"; + function = "gpio"; + }; + + config { + pins = "gpio128"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd0_active: sec_mi2s_sd0_active { + mux { + pins = "gpio128"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio128"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + sec_mi2s_sd1 { + sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep { + mux { + pins = "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio129"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_mi2s_sd1_active: sec_mi2s_sd1_active { + mux { + pins = "gpio129"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio129"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_mclk { + tert_mi2s_mclk_sleep: tert_mi2s_mclk_sleep { + mux { + pins = "gpio132"; + function = "gpio"; + }; + + config { + pins = "gpio132"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_mclk_active: tert_mi2s_mclk_active { + mux { + pins = "gpio132"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio132"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s { + tert_mi2s_sleep: tert_mi2s_sleep { + mux { + pins = "gpio133", "gpio134"; + function = "gpio"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_active: tert_mi2s_active { + mux { + pins = "gpio133", "gpio134"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio133", "gpio134"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + tert_mi2s_sd0 { + tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep { + mux { + pins = "gpio135"; + function = "gpio"; + }; + + config { + pins = "gpio135"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_sd0_active: tert_mi2s_sd0_active { + mux { + pins = "gpio135"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio135"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + tert_mi2s_sd1 { + tert_mi2s_sd1_sleep: tert_mi2s_sd1_sleep { + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + tert_mi2s_sd1_active: tert_mi2s_sd1_active { + mux { + pins = "gpio131"; + function = "ter_mi2s"; + }; + + config { + pins = "gpio131"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_mclk { + quat_mi2s_mclk_sleep: quat_mi2s_mclk_sleep { + mux { + pins = "gpio136"; + function = "gpio"; + }; + + config { + pins = "gpio136"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_mclk_active: quat_mi2s_mclk_active { + mux { + pins = "gpio136"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio136"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s { + quat_mi2s_sleep: quat_mi2s_sleep { + mux { + pins = "gpio137", "gpio138"; + function = "gpio"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_active: quat_mi2s_active { + mux { + pins = "gpio137", "gpio138"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio137", "gpio138"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quat_mi2s_sd0 { + quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { + mux { + pins = "gpio139"; + function = "gpio"; + }; + + config { + pins = "gpio139"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd0_active: quat_mi2s_sd0_active { + mux { + pins = "gpio139"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio139"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_sd1 { + quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { + mux { + pins = "gpio140"; + function = "gpio"; + }; + + config { + pins = "gpio140"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd1_active: quat_mi2s_sd1_active { + mux { + pins = "gpio140"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio140"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_sd2 { + quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { + mux { + pins = "gpio141"; + function = "gpio"; + }; + + config { + pins = "gpio141"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd2_active: quat_mi2s_sd2_active { + mux { + pins = "gpio141"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio141"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quat_mi2s_sd3 { + quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { + mux { + pins = "gpio142"; + function = "gpio"; + }; + + config { + pins = "gpio142"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quat_mi2s_sd3_active: quat_mi2s_sd3_active { + mux { + pins = "gpio142"; + function = "qua_mi2s"; + }; + + config { + pins = "gpio142"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_mi2s_mclk { + pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep { + mux { + pins = "gpio143"; + function = "gpio"; + }; + + config { + pins = "gpio143"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_mclk_active: pri_mi2s_mclk_active { + mux { + pins = "gpio143"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio143"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sck { + pri_mi2s_sck_sleep: pri_mi2s_sck_sleep { + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sck_active: pri_mi2s_sck_active { + mux { + pins = "gpio144"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio144"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_ws { + pri_mi2s_ws_sleep: pri_mi2s_ws_sleep { + mux { + pins = "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio145"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_ws_active: pri_mi2s_ws_active { + mux { + pins = "gpio145"; + function = "pri_mi2s_ws"; + }; + + config { + pins = "gpio145"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + pri_mi2s_sd0 { + pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep { + mux { + pins = "gpio146"; + function = "gpio"; + }; + + config { + pins = "gpio146"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd0_active: pri_mi2s_sd0_active { + mux { + pins = "gpio146"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio146"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pri_mi2s_sd1 { + pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep { + mux { + pins = "gpio147"; + function = "gpio"; + }; + + config { + pins = "gpio147"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_mi2s_sd1_active: pri_mi2s_sd1_active { + mux { + pins = "gpio147"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio147"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_mi2s_mclk { + quin_mi2s_mclk_sleep: quin_mi2s_mclk_sleep { + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + quin_mi2s_mclk_active: quin_mi2s_mclk_active { + mux { + pins = "gpio148"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio148"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_mi2s { + quin_mi2s_sleep: quin_mi2s_sleep { + mux { + pins = "gpio149", "gpio151"; + function = "gpio"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_mi2s_active: quin_mi2s_active { + mux { + pins = "gpio149", "gpio151"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio149", "gpio151"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + quin_mi2s_sd0 { + quin_mi2s_sd0_sleep: quin_mi2s_sd0_sleep { + mux { + pins = "gpio150"; + function = "gpio"; + }; + + config { + pins = "gpio150"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_mi2s_sd0_active: quin_mi2s_sd0_active { + mux { + pins = "gpio150"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio150"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + quin_mi2s_sd1 { + quin_mi2s_sd1_sleep: quin_mi2s_sd1_sleep { + mux { + pins = "gpio152"; + function = "gpio"; + }; + + config { + pins = "gpio152"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + quin_mi2s_sd1_active: quin_mi2s_sd1_active { + mux { + pins = "gpio152"; + function = "spkr_i2s"; + }; + + config { + pins = "gpio152"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + /* add pins for DisplayPort */ + sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-disable; + drive-strength = <16>; + }; + }; + + sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend { + mux { + pins = "gpio38"; + function = "gpio"; + }; + + config { + pins = "gpio38"; + bias-pull-down; + drive-strength = <2>; + }; + }; + + ap2mdm { + ap2mdm_active: ap2mdm_active { + mux { + /* ap2mdm-status + * ap2mdm-errfatal + * ap2mdm-vddmin + */ + pins = "gpio135", "gpio139"; + function = "gpio"; + }; + + config { + pins = "gpio135", "gpio139"; + drive-strength = <16>; + bias-disable; + }; + }; + + ap2mdm_sleep: ap2mdm_sleep { + mux { + /* ap2mdm-status + * ap2mdm-errfatal + * ap2mdm-vddmin + */ + pins = "gpio135", "gpio139"; + function = "gpio"; + }; + + config { + pins = "gpio135", "gpio139"; + drive-strength = <8>; + bias-disable; + }; + + }; + }; + + mdm2ap { + mdm2ap_active: mdm2ap_active { + mux { + /* mdm2ap-status + * mdm2ap-errfatal + * mdm2ap-vddmin + */ + pins = "gpio81", "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio81", "gpio53"; + drive-strength = <8>; + bias-disable; + }; + }; + + mdm2ap_sleep: mdm2ap_sleep { + mux { + /* mdm2ap-status + * mdm2ap-errfatal + * mdm2ap-vddmin + */ + pins = "gpio81", "gpio53"; + function = "gpio"; + }; + + config { + pins = "gpio81", "gpio53"; + drive-strength = <8>; + bias-disable; + }; + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor0_active: cam_sensor0_active { + /* intr gpio for bridge chip 0 */ + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + bias-pull-up; /* PULL UP */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor0_suspend: cam_sensor0_suspend { + /* intr gpio for bridge chip 0 */ + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor1_active: cam_sensor1_active { + /* intr gpio for bridge chip 1 */ + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor1_suspend: cam_sensor1_suspend { + /* intr gpio for bridge chip 1 */ + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor2_active: cam_sensor2_active { + /* intr gpio for bridge chip 2 */ + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + bias-pull-up; /* PULL UP */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor2_suspend: cam_sensor2_suspend { + /* intr gpio for bridge chip 2 */ + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor3_active: cam_sensor3_active { + /* intr gpio for bridge chip 3 */ + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + bias-pull-up; /* PULL UP */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor3_suspend: cam_sensor3_suspend { + /* intr gpio for bridge chip 3 */ + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_eldo2_default: cam_sensor_eldo2_default { + /* AVDD ELDO2 */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* NO PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + camera_vaf_en_default: camera_vaf_en_default { + /* VAF ELDO1 */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + camera_vana_en_default: camera_vana_en_default { + /* VANA ELDO2 */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rear: cam_sensor_active_rear { + /* RESET REAR2 */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rear: cam_sensor_suspend_rear { + /* RESET REAR2 */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rear_aux: cam_sensor_active_rear_aux { + /* RESET REARAUX */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rear_aux: cam_sensor_suspend_rear_aux { + /* RESET REARAUX */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_front: cam_sensor_active_front { + /* RESET FRONT */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_front: cam_sensor_suspend_front { + /* RESET FRONT */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_iris: cam_sensor_active_iris { + /* RESET IRIS */ + mux { + pins = "gpio23", "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_iris: cam_sensor_suspend_iris { + /* RESET IRIS */ + mux { + pins = "gpio23", "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio26"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_triple_rear: cam_sensor_active_triple_rear { + mux { + pins = "gpio30", "gpio157", "gpio158"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio157", "gpio158"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_triple_rear: cam_sensor_suspend_triple_rear { + mux { + pins = "gpio30", "gpio157", "gpio158"; + function = "gpio"; + }; + + config { + pins = "gpio30", "gpio157", "gpio158"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_triple_rear_aux: + cam_sensor_active_triple_rear_aux { + mux { + pins = "gpio23", "gpio159", "gpio160"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio159", "gpio160"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_triple_rear_aux: + cam_sensor_suspend_triple_rear_aux { + mux { + pins = "gpio23", "gpio159", "gpio160"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio159", "gpio160"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_triple_rear_aux2: + cam_sensor_active_triple_rear_aux2 { + mux { + pins = "gpio28", "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio24", "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_triple_rear_aux2: + cam_sensor_suspend_triple_rear_aux2 { + mux { + pins = "gpio28", "gpio24", "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio28", "gpio24", "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio17","gpio18"; // Only 2 + function = "cci_i2c"; + }; + + config { + pins = "gpio17","gpio18"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio17","gpio18"; + function = "cci_i2c"; + }; + + config { + pins = "gpio17","gpio18"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio19","gpio20"; + function = "cci_i2c"; + }; + + config { + pins = "gpio19","gpio20"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio19","gpio20"; + function = "cci_i2c"; + }; + + config { + pins = "gpio19","gpio20"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_active: cci2_active { + mux { + /* CLK, DATA */ + pins = "gpio31","gpio32"; + function = "cci_i2c"; + }; + + config { + pins = "gpio31","gpio32"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_suspend: cci2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio31","gpio32"; + function = "cci_i2c"; + }; + + config { + pins = "gpio31","gpio32"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_active: cci3_active { + mux { + /* CLK, DATA */ + pins = "gpio33","gpio34"; + function = "cci_i2c"; + }; + + config { + pins = "gpio33","gpio34"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_suspend: cci3_suspend { + mux { + /* CLK, DATA */ + pins = "gpio33","gpio34"; + function = "cci_i2c"; + }; + + config { + pins = "gpio33","gpio34"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci4_active: cci4_active { + mux { + /* CLK, DATA */ + pins = "gpio0","gpio1"; + function = "cci_i2c"; + }; + + config { + pins = "gpio0","gpio1"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci4_suspend: cci4_suspend { + mux { + /* CLK, DATA */ + pins = "gpio0","gpio1"; + function = "cci_i2c"; + }; + + config { + pins = "gpio0","gpio1"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci5_active: cci5_active { + mux { + /* CLK, DATA */ + pins = "gpio2","gpio3"; + function = "cci_i2c"; + }; + + config { + pins = "gpio2","gpio3"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci5_suspend: cci5_suspend { + mux { + /* CLK, DATA */ + pins = "gpio2","gpio3"; + function = "cci_i2c"; + }; + + config { + pins = "gpio2","gpio3"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci6_active: cci6_active { + mux { + /* CLK, DATA */ + pins = "gpio39","gpio40"; + function = "cci_i2c"; + }; + + config { + pins = "gpio39","gpio40"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci6_suspend: cci6_suspend { + mux { + /* CLK, DATA */ + pins = "gpio39","gpio40"; + function = "cci_i2c"; + }; + + config { + pins = "gpio39","gpio40"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci7_active: cci7_active { + mux { + /* CLK, DATA */ + pins = "gpio41","gpio42"; + function = "cci_i2c"; + }; + + config { + pins = "gpio41","gpio42"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci7_suspend: cci7_suspend { + mux { + /* CLK, DATA */ + pins = "gpio41","gpio42"; + function = "cci_i2c"; + }; + + config { + pins = "gpio41","gpio42"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + fsa_usbc_ana_en_n@100 { + fsa_usbc_ana_en: fsa_usbc_ana_en { + mux { + pins = "gpio100"; + function = "gpio"; + }; + + config { + pins = "gpio100"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + }; + + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_on: cd_on { + mux { + pins = "gpio96"; /* sdcard_det */ + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_cd_off: cd_off { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie0 { + pcie0_clkreq_default: pcie0_clkreq_default { + mux { + pins = "gpio36"; + function = "pci_e0"; + }; + + config { + pins = "gpio36"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie0_perst_default: pcie0_perst_default { + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie0_wake_default: pcie0_wake_default { + mux { + pins = "gpio37"; + function = "gpio"; + }; + + config { + pins = "gpio37"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie1 { + pcie1_clkreq_default: pcie1_clkreq_default { + mux { + pins = "gpio103"; + function = "pci_e1"; + }; + + config { + pins = "gpio103"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_perst_default: pcie1_perst_default { + mux { + pins = "gpio175"; + function = "gpio"; + }; + + config { + pins = "gpio175"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie1_wake_default: pcie1_wake_default { + mux { + pins = "gpio177"; + function = "gpio"; + }; + + config { + pins = "gpio177"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie2 { + pcie2_clkreq_default: pcie2_clkreq_default { + mux { + pins = "gpio176"; + function = "pci_e2"; + }; + + config { + pins = "gpio176"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie2_perst_default: pcie2_perst_default { + mux { + pins = "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio102"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie2_wake_default: pcie2_wake_default { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie3 { + pcie3_clkreq_default: pcie3_clkreq_default { + mux { + pins = "gpio179"; + function = "pci_e3"; + }; + + config { + pins = "gpio179"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie3_perst_default: pcie3_perst_default { + mux { + pins = "gpio178"; + function = "gpio"; + }; + + config { + pins = "gpio178"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie3_wake_default: pcie3_wake_default { + mux { + pins = "gpio56"; + function = "gpio"; + }; + + config { + pins = "gpio56"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + pcie_ep { + pcie_ep_clkreq_default: pcie_ep_clkreq_default { + mux { + pins = "gpio176"; + function = "pci_e1"; + }; + + config { + pins = "gpio176"; + drive-strength = <2>; + bias-disable; + }; + }; + + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio102"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio104"; + function = "gpio"; + }; + + config { + pins = "gpio104"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + hs1_i2s_mclk { + hs1_i2s_mclk_sleep: hs1_i2s_mclk_sleep { + mux { + pins = "gpio155"; + function = "gpio"; + }; + + config { + pins = "gpio155"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs1_i2s_mclk_active: hs1_i2s_mclk_active { + mux { + pins = "gpio155"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio155"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs1_i2s_sck { + hs1_i2s_sck_sleep: hs1_i2s_sck_sleep { + mux { + pins = "gpio156"; + function = "gpio"; + }; + + config { + pins = "gpio156"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs1_i2s_sck_active: hs1_i2s_sck_active { + mux { + pins = "gpio156"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio156"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs1_i2s_ws { + hs1_i2s_ws_sleep: hs1_i2s_ws_sleep { + mux { + pins = "gpio157"; + function = "gpio"; + }; + + config { + pins = "gpio157"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs1_i2s_ws_active: hs1_i2s_ws_active { + mux { + pins = "gpio157"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio157"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs1_i2s_data0 { + hs1_i2s_data0_sleep: hs1_i2s_data0_sleep { + mux { + pins = "gpio158"; + function = "sleep"; + }; + + config { + pins = "gpio158"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs1_i2s_data0_active: hs1_i2s_data0_active { + mux { + pins = "gpio158"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio158"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs1_i2s_data1 { + hs1_i2s_data1_sleep: hs1_i2s_data1_sleep { + mux { + pins = "gpio159"; + function = "gpio"; + }; + + config { + pins = "gpio159"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs1_i2s_data1_active: hs1_i2s_data1_active { + mux { + pins = "gpio159"; + function = "hs1_mi2s"; + }; + + config { + pins = "gpio159"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + input-enable; + }; + }; + }; + + hs2_i2s_mclk { + hs2_i2s_mclk_sleep: hs2_i2s_mclk_sleep { + mux { + pins = "gpio160"; + function = "gpio"; + }; + + config { + pins = "gpio160"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs2_i2s_mclk_active: hs2_i2s_mclk_active { + mux { + pins = "gpio160"; + function = "hs2_mi2s"; + }; + + config { + pins = "gpio160"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs2_i2s_sck { + hs2_i2s_sck_sleep: hs2_i2s_sck_sleep { + mux { + pins = "gpio161"; + function = "gpio"; + }; + + config { + pins = "gpio161"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs2_i2s_sck_active: hs2_i2s_sck_active { + mux { + pins = "gpio161"; + function = "hs2_mi2s"; + }; + + config { + pins = "gpio161"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs2_i2s_ws { + hs2_i2s_ws_sleep: hs2_i2s_ws_sleep { + mux { + pins = "gpio162"; + function = "gpio"; + }; + + config { + pins = "gpio162"; + drive-strength = <2>; /* 8 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs2_i2s_ws_active: hs2_i2s_ws_active { + mux { + pins = "gpio162"; + function = "hs2_mi2s"; + }; + + config { + pins = "gpio162"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs2_i2s_data0 { + hs2_i2s_data0_sleep: hs2_i2s_data0_sleep { + mux { + pins = "gpio163"; + function = "gpio"; + }; + + config { + pins = "gpio163"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs2_i2s_data0_active: hs2_i2s_data0_active { + mux { + pins = "gpio163"; + function = "hs2_mi2s"; + }; + + config { + pins = "gpio163"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs2_i2s_data1 { + hs2_i2s_data1_sleep: hs2_i2s_data1_sleep { + mux { + pins = "gpio164"; + function = "gpio"; + }; + + config { + pins = "gpio164"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs2_i2s_data1_active: hs2_i2s_data1_active { + mux { + pins = "gpio164"; + function = "hs2_mi2s"; + }; + + config { + pins = "gpio164"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + input-enable; + }; + }; + }; + + hs3_i2s_mclk { + hs3_i2s_mclk_sleep: hs3_i2s_mclk_sleep { + mux { + pins = "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio125"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs3_i2s_mclk_active: hs3_i2s_mclk_active { + mux { + pins = "gpio125"; + function = "hs3_mi2s"; + }; + + config { + pins = "gpio125"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs3_i2s_sck { + hs3_i2s_sck_sleep: hs3_i2s_sck_sleep { + mux { + pins = "gpio165"; + function = "gpio"; + }; + + config { + pins = "gpio165"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs3_i2s_sck_active: hs3_i2s_sck_active { + mux { + pins = "gpio165"; + function = "hs3_mi2s"; + }; + + config { + pins = "gpio165"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs3_i2s_ws { + hs3_i2s_ws_sleep: hs3_i2s_ws_sleep { + mux { + pins = "gpio166"; + function = "gpio"; + }; + + config { + pins = "gpio166"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs3_i2s_ws_active: hs3_i2s_ws_active { + mux { + pins = "gpio166"; + function = "hs3_mi2s"; + }; + + config { + pins = "gpio166"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs3_i2s_data0 { + hs3_i2s_data0_sleep: hs3_i2s_data0_sleep { + mux { + pins = "gpio167"; + function = "gpio"; + }; + + config { + pins = "gpio167"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs3_i2s_data0_active: hs3_i2s_data0_active { + mux { + pins = "gpio167"; + function = "hs3_mi2s"; + }; + + config { + pins = "gpio167"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + output-high; + }; + }; + }; + + hs3_i2s_data1 { + hs3_i2s_data1_sleep: hs3_i2s_data1_sleep { + mux { + pins = "gpio168"; + function = "gpio"; + }; + + config { + pins = "gpio168"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + hs3_i2s_data1_active: hs3_i2s_data1_active { + mux { + pins = "gpio168"; + function = "hs3_mi2s"; + }; + + config { + pins = "gpio168"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + input-enable; + }; + }; + }; + + emac { + emac_mdc: emac_mdc { + mux { + pins = "gpio7"; + function = "rgmii_mdc"; + }; + + config { + pins = "gpio7"; + bias-pull-up; + }; + }; + + emac_mdio: emac_mdio { + mux { + pins = "gpio59"; + function = "rgmii_mdio"; + }; + + config { + pins = "gpio59"; + bias-pull-up; + }; + }; + + emac_rgmii_txd0: emac_rgmii_txd0 { + mux { + pins = "gpio122"; + function = "rgmii_txd0"; + }; + + config { + pins = "gpio122"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txd1: emac_rgmii_txd1 { + mux { + pins = "gpio4"; + function = "rgmii_txd1"; + }; + + config { + pins = "gpio4"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txd2: emac_rgmii_txd2 { + mux { + pins = "gpio5"; + function = "rgmii_txd2"; + }; + + config { + pins = "gpio5"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txd3: emac_rgmii_txd3 { + mux { + pins = "gpio6"; + function = "rgmii_txd3"; + }; + + config { + pins = "gpio6"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_txc: emac_rgmii_txc { + mux { + pins = "gpio114"; + function = "rgmii_txc"; + }; + + config { + pins = "gpio114"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_tx_ctl: emac_rgmii_tx_ctl { + mux { + pins = "gpio121"; + function = "rgmii_tx"; + }; + + config { + pins = "gpio121"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_rgmii_rxd0: emac_rgmii_rxd0 { + mux { + pins = "gpio117"; + function = "rgmii_rxd0"; + }; + + config { + pins = "gpio117"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2MA */ + }; + }; + + emac_rgmii_rxd1: emac_rgmii_rxd1 { + mux { + pins = "gpio118"; + function = "rgmii_rxd1"; + }; + + config { + pins = "gpio118"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_rgmii_rxd2: emac_rgmii_rxd2 { + mux { + pins = "gpio119"; + function = "rgmii_rxd2"; + }; + + config { + pins = "gpio119"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_rgmii_rxd3: emac_rgmii_rxd3 { + mux { + pins = "gpio120"; + function = "rgmii_rxd3"; + }; + + config { + pins = "gpio120"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_rgmii_rxc: emac_rgmii_rxc { + mux { + pins = "gpio115"; + function = "rgmii_rxc"; + }; + + config { + pins = "gpio115"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_rgmii_rx_ctl: emac_rgmii_rx_ctl { + mux { + pins = "gpio116"; + function = "rgmii_rx"; + }; + + config { + pins = "gpio116"; + bias-disable; /* NO pull */ + drive-strength = <2>; + }; + }; + + emac_phy_intr: emac_phy_intr { + mux { + pins = "gpio124"; + function = "emac_phy"; + }; + + config { + pins = "gpio124"; + bias-disable; /* NO pull */ + drive-strength = <8>; + }; + }; + + emac_phy_reset_state: emac_phy_reset_state { + mux { + pins = "gpio79"; + function = "gpio"; + }; + + config { + pins = "gpio79"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + emac_pin_pps_0: emac_pin_pps_0 { + mux { + pins = "gpio81"; + function = "emac_pps"; + }; + + config { + pins = "gpio81"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + }; + + cnss_pins { + cnss_wlan_en_active: cnss_wlan_en_active { + mux { + pins = "gpio169"; + function = "gpio"; + }; + + config { + pins = "gpio169"; + drive-strength = <16>; + output-high; + bias-pull-up; + }; + }; + + cnss_wlan_en_sleep: cnss_wlan_en_sleep { + mux { + pins = "gpio169"; + function = "gpio"; + }; + + config { + pins = "gpio169"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + }; + }; + + usb2phy_ac_en1_default: usb2phy_ac_en1_default { + mux { + pins = "gpio113"; + function = "usb2phy_ac"; + }; + + config { + pins = "gpio113"; + drive-strength = <2>; + bias-disable; + }; + }; + + usb2phy_ac_en2_default: usb2phy_ac_en2_default { + mux { + pins = "gpio123"; + function = "usb2phy_ac"; + }; + + config { + pins = "gpio123"; + drive-strength = <2>; + bias-disable; + }; + }; + + audio_ioexp_reset_active: audio_ioexp_reset_active { + mux { + pins = "gpio166"; + function = "gpio"; + }; + + config { + pins = "gpio166"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + tsif0_signals_active: tsif0_signals_active { + tsif1_clk { + pins = "gpio88"; /* TSIF0 CLK */ + function = "tsif1_clk"; + }; + + tsif1_en { + pins = "gpio89"; /* TSIF0 Enable */ + function = "tsif1_en"; + }; + + tsif1_data { + pins = "gpio90"; /* TSIF0 DATA */ + function = "tsif1_data"; + }; + + signals_cfg { + pins = "gpio88", "gpio89", "gpio90"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + /* sync signal is only used if configured to mode-2 */ + tsif0_sync_active: tsif0_sync_active { + tsif1_sync { + pins = "gpio91"; /* TSIF0 SYNC */ + function = "tsif1_sync"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + tsif1_signals_active: tsif1_signals_active { + tsif2_clk { + pins = "gpio92"; /* TSIF1 CLK */ + function = "tsif2_clk"; + }; + + tsif2_en { + pins = "gpio93"; /* TSIF1 Enable */ + function = "tsif2_en"; + }; + + tsif2_data { + pins = "gpio94"; /* TSIF1 DATA */ + function = "tsif2_data"; + }; + + signals_cfg { + pins = "gpio92", "gpio93", "gpio94"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + /* sync signal is only used if configured to mode-2 */ + tsif1_sync_active: tsif1_sync_active { + tsif2_sync { + pins = "gpio95"; /* TSIF1 SYNC */ + function = "tsif2_sync"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + conn_power_1p8_active: conn_power_1p8_active { + mux { + pins = "gpio173"; + function = "gpio"; + }; + + config { + pins = "gpio173"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + conn_power_pa_active: conn_power_pa_active { + mux { + pins = "gpio174"; + function = "gpio"; + }; + + config { + pins = "gpio174"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + bt_en_active: bt_en_active { + mux { + pins = "gpio172"; + function = "gpio"; + }; + + config { + pins = "gpio172"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + /* SE0 pin mappings */ + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_active: qupv3_se0_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup0"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_active: qupv3_se0_spi_active { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "qup0"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", "gpio2", + "gpio3"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + /* SE 1 pin mappings */ + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_active: qupv3_se1_i2c_active { + mux { + pins = "gpio114", "gpio115"; + function = "qup1"; + }; + + config { + pins = "gpio114", "gpio115"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio114", "gpio115"; + function = "gpio"; + }; + + config { + pins = "gpio114", "gpio115"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_active: qupv3_se1_spi_active { + mux { + pins = "gpio114", "gpio115", "gpio116", + "gpio117"; + function = "qup1"; + }; + + config { + pins = "gpio114", "gpio115", "gpio116", + "gpio117"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio114", "gpio115", "gpio116", + "gpio117"; + function = "gpio"; + }; + + config { + pins = "gpio114", "gpio115", "gpio116", + "gpio117"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 2 pin mappings */ + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio126", "gpio127"; + function = "qup2"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio126", "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio126", "gpio127"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio126", "gpio127", "gpio128", + "gpio129"; + function = "qup2"; + }; + + config { + pins = "gpio126", "gpio127", "gpio128", + "gpio129"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio126", "gpio127", "gpio128", + "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio126", "gpio127", "gpio128", + "gpio129"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 3 pin mappings */ + qupv3_se3_i2c_pins: qupv3_se3_i2c_pins { + qupv3_se3_i2c_active: qupv3_se3_i2c_active { + mux { + pins = "gpio144", "gpio145"; + function = "qup3"; + }; + + config { + pins = "gpio144", "gpio145"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep { + mux { + pins = "gpio144", "gpio145"; + function = "gpio"; + }; + + config { + pins = "gpio144", "gpio145"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se3_spi_pins: qupv3_se3_spi_pins { + qupv3_se3_spi_active: qupv3_se3_spi_active { + mux { + pins = "gpio144", "gpio145", "gpio146", + "gpio147"; + function = "qup3"; + }; + + config { + pins = "gpio144", "gpio145", "gpio146", + "gpio147"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se3_spi_sleep: qupv3_se3_spi_sleep { + mux { + pins = "gpio144", "gpio145", "gpio146", + "gpio147"; + function = "qup3"; + }; + + config { + pins = "gpio144", "gpio145", "gpio146", + "gpio147"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 4 pin mappings */ + qupv3_se4_i2c_pins: qupv3_se4_i2c_pins { + qupv3_se4_i2c_active: qupv3_se4_i2c_active { + mux { + pins = "gpio51", "gpio52"; + function = "qup4"; + }; + + config { + pins = "gpio51", "gpio52"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep { + mux { + pins = "gpio51", "gpio52"; + function = "gpio"; + }; + + config { + pins = "gpio51", "gpio52"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se4_spi_pins: qupv3_se4_spi_pins { + qupv3_se4_spi_active: qupv3_se4_spi_active { + mux { + pins = "gpio51", "gpio52", "gpio53", + "gpio54"; + function = "qup4"; + }; + + config { + pins = "gpio51", "gpio52", "gpio53", + "gpio54"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se4_spi_sleep: qupv3_se4_spi_sleep { + mux { + pins = "gpio51", "gpio52", "gpio53", + "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio51", "gpio52", "gpio53", + "gpio54"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 5 pin mappings */ + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_active: qupv3_se5_i2c_active { + mux { + pins = "gpio121", "gpio122"; + function = "qup5"; + }; + + config { + pins = "gpio121", "gpio122"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio121", "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio121", "gpio122"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se5_spi_pins: qupv3_se5_spi_pins { + qupv3_se5_spi_active: qupv3_se5_spi_active { + mux { + pins = "gpio119", "gpio120", "gpio121", + "gpio122"; + function = "qup5"; + }; + + config { + pins = "gpio119", "gpio120", "gpio121", + "gpio122"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { + mux { + pins = "gpio119", "gpio120", "gpio121", + "gpio122"; + function = "gpio"; + }; + + config { + pins = "gpio119", "gpio120", "gpio121", + "gpio122"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 6 pin mappings */ + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_active: qupv3_se6_i2c_active { + mux { + pins = "gpio6", "gpio7"; + function = "qup6"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_active: qupv3_se6_spi_active { + mux { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + function = "qup6"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", "gpio6", + "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 7 pin mappings */ + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_active: qupv3_se7_i2c_active { + mux { + pins = "gpio98", "gpio99"; + function = "qup7"; + }; + + config { + pins = "gpio98", "gpio99"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio98", "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio98", "gpio99"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se7_spi_pins: qupv3_se7_spi_pins { + qupv3_se7_spi_active: qupv3_se7_spi_active { + mux { + pins = "gpio98", "gpio99", "gpio100", + "gpio101"; + function = "qup7"; + }; + + config { + pins = "gpio98", "gpio99", "gpio100", + "gpio101"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se7_spi_sleep: qupv3_se7_spi_sleep { + mux { + pins = "gpio98", "gpio99", "gpio100", + "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio98", "gpio99", "gpio100", + "gpio101"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* QUPv3 East instances */ + /* SE 8 pin mappings */ + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_active: qupv3_se8_i2c_active { + mux { + pins = "gpio88", "gpio89"; + function = "qup8"; + }; + + config { + pins = "gpio88", "gpio89"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio88", "gpio89"; + function = "gpio"; + }; + + config { + pins = "gpio88", "gpio89"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se8_spi_pins: qupv3_se8_spi_pins { + qupv3_se8_spi_active: qupv3_se8_spi_active { + mux { + pins = "gpio88", "gpio89", "gpio90", + "gpio91"; + function = "qup8"; + }; + + config { + pins = "gpio88", "gpio89", "gpio90", + "gpio91"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se8_spi_sleep: qupv3_se8_spi_sleep { + mux { + pins = "gpio88", "gpio89", "gpio90", + "gpio91"; + function = "gpio"; + }; + + config { + pins = "gpio88", "gpio89", "gpio90", + "gpio91"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 9 pin mappings */ + qupv3_se9_i2c_pins: qupv3_se9_i2c_pins { + qupv3_se9_i2c_active: qupv3_se9_i2c_active { + mux { + pins = "gpio39", "gpio40"; + function = "qup9"; + }; + + config { + pins = "gpio39", "gpio40"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep { + mux { + pins = "gpio39", "gpio40"; + function = "gpio"; + }; + + config { + pins = "gpio39", "gpio40"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se9_spi_pins: qupv3_se9_spi_pins { + qupv3_se9_spi_active: qupv3_se9_spi_active { + mux { + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; + function = "qup9"; + }; + + config { + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se9_spi_sleep: qupv3_se9_spi_sleep { + mux { + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio39", "gpio40", "gpio41", + "gpio42"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 10 pin mappings */ + qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { + qupv3_se10_i2c_active: qupv3_se10_i2c_active { + mux { + pins = "gpio9", "gpio10"; + function = "qup10"; + }; + + config { + pins = "gpio9", "gpio10"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { + mux { + pins = "gpio9", "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio9", "gpio10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se10_spi_pins: qupv3_se10_spi_pins { + qupv3_se10_spi_active: qupv3_se10_spi_active { + mux { + pins = "gpio9", "gpio10", "gpio11", + "gpio12"; + function = "qup10"; + }; + + config { + pins = "gpio9", "gpio10", "gpio11", + "gpio12"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se10_spi_sleep: qupv3_se10_spi_sleep { + mux { + pins = "gpio9", "gpio10", "gpio11", + "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio9", "gpio10", "gpio11", + "gpio12"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 11 pin mappings */ + qupv3_se11_i2c_pins: qupv3_se11_i2c_pins { + qupv3_se11_i2c_active: qupv3_se11_i2c_active { + mux { + pins = "gpio94", "gpio95"; + function = "qup11"; + }; + + config { + pins = "gpio94", "gpio95"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep { + mux { + pins = "gpio94", "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio94", "gpio95"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se11_spi_pins: qupv3_se11_spi_pins { + qupv3_se11_spi_active: qupv3_se11_spi_active { + mux { + pins = "gpio92", "gpio93", "gpio94", + "gpio95"; + function = "qup11"; + }; + + config { + pins = "gpio92", "gpio93", "gpio94", + "gpio95"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se11_spi_sleep: qupv3_se11_spi_sleep { + mux { + pins = "gpio92", "gpio93", "gpio94", + "gpio95"; + function = "gpio"; + }; + + config { + pins = "gpio92", "gpio93", "gpio94", + "gpio95"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 12 pin mappings */ + qupv3_se12_i2c_pins: qupv3_se12_i2c_pins { + qupv3_se12_i2c_active: qupv3_se12_i2c_active { + mux { + pins = "gpio83", "gpio84"; + function = "qup12"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep { + mux { + pins = "gpio83", "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se12_spi_pins: qupv3_se12_spi_pins { + qupv3_se12_spi_active: qupv3_se12_spi_active { + mux { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + function = "qup12"; + }; + + config { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se12_spi_sleep: qupv3_se12_spi_sleep { + mux { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 13 pin mappings */ + qupv3_se13_i2c_pins: qupv3_se13_i2c_pins { + qupv3_se13_i2c_active: qupv3_se13_i2c_active { + mux { + pins = "gpio43", "gpio44"; + function = "qup13"; + }; + + config { + pins = "gpio43", "gpio44"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep { + mux { + pins = "gpio43", "gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio43", "gpio44"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se13_spi_pins: qupv3_se13_spi_pins { + qupv3_se13_spi_active: qupv3_se13_spi_active { + mux { + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; + function = "qup13"; + }; + + config { + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se13_spi_sleep: qupv3_se13_spi_sleep { + mux { + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; + function = "gpio"; + }; + + config { + pins = "gpio43", "gpio44", "gpio45", + "gpio46"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + + /* SE 14 pin mappings */ + qupv3_se14_i2c_pins: qupv3_se14_i2c_pins { + qupv3_se14_i2c_active: qupv3_se14_i2c_active { + mux { + pins = "gpio47", "gpio48"; + function = "qup14"; + }; + + config { + pins = "gpio47", "gpio48"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep { + mux { + pins = "gpio47", "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio47", "gpio48"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se14_spi_pins: qupv3_se14_spi_pins { + qupv3_se14_spi_active: qupv3_se14_spi_active { + mux { + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; + function = "qup14"; + }; + + config { + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se14_spi_sleep: qupv3_se14_spi_sleep { + mux { + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio47", "gpio48", "gpio49", + "gpio50"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 15 pin mappings */ + qupv3_se15_i2c_pins: qupv3_se15_i2c_pins { + qupv3_se15_i2c_active: qupv3_se15_i2c_active { + mux { + pins = "gpio27", "gpio28"; + function = "qup15"; + }; + + config { + pins = "gpio27", "gpio28"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep { + mux { + pins = "gpio27", "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio27", "gpio28"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se15_spi_pins: qupv3_se15_spi_pins { + qupv3_se15_spi_active: qupv3_se15_spi_active { + mux { + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; + function = "qup15"; + }; + + config { + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se15_spi_sleep: qupv3_se15_spi_sleep { + mux { + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio27", "gpio28", "gpio29", + "gpio30"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 16 pin mappings */ + qupv3_se16_i2c_pins: qupv3_se16_i2c_pins { + qupv3_se16_i2c_active: qupv3_se16_i2c_active { + mux { + pins = "gpio86", "gpio85"; + function = "qup16"; + }; + + config { + pins = "gpio86", "gpio85"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se16_i2c_sleep: qupv3_se16_i2c_sleep { + mux { + pins = "gpio86", "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio86", "gpio85"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se16_spi_pins: qupv3_se16_spi_pins { + qupv3_se16_spi_active: qupv3_se16_spi_active { + mux { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + function = "qup16"; + }; + + config { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se16_spi_sleep: qupv3_se16_spi_sleep { + mux { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio83", "gpio84", "gpio85", + "gpio86"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 17 pin mappings */ + qupv3_se17_i2c_pins: qupv3_se17_i2c_pins { + qupv3_se17_i2c_active: qupv3_se17_i2c_active { + mux { + pins = "gpio55", "gpio56"; + function = "qup17"; + }; + + config { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se17_i2c_sleep: qupv3_se17_i2c_sleep { + mux { + pins = "gpio55", "gpio56"; + function = "gpio"; + }; + + config { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se17_spi_pins: qupv3_se17_spi_pins { + qupv3_se17_spi_active: qupv3_se17_spi_active { + mux { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + function = "qup17"; + }; + + config { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se17_spi_sleep: qupv3_se17_spi_sleep { + mux { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + function = "gpio"; + }; + + config { + pins = "gpio55", "gpio56", "gpio57", + "gpio58"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 18 pin mappings */ + qupv3_se18_i2c_pins: qupv3_se18_i2c_pins { + qupv3_se18_i2c_active: qupv3_se18_i2c_active { + mux { + pins = "gpio23", "gpio24"; + function = "qup18"; + }; + + config { + pins = "gpio23", "gpio24"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se18_i2c_sleep: qupv3_se18_i2c_sleep { + mux { + pins = "gpio23", "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio24"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se18_spi_pins: qupv3_se18_spi_pins { + qupv3_se18_spi_active: qupv3_se18_spi_active { + mux { + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; + function = "qup18"; + }; + + config { + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se18_spi_sleep: qupv3_se18_spi_sleep { + mux { + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio23", "gpio24", "gpio25", + "gpio26"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + /* SE 19 pin mappings */ + qupv3_se19_i2c_pins: qupv3_se19_i2c_pins { + qupv3_se19_i2c_active: qupv3_se19_i2c_active { + mux { + pins = "gpio181", "gpio182"; + function = "qup19"; + }; + + config { + pins = "gpio181", "gpio182"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se19_i2c_sleep: qupv3_se19_i2c_sleep { + mux { + pins = "gpio181", "gpio182"; + function = "gpio"; + }; + + config { + pins = "gpio181", "gpio182"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se19_spi_pins: qupv3_se19_spi_pins { + qupv3_se19_spi_active: qupv3_se19_spi_active { + mux { + pins = "gpio181", "gpio182", "gpio183", + "gpio184"; + function = "qup19"; + }; + + config { + pins = "gpio181", "gpio182", "gpio183", + "gpio184"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se19_spi_sleep: qupv3_se19_spi_sleep { + mux { + pins = "gpio181", "gpio182", "gpio183", + "gpio184"; + function = "gpio"; + }; + + config { + pins = "gpio181", "gpio182", "gpio183", + "gpio184"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + + /* SE12 UART-2wire pin mappings */ + qupv3_se12_2uart_pins: qupv3_se12_2uart_pins { + qupv3_se12_2uart_active: qupv3_se12_2uart_active { + mux { + pins = "gpio85", "gpio86"; + function = "qup12"; + }; + + config { + pins = "gpio85", "gpio86"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se12_2uart_sleep: qupv3_se12_2uart_sleep { + mux { + pins = "gpio85", "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio85", "gpio86"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + trigout_a: trigout_a { + mux { + pins = "gpio141"; + function = "qdss_cti"; + }; + + config { + pins = "gpio141"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* SE 10 pin mappings */ + qupv3_se10_2uart_pins: qupv3_se10_2uart_pins { + qupv3_se10_2uart_active: qupv3_se10_2uart_active { + mux { + pins = "gpio11", "gpio12"; + function = "qup10"; + }; + + config { + pins = "gpio11", "gpio12"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se10_2uart_sleep: qupv3_se10_2uart_sleep { + mux { + pins = "gpio11", "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio11", "gpio12"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se16_2uart_pins: qupv3_se16_2uart_pins { + qupv3_se16_2uart_active: qupv3_se16_2uart_active { + mux { + pins = "gpio83", "gpio84"; + function = "qup16"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se16_2uart_sleep: qupv3_se16_2uart_sleep { + mux { + pins = "gpio83", "gpio84"; + function = "gpio"; + }; + + config { + pins = "gpio83", "gpio84"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + /* SE 13 UART 4-Wire pin mappings */ + qupv3_se13_4uart_pins: qupv3_se13_4uart_pins { + qupv3_se13_default_ctsrtsrx: + qupv3_se13_default_ctsrtsrx { + mux { + pins = "gpio43", "gpio44", "gpio46"; + function = "gpio"; + }; + + config { + pins = "gpio43", "gpio44", "gpio46"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se13_default_tx: qupv3_se13_default_tx { + mux { + pins = "gpio45"; + function = "gpio"; + }; + + config { + pins = "gpio45"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se13_ctsrx: qupv3_se13_ctsrx { + mux { + pins = "gpio43", "gpio46"; + function = "qup13"; + }; + + config { + pins = "gpio43", "gpio46"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se13_rts: qupv3_se13_rts { + mux { + pins = "gpio44"; + function = "qup13"; + }; + + config { + pins = "gpio44"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se13_tx: qupv3_se13_tx { + mux { + pins = "gpio45"; + function = "qup13"; + }; + + config { + pins = "gpio45"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + }; +}; diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index a2722edeb2e9..c1079ca2028a 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -653,3 +653,4 @@ }; +#include "sdmshrike-pinctrl.dtsi" From 677d5936a1bc57aa87b80e827d9475af2624cac5 Mon Sep 17 00:00:00 2001 From: Maria Yu Date: Tue, 13 Oct 2020 09:09:54 +0800 Subject: [PATCH 06/66] ARM: dts: msm: Change the node location for optimise Optimise for boot up time since it will use special node and dt property before unflat and put those in the beginning of the device tree can make it search fast. Change-Id: I2e26f72531c8a3037aa6d6e0973b00d24389335e --- qcom/lahaina.dtsi | 510 +++++++++++++++++++++++----------------------- 1 file changed, 256 insertions(+), 254 deletions(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index c57b755b6524..b9827601ded2 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -32,7 +32,13 @@ #address-cells = <2>; #size-cells = <2>; + + chosen { + bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x98c000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + }; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + reserved_memory: reserved-memory { }; mem-offline { compatible = "qcom,mem-offline"; @@ -289,264 +295,260 @@ }; }; }; +}; - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; +&reserved_memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; - hyp_mem: hyp_region@80000000 { - no-map; - reg = <0x0 0x80000000 0x0 0x600000>; - }; - - xbl_aop_mem: xbl_aop_region@80700000 { - no-map; - reg = <0x0 0x80700000 0x0 0x160000>; - }; - - cmd_db: reserved-memory@80860000 { - compatible = "qcom,cmd-db"; - no-map; - reg = <0x0 0x80860000 0x0 0x20000>; - }; - - reserved_xbl_uefi_log: res_xbl_uefi_log_region@80880000 { - no-map; - reg = <0x0 0x80880000 0x0 0x14000>; - }; - - smem_mem: smem_region@80900000 { - no-map; - reg = <0x0 0x80900000 0x0 0x200000>; - }; - - cpucp_fw_mem: cpucp_fw_region@80b00000 { - no-map; - reg = <0x0 0x80b00000 0x0 0x100000>; - }; - - cdsp_secure_heap: cdsp_secure_heap@80c00000 { - no-map; - reg = <0x0 0x80c00000 0x0 0x4600000>; - }; - - pil_camera_mem: pil_camera_region@85200000 { - no-map; - reg = <0x0 0x85200000 0x0 0x500000>; - }; - - pil_video_mem: pil_video_region@85700000 { - no-map; - reg = <0x0 0x85700000 0x0 0x500000>; - }; - - pil_cvp_mem: pil_cvp_region@85c00000 { - no-map; - reg = <0x0 0x85c00000 0x0 0x500000>; - }; - - pil_adsp_mem: pil_adsp_region@86100000 { - no-map; - reg = <0x0 0x86100000 0x0 0x2100000>; - }; - - pil_slpi_mem: pil_slpi_region@88200000 { - no-map; - reg = <0x0 0x88200000 0x0 0x1500000>; - }; - - pil_cdsp_mem: pil_cdsp_region@89700000 { - no-map; - reg = <0x0 0x89700000 0x0 0x1e00000>; - }; - - pil_ipa_fw_mem: pil_ipa_fw_region@8b500000 { - no-map; - reg = <0x0 0x8b500000 0x0 0x10000>; - }; - - pil_ipa_gsi_mem: pil_ipa_gsi_region@8b510000 { - no-map; - reg = <0x0 0x8b510000 0x0 0xa000>; - }; - - pil_gpu_mem: pil_gpu_region@8b51a000 { - no-map; - reg = <0x0 0x8b51a000 0x0 0x2000>; - }; - - pil_spss_mem: pil_spss_region@8b600000 { - no-map; - reg = <0x0 0x8b600000 0x0 0x100000>; - }; - - pil_modem_mem: modem_region@8b800000 { - no-map; - reg = <0x0 0x8b800000 0x0 0x10000000>; - }; - - hyp_reserved_mem: qheebsp_dbg_vm_hyp_region@d0000000 { - no-map; - reg = <0x0 0xd0000000 0x0 0x800000>; - }; - - pil_trustedvm_mem: pil_trustedvm_region@d0800000 { - no-map; - reg = <0x0 0xd0800000 0x0 0x76f7000>; - }; - - qrtr_shbuf: qrtr-shmem { - no-map; - reg = <0x0 0xd7ef7000 0x0 0x9000>; - }; - - chan0_shbuf: neuron_block@0 { - no-map; - reg = <0x0 0xd7f00000 0x0 0x80000>; - }; - - chan1_shbuf: neuron_block@1 { - no-map; - reg = <0x0 0xd7f80000 0x0 0x80000>; - }; - - removed_mem: removed_region@d8800000 { - no-map; - reg = <0x0 0xd8800000 0x0 0x6800000>; - }; - - adsp_mem: adsp_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0xC00000>; - }; - - sdsp_mem: sdsp_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x800000>; - }; - - cdsp_mem: cdsp_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x400000>; - }; - - user_contig_mem: user_contig_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1000000>; - }; - - qseecom_mem: qseecom_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1400000>; - }; - - qseecom_ta_mem: qseecom_ta_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1000000>; - }; - - secure_display_memory: secure_display_region { /* Secure UI */ - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0xA400000>; - }; - - cnss_wlan_mem: cnss_wlan_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1400000>; - }; - - /* global autoconfigured region for contiguous allocations */ - linux,cma { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x2000000>; - linux,cma-default; - }; - - dump_mem: mem_dump_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - size = <0 0x3000000>; - }; - - sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1000000>; - }; - - audio_cma_mem: audio_cma_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x1C00000>; - }; - - splash_memory:splash_region { - reg = <0x0 0xe1000000 0x0 0x02300000>; - label = "cont_splash_region"; - }; - - dfps_data_memory: dfps_data_region { - reg = <0x0 0xe3300000 0x0 0x0100000>; - label = "dfps_data_region"; - }; - - memshare_mem: memshare_region { - compatible = "shared-dma-pool"; - no-map; - /* - * Memory shared with modem needs to be outside of - * the CLADE address space, which begins at - * 0xE0000000 and spans 512 MB. - */ - alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>; - alignment = <0x0 0x100000>; - size = <0x0 0x800000>; - }; - - non_secure_display_memory: non_secure_display_region { - compatible = "shared-dma-pool"; - alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; - reusable; - alignment = <0x0 0x400000>; - size = <0x0 0x6400000>; - }; + hyp_mem: hyp_region@80000000 { + no-map; + reg = <0x0 0x80000000 0x0 0x600000>; }; - chosen { - bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x98c000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + xbl_aop_mem: xbl_aop_region@80700000 { + no-map; + reg = <0x0 0x80700000 0x0 0x160000>; + }; + + cmd_db: reserved-memory@80860000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x0 0x80860000 0x0 0x20000>; + }; + + reserved_xbl_uefi_log: res_xbl_uefi_log_region@80880000 { + no-map; + reg = <0x0 0x80880000 0x0 0x14000>; + }; + + smem_mem: smem_region@80900000 { + no-map; + reg = <0x0 0x80900000 0x0 0x200000>; + }; + + cpucp_fw_mem: cpucp_fw_region@80b00000 { + no-map; + reg = <0x0 0x80b00000 0x0 0x100000>; + }; + + cdsp_secure_heap: cdsp_secure_heap@80c00000 { + no-map; + reg = <0x0 0x80c00000 0x0 0x4600000>; + }; + + pil_camera_mem: pil_camera_region@85200000 { + no-map; + reg = <0x0 0x85200000 0x0 0x500000>; + }; + + pil_video_mem: pil_video_region@85700000 { + no-map; + reg = <0x0 0x85700000 0x0 0x500000>; + }; + + pil_cvp_mem: pil_cvp_region@85c00000 { + no-map; + reg = <0x0 0x85c00000 0x0 0x500000>; + }; + + pil_adsp_mem: pil_adsp_region@86100000 { + no-map; + reg = <0x0 0x86100000 0x0 0x2100000>; + }; + + pil_slpi_mem: pil_slpi_region@88200000 { + no-map; + reg = <0x0 0x88200000 0x0 0x1500000>; + }; + + pil_cdsp_mem: pil_cdsp_region@89700000 { + no-map; + reg = <0x0 0x89700000 0x0 0x1e00000>; + }; + + pil_ipa_fw_mem: pil_ipa_fw_region@8b500000 { + no-map; + reg = <0x0 0x8b500000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: pil_ipa_gsi_region@8b510000 { + no-map; + reg = <0x0 0x8b510000 0x0 0xa000>; + }; + + pil_gpu_mem: pil_gpu_region@8b51a000 { + no-map; + reg = <0x0 0x8b51a000 0x0 0x2000>; + }; + + pil_spss_mem: pil_spss_region@8b600000 { + no-map; + reg = <0x0 0x8b600000 0x0 0x100000>; + }; + + pil_modem_mem: modem_region@8b800000 { + no-map; + reg = <0x0 0x8b800000 0x0 0x10000000>; + }; + + hyp_reserved_mem: qheebsp_dbg_vm_hyp_region@d0000000 { + no-map; + reg = <0x0 0xd0000000 0x0 0x800000>; + }; + + pil_trustedvm_mem: pil_trustedvm_region@d0800000 { + no-map; + reg = <0x0 0xd0800000 0x0 0x76f7000>; + }; + + qrtr_shbuf: qrtr-shmem { + no-map; + reg = <0x0 0xd7ef7000 0x0 0x9000>; + }; + + chan0_shbuf: neuron_block@0 { + no-map; + reg = <0x0 0xd7f00000 0x0 0x80000>; + }; + + chan1_shbuf: neuron_block@1 { + no-map; + reg = <0x0 0xd7f80000 0x0 0x80000>; + }; + + removed_mem: removed_region@d8800000 { + no-map; + reg = <0x0 0xd8800000 0x0 0x6800000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xC00000>; + }; + + sdsp_mem: sdsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + }; + + cdsp_mem: cdsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x400000>; + }; + + user_contig_mem: user_contig_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + secure_display_memory: secure_display_region { /* Secure UI */ + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0xA400000>; + }; + + cnss_wlan_mem: cnss_wlan_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + size = <0 0x3000000>; + }; + + sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + audio_cma_mem: audio_cma_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1C00000>; + }; + + splash_memory:splash_region { + reg = <0x0 0xe1000000 0x0 0x02300000>; + label = "cont_splash_region"; + }; + + dfps_data_memory: dfps_data_region { + reg = <0x0 0xe3300000 0x0 0x0100000>; + label = "dfps_data_region"; + }; + + memshare_mem: memshare_region { + compatible = "shared-dma-pool"; + no-map; + /* + * Memory shared with modem needs to be outside of + * the CLADE address space, which begins at + * 0xE0000000 and spans 512 MB. + */ + alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>; + alignment = <0x0 0x100000>; + size = <0x0 0x800000>; + }; + + non_secure_display_memory: non_secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x6400000>; }; }; From fb9ed3827fd94da2035e7872d3fd8db2078274d3 Mon Sep 17 00:00:00 2001 From: Vaibhav Agrawal Date: Tue, 13 Oct 2020 20:47:25 +0530 Subject: [PATCH 07/66] ARM: dts: msm: Add cqhci_ice and sdcc_ice_slave regions Add the cqhci_ice in cqhci node and sdcc_ice_slave region in hwkm node to support file based encryption on holi emmc device. Change-Id: Ic9f3486f1fe3f572c444dc327e121f7b20c69129 --- qcom/holi.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 1d8a294b6fd4..8dc92e087030 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2119,8 +2119,8 @@ sdhc_1: sdhci@4744000 { compatible = "qcom,sdhci-msm-v5"; - reg = <0x04744000 0x1000>, <0x04745000 0x1000>; - reg-names = "hc_mem", "cqhci_mem"; + reg = <0x04744000 0x1000>, <0x04745000 0x1000>, <0x04748000 0x8000>; + reg-names = "hc_mem", "cqhci_mem", "cqhci_ice"; iommus = <&apps_smmu 0x20 0x0>; qcom,iommu-dma = "fastmap"; @@ -2491,8 +2491,8 @@ qcom_hwkm: hwkm@4440000 { compatible = "qcom,hwkm"; - reg = <0x4440000 0x9000>, <0x04810000 0x9000>; - reg-names = "km_master", "ice_slave"; + reg = <0x4440000 0x9000>, <0x04810000 0x9000>, <0x04750000 0x9000>; + reg-names = "km_master", "ice_slave", "sdcc_ice_slave"; qcom,enable-hwkm-clk; clock-names = "km_clk_src"; clocks = <&rpmcc RPM_SMD_HWKM_CLK>; From 15b27cfd0ae9aac4ddfa031d331daf10a73a604f Mon Sep 17 00:00:00 2001 From: Mohammed Siddiq Date: Wed, 14 Oct 2020 21:03:42 +0530 Subject: [PATCH 08/66] ARM: dts: msm: Add cnss config for internal power amp for shima QCA6490 requires additional voltage regulator for internal power amplifier. Add config for TCS CMD offset to enable this regulator. Change-Id: Iea43e40b95f7bf36ab2bf0dd36039fd21f213be5 --- qcom/shima.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 3e2dd664a680..488876e47603 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3463,8 +3463,9 @@ wlan: qcom,cnss-qca6490@b0000000 { compatible = "qcom,cnss-qca6490"; - reg = <0xb0000000 0x10000>; - reg-names = "smmu_iova_ipa"; + reg = <0xb0000000 0x10000>, + <0xb2e5510 0x690>; + reg-names = "smmu_iova_ipa", "tcs_cmd"; wlan-en-gpio = <&tlmm 64 0>; qcom,bt-en-gpio = <&tlmm 65 0>; pinctrl-names = "wlan_en_active", "wlan_en_sleep"; @@ -3473,6 +3474,8 @@ qcom,wlan-rc-num = <0>; qcom,wlan-ramdump-dynamic = <0x420000>; qcom,wlan-cbc-enabled; + /* RPMH_PDC_WLAN_RF_TCS<6>_CMD<0> offset */ + qcom,tcs_offset_int_pow_amp_vreg = <0x4B0>; vdd-wlan-aon-supply = <&S2C>; qcom,vdd-wlan-aon-config = <950000 952000 0 0 1>; From c86be42f33c9f212b3692b91f91ac0e2564857fe Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Thu, 15 Oct 2020 16:50:08 +0530 Subject: [PATCH 09/66] ARM: dts: msm: Change IPA bandwidth threshold value for holi target Change IPA bandwidth threshold value for holi target. Change-Id: I85e67351f544fe0eb6689257e4d15190b454a9cd --- qcom/holi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index e5a0ef6954b8..58f58f86e357 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2638,7 +2638,7 @@ qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO"; - qcom,throughput-threshold = <310 600 1000>; + qcom,throughput-threshold = <600 2500 5000>; qcom,scaling-exceptions = <>; /* smp2p information */ From 1e09bb15e1e6e8066078be8274f27061fd67b6e8 Mon Sep 17 00:00:00 2001 From: Maria Yu Date: Thu, 15 Oct 2020 19:28:37 +0800 Subject: [PATCH 10/66] ARM: dts: msm: Move firmware node ahead Bootloader need to update property in firmware, so move firmware node ahead can improve the bootloader search dt and update property time. Change-Id: Id04bf9b8544cf43e33c0fc30aaef4b9bf5eb093d --- qcom/lahaina.dtsi | 44 +++++++++++++++++++++++--------------------- 1 file changed, 23 insertions(+), 21 deletions(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index b9827601ded2..9b7ee550cea5 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -63,6 +63,8 @@ usb1 = &usb1; }; + firmware: firmware {}; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -267,31 +269,31 @@ }; soc: soc { }; +}; - firmware: firmware { - scm { - compatible = "qcom,scm"; - qcom,dload-mode = <&tcsr 0x13000>; +&firmware { + scm { + compatible = "qcom,scm"; + qcom,dload-mode = <&tcsr 0x13000>; + }; + + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; }; - android { - compatible = "android,firmware"; - vbmeta { - compatible = "android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo"; - }; - - fstab { - compatible = "android,fstab"; - vendor { - compatible = "android,vendor"; - dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; - type = "ext4"; - mnt_flags = "ro,barrier=1,discard"; - fsmgr_flags = "wait,slotselect,avb"; - status = "ok"; - }; + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; }; }; }; From e52c882a4cd2f243ea4f8c87104aa8ee383c6297 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Fri, 16 Oct 2020 16:27:15 +0530 Subject: [PATCH 11/66] dt-bindings: thermal: Add support for QMI beamer ADC and RF sensors Add support for QMI beamer ADC and RF sensors to apps. It enables these sensors as thermal zone sensors so that we can read and set trip thresholds via thermal zone. Change-Id: I000d335dc2ee82afd4b3f41425ff296205e6f922 --- bindings/thermal/qti-qmi-sensor.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/bindings/thermal/qti-qmi-sensor.txt b/bindings/thermal/qti-qmi-sensor.txt index b9a703cf1a14..319329676034 100644 --- a/bindings/thermal/qti-qmi-sensor.txt +++ b/bindings/thermal/qti-qmi-sensor.txt @@ -62,6 +62,15 @@ Subsystem properties: 29. mmw_pa3 30. sdr_mmw_therm 31. msm_skin_therm + 32. beamer_n_therm + 33. beamer_e_therm + 34. beamer_w_therm + 35. qfe_ret_pa0_fr1 + 36. qfe_wtr_pa0_fr1 + 37. qfe_wtr_pa1_fr1 + 38. qfe_wtr_pa2_fr1 + 39. qfe_wtr_pa3_fr1 + 40. qfe_wtr0_fr1 Example: From 2689aa15563fe8023e1c664a09d8431db6afde75 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Singh Date: Mon, 28 Sep 2020 12:00:33 +0530 Subject: [PATCH 12/66] ARM: dts: msm: Add HWSPINLOCK, SMEM and SMP2P for yupik Add the device tree nodes to enable smp2p communication to remote processors. Change-Id: I09caa7bfc86231a8b1abdbe2141404081a0f1174 --- qcom/yupik.dtsi | 111 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 63494e9684f3..d3e179d55f4c 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -837,6 +837,117 @@ , ; }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0x1f40000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1fc0000 { + compatible = "syscon"; + reg = <0x1fc0000 0x30000>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-nsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-wpss { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P>; + qcom,local-pid = <0>; + qcom,remote-pid = <13>; + + wpss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wpss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; }; #include "shima-gdsc.dtsi" From 1d91bdadb78b43f93390ed8456def479582aed91 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Singh Date: Mon, 28 Sep 2020 20:01:14 +0530 Subject: [PATCH 13/66] ARM: dts: msm: Add glink entries for yupik Add the device tree entries for glink driver and glink packet driver to provide the communication with remote peripherals. Change-Id: Ibe804ad78b57a7eabc764227e40316e8d9f16fe3 --- qcom/yupik.dtsi | 167 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 167 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index d3e179d55f4c..dec328452df7 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -948,6 +948,173 @@ #interrupt-cells = <2>; }; }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "mpss_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 0x2>; + }; + + qcom,modem_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>, + <&glink_wpss>; + }; + }; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "adsp_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_cdsp>, + <&glink_wpss>; + }; + }; + + glink_cdsp: cdsp { + qcom,remote-pid = <5>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "dsps_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "cdsp"; + qcom,glink-label = "cdsp"; + + qcom,cdsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,cdsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>, + <&glink_wpss>; + }; + }; + + glink_wpss: wpss { + qcom,remote-pid = <13>; + transport = "smem"; + mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "wpss_smem"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + label = "wpss"; + qcom,glink-label = "wpss"; + + qcom,wpss_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,wpss_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>, + <&glink_cdsp>; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; }; #include "shima-gdsc.dtsi" From a1b66c7137a138a54833ee3028f2bb7af80aff03 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Singh Date: Tue, 29 Sep 2020 12:55:56 +0530 Subject: [PATCH 14/66] ARM: dts: msm: Add AOP QMP nodes for yupik Add the QMP and QMP DEBUGFS node to facilitiate communication with AOP. The QMP driver sends messages using the AOP msgram with a mailbox like protocol. Change-Id: I71d3fe058ff98d2000c61d91b3601c3d6217ed34 --- qcom/yupik.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index dec328452df7..c07780c7eed8 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1115,6 +1115,31 @@ qcom,glinkpkt-dev-name = "smd11"; }; }; + + qmp_aop: qcom,qmp-aop@c300000 { + compatible = "qcom,qmp-mbox"; + mboxes = <&ipcc_mproc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "aop_qmp"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + reg = <0xc300000 0x400>; + reg-names = "msgram"; + + label = "aop"; + qcom,early-boot; + priority = <0>; + mbox-desc-offset = <0x0>; + #mbox-cells = <1>; + }; + + aop-msg-client { + compatible = "qcom,debugfs-qmp-client"; + mboxes = <&qmp_aop 0>; + mbox-names = "aop"; + }; }; #include "shima-gdsc.dtsi" From 68909502f4d209717c4ed7433f12391a492f41a2 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Sun, 18 Oct 2020 22:23:06 +0530 Subject: [PATCH 15/66] ARM: dts: qcom: Add quiet-therm thermal zone mitigation for HOLI Add quiet-therm skin thermal zone mitigation rule with gpu, cdsp and modem_skin as cooling devices based on latest recommendations. Change-Id: I25e18a1a693f3107be823ea6dd666084e4f84a2c --- qcom/holi-qrd.dtsi | 64 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index 35c761d75f92..51c11a11dd60 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -320,6 +320,70 @@ 500000>; }; +&thermal_zones { + quiet-therm-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm6150l_adc_tm ADC5_GPIO4_100K_PU>; + + trips { + quiet_modem_trip0: quiet-modem-trip0 { + temperature = <42000>; + hysteresis = <4000>; + type = "passive"; + }; + + quiet_modem_trip1: quiet-modem-trip1 { + temperature = <44000>; + hysteresis = <4000>; + type = "passive"; + }; + + quiet_cx_trip: quiet-cx-trip { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; + + quiet_modem_trip2: quiet-modem-trip2 { + temperature = <56000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu-cdev { + trip = <&quiet_cx_trip>; + /* throttle to 565000000Hz */ + cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-3) + (THERMAL_MAX_LIMIT-3)>; + }; + + cdsp-cdev0 { + trip = <&quiet_cx_trip>; + cooling-device = <&cdsp_sw 4 4>; + }; + + modem-skin-cdev0 { + trip = <&quiet_modem_trip0>; + cooling-device = <&modem_skin 1 1>; + }; + + modem-skin-cdev1 { + trip = <&quiet_modem_trip1>; + cooling-device = <&modem_skin 2 2>; + }; + + modem-skin-cdev2 { + trip = <&quiet_modem_trip2>; + cooling-device = <&modem_skin 3 3>; + }; + }; + }; +}; + &pm7250b_qg { status = "ok"; #io-channel-cells = <1>; From c12341fa846cbdae3b4899d126681a84ac6d5b81 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Mon, 19 Oct 2020 15:42:49 +0530 Subject: [PATCH 16/66] ARM: dts: msm: Update the PSCI mode id for yupik Cx-off mode is not supported for yupik. Update the mode id to exercise cx-ret mode instead of cx-off. Change-Id: I685d2869c58d99edc4c3631c0c74ae08877ee03a --- qcom/yupik-pm.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/qcom/yupik-pm.dtsi b/qcom/yupik-pm.dtsi index cfd438443c3c..5019d0da8c8c 100644 --- a/qcom/yupik-pm.dtsi +++ b/qcom/yupik-pm.dtsi @@ -37,15 +37,15 @@ qcom,min-child-idx = <2>; }; - CX_OFF: qcom,pm-cluster-level@2 { /* Cx Off */ + CX_RET: qcom,pm-cluster-level@2 { /* Cx Ret */ reg = <2>; compatible = "arm,idle-state"; - idle-state-name = "cx-off"; + idle-state-name = "cx-ret"; entry-latency-us = <3263>; exit-latency-us = <4562>; min-residency-us = <8467>; - arm,psci-suspend-param = <0x2240>; - qcom,psci-mode = <0x224>; + arm,psci-suspend-param = <0x1240>; + qcom,psci-mode = <0x124>; qcom,is-reset; qcom,notify-rpm; qcom,min-child-idx = <2>; @@ -58,8 +58,8 @@ entry-latency-us = <3638>; exit-latency-us = <6562>; min-residency-us = <9826>; - arm,psci-suspend-param = <0xc340>; - qcom,psci-mode = <0xc34>; + arm,psci-suspend-param = <0xb340>; + qcom,psci-mode = <0xb34>; qcom,is-reset; qcom,notify-rpm; qcom,min-child-idx = <2>; From 6df8cf02ab25b0df4c3b1a0791e8f17bf3514148 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Mon, 19 Oct 2020 19:32:44 +0530 Subject: [PATCH 17/66] ARM: dts: msm: Update PSCI state id for shima The wakeup value needs to be programmed for cx-off mode as well. Update the state id to 0x234 to indicate trustzone to program wakeup value. Change-Id: I3fcb7c66b4d796b121fce4059574d467f61f91a9 --- qcom/shima-pm.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/shima-pm.dtsi b/qcom/shima-pm.dtsi index cfd438443c3c..73a3de7dbd79 100644 --- a/qcom/shima-pm.dtsi +++ b/qcom/shima-pm.dtsi @@ -44,8 +44,8 @@ entry-latency-us = <3263>; exit-latency-us = <4562>; min-residency-us = <8467>; - arm,psci-suspend-param = <0x2240>; - qcom,psci-mode = <0x224>; + arm,psci-suspend-param = <0x2340>; + qcom,psci-mode = <0x234>; qcom,is-reset; qcom,notify-rpm; qcom,min-child-idx = <2>; From 00b3cbb697558c79ef788a5de6a43b2f573fb4a1 Mon Sep 17 00:00:00 2001 From: "Vangala, Amarnath" Date: Tue, 20 Oct 2020 00:12:55 +0530 Subject: [PATCH 18/66] ARM: dts: qcom: add physical addr for swr tx slaves of Shima Add dt property to read physical addresses of TX soundwire master slaves of Shima. Change-Id: I00d4c7c7c7c6c4c59b792fbea48e8cf4ae44bbb8 --- qcom/shima-audio-overlay.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/shima-audio-overlay.dtsi b/qcom/shima-audio-overlay.dtsi index 5c44652dd529..69e699119b63 100644 --- a/qcom/shima-audio-overlay.dtsi +++ b/qcom/shima-audio-overlay.dtsi @@ -69,6 +69,11 @@ <3 SWRM_TX3_CH1 0x1>, <3 SWRM_TX3_CH2 0x2>, <3 SWRM_TX3_CH3 0x4>, <3 SWRM_TX3_CH4 0x8>; qcom,swr-num-dev = <1>; + qcom,swr-phy-dev-addr = <0x0D 0x01170223>, + <0x08 0x58350223>, + <0x08 0x58350222>, + <0x08 0x58350221>, + <0x08 0x58350220>; qcom,swr-clock-stop-mode0 = <1>; qcom,swr-mstr-irq-wakeup-capable = <1>; wcd938x_tx_slave: wcd938x-tx-slave { From 9c0aa378c748225ad4d78a8c9406447576f3e342 Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Wed, 30 Sep 2020 16:24:49 -0700 Subject: [PATCH 19/66] ARM: dts: msm: Update memory-map for sdxlemur Select a different memory map depending on board file. Change-Id: I5ed751eac765363a064edf8069428e4290a0648d --- qcom/sdxlemur-1024mb.dtsi | 9 +++++ qcom/sdxlemur-512mb.dtsi | 53 ++++++++++++++++++++++++++++ qcom/sdxlemur-cdp.dts | 2 +- qcom/sdxlemur-mtp-cpe.dts | 1 + qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts | 1 + qcom/sdxlemur-mtp-mbb-pcie-ep.dts | 1 + qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts | 1 + qcom/sdxlemur-mtp-mbb.dts | 1 + qcom/sdxlemur-mtp.dts | 1 + qcom/sdxlemur-rcm-pcie-ep.dts | 1 + qcom/sdxlemur-rcm-rc.dts | 1 + qcom/sdxlemur-rumi.dts | 1 + qcom/sdxlemur.dtsi | 42 ---------------------- 13 files changed, 72 insertions(+), 43 deletions(-) create mode 100644 qcom/sdxlemur-1024mb.dtsi create mode 100644 qcom/sdxlemur-512mb.dtsi diff --git a/qcom/sdxlemur-1024mb.dtsi b/qcom/sdxlemur-1024mb.dtsi new file mode 100644 index 000000000000..86fae265cfbd --- /dev/null +++ b/qcom/sdxlemur-1024mb.dtsi @@ -0,0 +1,9 @@ +#include "sdxlemur-512mb.dtsi" + +&mpss_adsp_mem { + reg = <0x90800000 0x10000000>; +}; + +&access_control_mem { + reg = <0x8fd80000 0x80000>; +}; diff --git a/qcom/sdxlemur-512mb.dtsi b/qcom/sdxlemur-512mb.dtsi new file mode 100644 index 000000000000..4e48c97523d0 --- /dev/null +++ b/qcom/sdxlemur-512mb.dtsi @@ -0,0 +1,53 @@ +&reserved_memory { + mpss_adsp_mem: mpss_adsp_region@90800000 { + no-map; + reg = <0x90800000 0xF800000>; + }; + + tz_mem: tz_mem_region@8ff00000 { + no-map; + reg = <0x8ff00000 0x600000>; + }; + + cmd_db: reserved-memory@8fee0000 { + compatible = "qcom,cmd-db"; + no-map; + reg = <0x8fee0000 0x20000>; + }; + + smem_mem: smem_region@8fe20000 { + no-map; + reg = <0x8fe20000 0xc0000>; + label = "smem_mem"; + }; + + aop_mem: aop_regions@0x8fe00000 { + no-map; + reg = <0x8fe00000 0x20000>; + }; + + access_control_mem: access_control_region@8fd80000 { + no-map; + reg = <0x8fd80000 0x40000>; + }; + + hyp_mem: hyp_region@8fd00000 { + no-map; + reg = <0x8fd00000 0x80000>; + }; + + secdata_mem: secdata_region@0x8fcfd000 { + no-map; + reg = <0x8fcfd000 0x1000>; + }; + + ipa_fw_mem: ipa_fw_region@0x8fced000 { + no-map; + reg = <0x8fced000 0x10000>; + }; + + mpss_dsm: mpss_dsm_region@8c400000 { + no-map; + reg = <0x8c400000 0x3200000>; + }; +}; diff --git a/qcom/sdxlemur-cdp.dts b/qcom/sdxlemur-cdp.dts index 963cb1d1f502..93cd0f92dd66 100644 --- a/qcom/sdxlemur-cdp.dts +++ b/qcom/sdxlemur-cdp.dts @@ -2,7 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-cdp.dtsi" - +#include "sdxlemur-1024mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR CDP"; compatible = "qcom,sdxlemur-cdp", diff --git a/qcom/sdxlemur-mtp-cpe.dts b/qcom/sdxlemur-mtp-cpe.dts index 696b1ab58713..0e48eebc0c2f 100644 --- a/qcom/sdxlemur-mtp-cpe.dts +++ b/qcom/sdxlemur-mtp-cpe.dts @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-cpe.dtsi" +#include "sdxlemur-1024mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE"; diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts index ead998c52e3c..e8afacb3c415 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-mbb-ntn3-pcie.dtsi" +#include "sdxlemur-1024mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB NTN3 PCIE"; diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep.dts b/qcom/sdxlemur-mtp-mbb-pcie-ep.dts index 615f5c59659c..eb4521abbe69 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-ep.dts +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep.dts @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-mbb-pcie-ep.dtsi" +#include "sdxlemur-512mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB PCIE-EP"; diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts index c849ed133087..ac65ac0913e2 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-mbb-pcie-rc-ep.dtsi" +#include "sdxlemur-512mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB RC PCIE-EP"; diff --git a/qcom/sdxlemur-mtp-mbb.dts b/qcom/sdxlemur-mtp-mbb.dts index 117c1bb3719b..e9bc21eb4200 100644 --- a/qcom/sdxlemur-mtp-mbb.dts +++ b/qcom/sdxlemur-mtp-mbb.dts @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-mbb.dtsi" +#include "sdxlemur-1024mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB"; diff --git a/qcom/sdxlemur-mtp.dts b/qcom/sdxlemur-mtp.dts index f826463910c2..dfbdf23171f0 100644 --- a/qcom/sdxlemur-mtp.dts +++ b/qcom/sdxlemur-mtp.dts @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp.dtsi" +#include "sdxlemur-1024mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP"; diff --git a/qcom/sdxlemur-rcm-pcie-ep.dts b/qcom/sdxlemur-rcm-pcie-ep.dts index 11a14dc88bef..43e60bca2eca 100644 --- a/qcom/sdxlemur-rcm-pcie-ep.dts +++ b/qcom/sdxlemur-rcm-pcie-ep.dts @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-rcm-pcie-ep.dtsi" +#include "sdxlemur-512mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR RCM PCIe-EP"; diff --git a/qcom/sdxlemur-rcm-rc.dts b/qcom/sdxlemur-rcm-rc.dts index f061c22ed532..990224dd464a 100644 --- a/qcom/sdxlemur-rcm-rc.dts +++ b/qcom/sdxlemur-rcm-rc.dts @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-rcm-rc.dtsi" +#include "sdxlemur-1024mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR RCM Root Complex"; diff --git a/qcom/sdxlemur-rumi.dts b/qcom/sdxlemur-rumi.dts index 59a28ebbef55..d0b471e1379f 100644 --- a/qcom/sdxlemur-rumi.dts +++ b/qcom/sdxlemur-rumi.dts @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-rumi.dtsi" +#include "sdxlemur-1024mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR RUMI"; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index f7026ee36267..a3294e016f86 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -32,48 +32,6 @@ #size-cells = <1>; ranges; - cmd_db: reserved-memory@8fee0000 { - compatible = "qcom,cmd-db"; - no-map; - reg = <0x8fee0000 0x20000>; - }; - - mpss_adsp_mem: mpss_adsp_region@90800000 { - no-map; - reg = <0x90800000 0x10000000>; - }; - - tz_mem: tz_mem_region@8ff00000 { - no-map; - reg = <0x8ff00000 0x600000>; - }; - - smem_mem: smem_region@8fe40000 { - no-map; - reg = <0x8fe40000 0xc0000>; - label = "smem_mem"; - }; - - peripheral_mem: peripheral_region@8fd00000 { - no-map; - reg = <0x8fd00000 0x140000>; - }; - - /* - * The exact size of this region may vary based on DDR size. - * 0x100000 will be valid for all DDR sizes at the cost of - * slightly reducing the memory available for HLOS. - */ - peripheral_mem2: peripheral_region2@8fb00000 { - no-map; - reg = <0x8fb00000 0x100000>; - }; - - mpss_dsm: mpss_dsm_region@8c400000 { - no-map; - reg = <0x8c400000 0x3200000>; - }; - dump_mem: mem_dump_region { compatible = "shared-dma-pool"; alloc-ranges = <0x00000000 0xffffffff>; From 0b6c0a5d70c102e9838af6be28be9113c70a6f3e Mon Sep 17 00:00:00 2001 From: Mohammed Siddiq Date: Tue, 20 Oct 2020 10:00:52 +0530 Subject: [PATCH 20/66] ARM: dts: msm: Add cnss-enable-self-recovery flag for shima Add cnss-enable-self-recovery flag for shima. It enables self recovery on link down detected by host driver. Change-Id: I2c66bcc0d9359dbb972b7180aa40eba404cb08d8 --- qcom/shima.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 5032f9039003..4e0d2f39ab72 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3497,6 +3497,7 @@ qcom,wlan-cbc-enabled; /* RPMH_PDC_WLAN_RF_TCS<6>_CMD<0> offset */ qcom,tcs_offset_int_pow_amp_vreg = <0x4B0>; + cnss-enable-self-recovery; vdd-wlan-aon-supply = <&S2C>; qcom,vdd-wlan-aon-config = <950000 952000 0 0 1>; From 9e2e1a059b39fecd22926d93f9f78edf9c34dbc9 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Tue, 20 Oct 2020 13:38:53 +0530 Subject: [PATCH 21/66] ARM: dts: msm: Add bootargs for Yupik Add bootargs earlycon boot parameters for Yupik SOC. Change-Id: I8019e2d2cc86de5ab51c850af8e4b43cf7365cad --- qcom/yupik.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index d5d4682d9a13..4ae827c5a3bc 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -306,7 +306,9 @@ soc: soc { }; - chosen { }; + chosen { + bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + }; }; &soc { From 9419db1f2aad66429f96c5735c7eda97f5462f11 Mon Sep 17 00:00:00 2001 From: Vivek Golani Date: Tue, 20 Oct 2020 13:21:19 +0530 Subject: [PATCH 22/66] bindings: mproc: Add support for scuba and monaco mailbox strings Update bindings of mailbox for scuba and monaco device. Change-Id: Ie35d098cb7bce110597c84e34e6eb498d3a170a9 --- bindings/mailbox/qcom,apcs-kpss-global.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/mailbox/qcom,apcs-kpss-global.txt b/bindings/mailbox/qcom,apcs-kpss-global.txt index 63cd9385a136..833c68a150c1 100644 --- a/bindings/mailbox/qcom,apcs-kpss-global.txt +++ b/bindings/mailbox/qcom,apcs-kpss-global.txt @@ -17,6 +17,8 @@ platforms. "qcom,sm8150-apss-shared" "qcom,ipq8074-apcs-apps-global" "qcom,sdxlemur-apcs-gcc" + "qcom,scuba-apcs-hmss-global" + "qcom,monaco-apcs-hmss-global" - reg: Usage: required From 09a059f435aa12ab46215c534897cc398a17e10c Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Tue, 20 Oct 2020 14:53:20 +0530 Subject: [PATCH 23/66] ARM: dts: msm: Update PSCI state id for yupik The wakeup value needs to be programmed for cx-ret mode as well. Update the state id to 0x134 to indicate trustzone to program wakeup value. Change-Id: I25143ff78842c7d415f46d0295cfce30b5727f96 --- qcom/yupik-pm.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/yupik-pm.dtsi b/qcom/yupik-pm.dtsi index 5019d0da8c8c..e3d1ff43d709 100644 --- a/qcom/yupik-pm.dtsi +++ b/qcom/yupik-pm.dtsi @@ -44,8 +44,8 @@ entry-latency-us = <3263>; exit-latency-us = <4562>; min-residency-us = <8467>; - arm,psci-suspend-param = <0x1240>; - qcom,psci-mode = <0x124>; + arm,psci-suspend-param = <0x1340>; + qcom,psci-mode = <0x134>; qcom,is-reset; qcom,notify-rpm; qcom,min-child-idx = <2>; From de5649249b05846dfca0bbbd82ce4d9f6e65ef75 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Tue, 20 Oct 2020 11:44:58 -0700 Subject: [PATCH 24/66] ARM: dts: msm: Update silver core mitigation for Lahaina Update silver core mitigation in Lahaina to ensure minimum operating performance. Change-Id: I06adfe3bdeddf6f68c013816e408532b44f1afcf --- qcom/lahaina-thermal-overlay.dtsi | 21 --------------------- qcom/lahaina-thermal.dtsi | 24 ------------------------ 2 files changed, 45 deletions(-) diff --git a/qcom/lahaina-thermal-overlay.dtsi b/qcom/lahaina-thermal-overlay.dtsi index 15a3f166fc78..ce48bd0436ae 100644 --- a/qcom/lahaina-thermal-overlay.dtsi +++ b/qcom/lahaina-thermal-overlay.dtsi @@ -184,12 +184,6 @@ THERMAL_MAX_LIMIT>; }; - pm8350_cpu0_freq { - trip = <&pm8350_trip0>; - cooling-device = <&CPU0 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - pm8350_cpu4_freq { trip = <&pm8350_trip0>; cooling-device = <&CPU4 THERMAL_MAX_LIMIT @@ -202,21 +196,6 @@ THERMAL_MAX_LIMIT>; }; - pm8350_cpu1 { - trip = <&pm8350_trip0>; - cooling-device = <&cpu1_isolate 1 1>; - }; - - pm8350_cpu2 { - trip = <&pm8350_trip0>; - cooling-device = <&cpu2_isolate 1 1>; - }; - - pm8350_cpu3 { - trip = <&pm8350_trip0>; - cooling-device = <&cpu3_isolate 1 1>; - }; - pm8350_cpu4 { trip = <&pm8350_trip0>; cooling-device = <&cpu4_isolate 1 1>; diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index 8be59cb4c62e..27210b21b047 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -792,12 +792,6 @@ cooling-device = <&cpu0_isolate 1 1>; }; - cpu00_cdev1 { - trip = <&cpu00_config>; - cooling-device = <&CPU0 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - cpu00_cdev2 { trip = <&cpu00_config1>; cooling-device = <&cpu0_hotplug 1 1>; @@ -830,12 +824,6 @@ cooling-device = <&cpu1_isolate 1 1>; }; - cpu01_cdev1 { - trip = <&cpu01_config>; - cooling-device = <&CPU0 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - cpu01_cdev2 { trip = <&cpu01_config1>; cooling-device = <&cpu1_hotplug 1 1>; @@ -868,12 +856,6 @@ cooling-device = <&cpu2_isolate 1 1>; }; - cpu02_cdev1 { - trip = <&cpu02_config>; - cooling-device = <&CPU0 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - cpu02_cdev2 { trip = <&cpu02_config1>; cooling-device = <&cpu2_hotplug 1 1>; @@ -906,12 +888,6 @@ cooling-device = <&cpu3_isolate 1 1>; }; - cpu03_cdev1 { - trip = <&cpu03_config>; - cooling-device = <&CPU0 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - cpu03_cdev2 { trip = <&cpu03_config1>; cooling-device = <&cpu3_hotplug 1 1>; From 6dd2c343bfa5eb1a4059f3644b61cca2a2bbf11d Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Fri, 9 Oct 2020 11:46:45 +0530 Subject: [PATCH 25/66] ARM: dts: msm: Add v2.1 MTP VM device tree file for Lahaina VM Add v2.1 MTP device tree files, for Lahaina SVM. Change-Id: Iab0595866114801ed11a7f64196ae608919c61a9 --- qcom/Makefile | 3 ++- qcom/lahaina-vm-mtp-v2.1.dts | 10 ++++++++++ qcom/lahaina-vm-mtp-v2.1.dtsi | 1 + qcom/lahaina-vm-v2.dtsi | 7 +++++++ 4 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 qcom/lahaina-vm-mtp-v2.1.dts create mode 100644 qcom/lahaina-vm-mtp-v2.1.dtsi create mode 100644 qcom/lahaina-vm-v2.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 212ca73f81f0..462f5883bb27 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -171,7 +171,8 @@ ifeq ($(CONFIG_ARCH_LAHAINA), y) ifeq ($(CONFIG_ARCH_QTI_VM), y) dtb-$(CONFIG_ARCH_QTI_VM) += lahaina-vm-mtp.dtb \ lahaina-vm-cdp.dtb \ - lahaina-vm-qrd.dtb + lahaina-vm-qrd.dtb \ + lahaina-vm-mtp-v2.1.dtb endif endif diff --git a/qcom/lahaina-vm-mtp-v2.1.dts b/qcom/lahaina-vm-mtp-v2.1.dts new file mode 100644 index 000000000000..c656317eac0d --- /dev/null +++ b/qcom/lahaina-vm-mtp-v2.1.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "lahaina-vm-v2.dtsi" +#include "lahaina-vm-mtp-v2.1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahaina SVM MTP V2.1"; + compatible = "qcom,lahaina-mtp", "qcom,lahaina", "qcom,mtp"; + qcom,board-id = <0x20108 0>; +}; diff --git a/qcom/lahaina-vm-mtp-v2.1.dtsi b/qcom/lahaina-vm-mtp-v2.1.dtsi new file mode 100644 index 000000000000..2a76b5241e44 --- /dev/null +++ b/qcom/lahaina-vm-mtp-v2.1.dtsi @@ -0,0 +1 @@ +#include "lahaina-vm-mtp.dtsi" diff --git a/qcom/lahaina-vm-v2.dtsi b/qcom/lahaina-vm-v2.dtsi new file mode 100644 index 000000000000..6c5494ed784f --- /dev/null +++ b/qcom/lahaina-vm-v2.dtsi @@ -0,0 +1,7 @@ +#include "lahaina-vm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahaina VM v2"; + compatible = "qcom,lahaina"; + qcom,msm-id = <415 0x20000>; +}; From cd5fd8cbf775e4f95f23ee44fe7fef017f776a65 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 20 Oct 2020 18:49:53 +0530 Subject: [PATCH 26/66] ARM: dts: qcom: Update skin and cx thermal mitigation config for SHIMA Add quiet-therm skin sensor thermal config for SHIMA with modem, cdsp and gpu as cooling devices based on latest recomondations. Update nspss-2 tsens sensor thermal config mitigation for SHIMA with cdsp, gpu and modem as cooling devices based on latest recomondations. Change-Id: I6a8cf412b80a6d071bd669fafed61aa72ba41b24 --- qcom/shima-qrd.dtsi | 93 ++++++++++++++++++++++++++++++++++++ qcom/shima-thermal.dtsi | 103 +++++++++++++--------------------------- 2 files changed, 126 insertions(+), 70 deletions(-) diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index ea9a65cd8f39..3c4d58ff97f2 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -197,6 +197,99 @@ qcom,wireless-fw-name = "idt9412.bin"; }; +&thermal_zones { + quiet-therm-step { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pmk8350_adc_tm PM8350_ADC7_AMUX_THM1_100K_PU>; + + trips { + quiet_gpu_trip: quiet-gpu-trip { + temperature = <45000>; + hysteresis = <0>; + type = "passive"; + }; + + quiet_cpu4_trip: quiet-cpu4-trip { + temperature = <46000>; + hysteresis = <0>; + type = "passive"; + }; + + quiet_cpu7_trip: quiet-cpu7-trip { + temperature = <48000>; + hysteresis = <0>; + type = "passive"; + }; + + quiet_cpu0_trip: quiet-cpu0-trip { + temperature = <50000>; + hysteresis = <0>; + type = "passive"; + }; + + quiet_cx_trip: quiet-cx-trip { + temperature = <55000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu-cdev0 { + trip = <&quiet_gpu_trip>; + /* throttle to 443000000Hz */ + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>; + }; + + gpu-cdev1 { + trip = <&quiet_cx_trip>; + /* throttle to 285000000Hz */ + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpufreq0-cdev { + trip = <&quiet_cpu0_trip>; + /* throttle to 1516800KHz */ + cooling-device = <&CPU0 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-7)>; + }; + + cpufreq4-cdev { + trip = <&quiet_cpu4_trip>; + /* throttle to 1651200KHz */ + cooling-device = <&CPU4 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-5)>; + }; + + cpufreq7-cdev { + trip = <&quiet_cpu7_trip>; + /* throttle to 1862400KHz */ + cooling-device = <&CPU7 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-5)>; + }; + + cdsp-cdev { + trip = <&quiet_cx_trip>; + cooling-device = <&cdsp_sw 5 5>; + }; + + modem-pa-cdev { + trip = <&quiet_cx_trip>; + cooling-device = <&modem_pa 3 3>; + }; + + modem-tj-cdev { + trip = <&quiet_cx_trip>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; +}; + &qupv3_se10_i2c { #address-cells = <1>; #size-cells = <0>; diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index abf3371998fc..73aa20666ae0 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -1254,18 +1254,12 @@ }; nspss-0-step { - polling-delay-passive = <10>; + polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&tsens1 3>; trips { - nspss0_trip0: nspss0-trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - nspss0_trip1: nspss0-trip1 { + nspss0_trip: nspss0-trip { temperature = <100000>; hysteresis = <5000>; type = "passive"; @@ -1273,49 +1267,37 @@ }; cooling-maps { - cdsp-cdev0 { - trip = <&nspss0_trip0>; - cooling-device = <&cdsp_sw THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - - cdsp-cdev1 { - trip = <&nspss0_trip1>; - cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + cdsp-cdev { + trip = <&nspss0_trip>; + cooling-device = <&cdsp_sw 5 5>; }; gpu_cdev { - trip = <&nspss0_trip1>; - cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1) - (THERMAL_MAX_LIMIT-1)>; + trip = <&nspss0_trip>; + /* throttle to 285000000Hz */ + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; modem-pa-cdev { - trip = <&nspss0_trip1>; + trip = <&nspss0_trip>; cooling-device = <&modem_pa 3 3>; }; modem-tj-cdev { - trip = <&nspss0_trip1>; + trip = <&nspss0_trip>; cooling-device = <&modem_tj 3 3>; }; }; }; nspss-1-step { - polling-delay-passive = <10>; + polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&tsens1 4>; trips { - nspss1_trip0: nspss1-trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - nspss1_trip1: nspss1-trip1 { + nspss1_trip: nspss1-trip { temperature = <100000>; hysteresis = <5000>; type = "passive"; @@ -1323,49 +1305,37 @@ }; cooling-maps { - cdsp-cdev0 { - trip = <&nspss1_trip0>; - cooling-device = <&cdsp_sw THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - - cdsp-cdev1 { - trip = <&nspss1_trip1>; - cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + cdsp-cdev { + trip = <&nspss1_trip>; + cooling-device = <&cdsp_sw 5 5>; }; gpu_cdev { - trip = <&nspss1_trip1>; - cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1) - (THERMAL_MAX_LIMIT-1)>; + trip = <&nspss1_trip>; + /* throttle to 285000000Hz */ + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; modem-pa-cdev { - trip = <&nspss1_trip1>; + trip = <&nspss1_trip>; cooling-device = <&modem_pa 3 3>; }; modem-tj-cdev { - trip = <&nspss1_trip1>; + trip = <&nspss1_trip>; cooling-device = <&modem_tj 3 3>; }; }; }; nspss-2-step { - polling-delay-passive = <10>; + polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&tsens1 5>; trips { - nspss2_trip0: nspss2-trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; - - nspss2_trip1: nspss2-trip1 { + nspss2_trip: nspss2-trip { temperature = <100000>; hysteresis = <5000>; type = "passive"; @@ -1373,34 +1343,27 @@ }; cooling-maps { - cdsp-cdev0 { - trip = <&nspss2_trip0>; - cooling-device = <&cdsp_sw THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - - cdsp-cdev1 { - trip = <&nspss2_trip1>; - cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + cdsp-cdev { + trip = <&nspss2_trip>; + cooling-device = <&cdsp_sw 5 5>; }; gpu_cdev { - trip = <&nspss2_trip1>; - cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1) - (THERMAL_MAX_LIMIT-1)>; + trip = <&nspss2_trip>; + /* throttle to 285000000Hz */ + cooling-device = <&msm_gpu THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; modem-pa-cdev { - trip = <&nspss2_trip1>; + trip = <&nspss2_trip>; cooling-device = <&modem_pa 3 3>; }; modem-tj-cdev { - trip = <&nspss2_trip1>; + trip = <&nspss2_trip>; cooling-device = <&modem_tj 3 3>; }; }; }; }; - From a979112191b747d9fa5df3c341721a90dd23918d Mon Sep 17 00:00:00 2001 From: Vivek Golani Date: Wed, 21 Oct 2020 18:13:27 +0530 Subject: [PATCH 27/66] ARM: dts: msm: Add MPROC device nodes for scuba Add SMEM, TCSR Mutex, Glink and SMP2P devices for enabling interprocessor communication with MPSS, LPASS and RPM. Change-Id: Idaf5abb3a4a3f6f25ff3c219531bfe8985209418 --- qcom/scuba-iot.dtsi | 183 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 183 insertions(+) diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index c07dcefb4820..bb28d23102ff 100644 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -567,6 +567,189 @@ dcc: dcc_v2@1be2000 { #interrupt-cells = <4>; cell-index = <0>; }; + + tcsr_mutex_block: syscon@00340000 { + compatible = "syscon"; + reg = <0x340000 0x20000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + smem: qcom,smem { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 3>; + }; + + rpm_msg_ram: memory@045f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x45f0000 0x7000>; + }; + + apcs_glb: mailbox@0f111000 { + compatible = "qcom,scuba-apcs-hmss-global"; + reg = <0xF111000 0x1000>; + + #mbox-cells = <1>; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + qcom,rpm_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>, + <&glink_adsp>; + }; + + }; + + qcom,glink { + compatible = "qcom,glink"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + glink_modem: modem { + qcom,remote-pid = <1>; + transport = "smem"; + mboxes = <&apcs_glb 12>; + mbox-names = "mpss_smem"; + interrupts = ; + + label = "modem"; + qcom,glink-label = "mpss"; + + qcom,modem_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,modem_ds { + qcom,glink-channels = "DS"; + qcom,intents = <0x4000 2>; + }; + + qcom,modem_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_adsp>; + }; + }; + + glink_adsp: adsp { + qcom,remote-pid = <2>; + transport = "smem"; + mboxes = <&apcs_glb 8>; + mbox-names = "adsp_smem"; + interrupts = ; + + label = "adsp"; + qcom,glink-label = "lpass"; + + qcom,adsp_qrtr { + qcom,glink-channels = "IPCRTR"; + qcom,low-latency; + qcom,intents = <0x800 5 + 0x2000 3 + 0x4400 2>; + }; + + qcom,adsp_glink_ssr { + qcom,glink-channels = "glink_ssr"; + qcom,notify-edges = <&glink_modem>; + }; + }; + }; + + qcom,glinkpkt { + compatible = "qcom,glinkpkt"; + + qcom,glinkpkt-at-mdm0 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DS"; + qcom,glinkpkt-dev-name = "at_mdm0"; + }; + + qcom,glinkpkt-apr-apps2 { + qcom,glinkpkt-edge = "adsp"; + qcom,glinkpkt-ch-name = "apr_apps2"; + qcom,glinkpkt-dev-name = "apr_apps2"; + }; + + qcom,glinkpkt-data40-cntl { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA40_CNTL"; + qcom,glinkpkt-dev-name = "smdcntl8"; + }; + + qcom,glinkpkt-data1 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA1"; + qcom,glinkpkt-dev-name = "smd7"; + }; + + qcom,glinkpkt-data4 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA4"; + qcom,glinkpkt-dev-name = "smd8"; + }; + + qcom,glinkpkt-data11 { + qcom,glinkpkt-edge = "mpss"; + qcom,glinkpkt-ch-name = "DATA11"; + qcom,glinkpkt-dev-name = "smd11"; + }; + }; + + qcom,smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + mboxes = <&apcs_glb 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + qcom,smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts = ; + mboxes = <&apcs_glb 10>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; }; #include "pm2250.dtsi" From 40a71ca76575c9c2534dd1a1d3369415f321a110 Mon Sep 17 00:00:00 2001 From: Amine Najahi Date: Fri, 16 Oct 2020 15:24:16 -0400 Subject: [PATCH 28/66] ARM: dts: msm: select visionox panel and touch controller for TVM Select visionox default panel and focaltech touch controller for Lahaina MTP V2.1 trusted VM. Change-Id: I78eb1dcbd20c342d1db9857abcb710bb60832e82 --- qcom/lahaina-vm-mtp-v2.1.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/qcom/lahaina-vm-mtp-v2.1.dtsi b/qcom/lahaina-vm-mtp-v2.1.dtsi index 2a76b5241e44..a15cbce6a7d7 100644 --- a/qcom/lahaina-vm-mtp-v2.1.dtsi +++ b/qcom/lahaina-vm-mtp-v2.1.dtsi @@ -1 +1,19 @@ -#include "lahaina-vm-mtp.dtsi" + +&qupv3_se4_i2c { + status = "ok"; + focaltech@38 { + compatible = "focaltech,fts_ts"; + reg = <0x38>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 2340>; + focaltech,trusted-touch-mode = "vm_mode"; + focaltech,touch-environment = "tvm"; + focaltech,trusted-touch-spi-irq = <566>; + focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>; + focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; + }; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; +}; From a986821e2562b51c88ba1be50ca37edec93b3c4f Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Wed, 21 Oct 2020 20:53:23 +0530 Subject: [PATCH 29/66] Revert "ARM: dts: msm: Use PCIe_MSI for Shima" This reverts commit e506b909ef43f6464f97201f193f2197bc827346. Commit e506b909ef43f6 ("ARM: dts: msm: Use PCIe_MSI for Shima") There is MSI interrupts in PCIe DRV suspend state from device, which caused NOC error when host try to read MSI status register. Change-Id: Ia0393a2005bac508c0b4a43e41341507070ea3cd --- qcom/shima-pcie.dtsi | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index fbe74ebfb44d..32573d6def76 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -33,7 +33,7 @@ 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - msi-parent = <&pcie0_msi_snps>; + msi-parent = <&pcie0_msi>; perst-gpio = <&tlmm 94 0>; wake-gpio = <&tlmm 96 0>; @@ -194,15 +194,6 @@ }; }; - pcie0_msi_snps: qcom,pcie0_msi@a0000000 { - compatible = "qcom,pci-msi"; - msi-controller; - reg = <0xa0000000 0x0>; - interrupt-parent = <&intc>; - interrupts = ; - qcom,snps; - }; - pcie0_msi: qcom,pcie0_msi@17a10040 { compatible = "qcom,pci-msi"; msi-controller; From e431f8f76936a51a8350e49f3ed1d00bcb6de961 Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Wed, 21 Oct 2020 11:20:27 -0700 Subject: [PATCH 30/66] ARM: dts: msm: Add usb bam dt node on sdxlemur Add the usb bam related device tree entries on sdxlemur. Change-Id: I238791a84f035091a8ecc80b0a642033ff6feeaa --- qcom/sdxlemur-usb.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index a7121b5fd80c..683efa443925 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -63,6 +63,35 @@ dr_mode = "otg"; snps,xhci-imod-value = <4000>; }; + + qcom,usbbam@a704000 { + compatible = "qcom,usb-bam-msm"; + reg = <0xa704000 0x17000>; + interrupts = ; + + qcom,usb-bam-fifo-baseaddr = <0x1468b000>; + qcom,usb-bam-num-pipes = <4>; + qcom,disable-clk-gating; + qcom,usb-bam-override-threshold = <0x4001>; + qcom,usb-bam-max-mbps-highspeed = <400>; + qcom,usb-bam-max-mbps-superspeed = <3600>; + qcom,reset-bam-on-connect; + + qcom,pipe0 { + label = "ssusb-qdss-in-0"; + qcom,usb-bam-mem-type = <2>; + qcom,dir = <1>; + qcom,pipe-num = <0>; + qcom,peer-bam = <0>; + qcom,peer-bam-physical-address = <0x6064000>; + qcom,src-bam-pipe-index = <0>; + qcom,dst-bam-pipe-index = <0>; + qcom,data-fifo-offset = <0x0>; + qcom,data-fifo-size = <0x1800>; + qcom,descriptor-fifo-offset = <0x1800>; + qcom,descriptor-fifo-size = <0x800>; + }; + }; }; usb_nop_phy: usb_nop_phy { From 42f6e16aeb970a8f0e88623d89130c746129ebed Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 19 Oct 2020 14:08:31 -0700 Subject: [PATCH 31/66] ARM: dts: msm: move qcom,boot-option to HSP dedicated DTSI for sdxlemur Having qcom,boot-option set to 0x1 on main sdxlemur devicetree prevents other connects from being automatically enumerated. Most connects do not require manual enumeration like Hastings Prime (HSP) does. Therefore, move qcom,boot-option with 0x1 for PCIe to HSP dedicated devicetree. Change-Id: Ib344311c968fc610df474c5eadc693b45eed3dba --- qcom/sdxlemur-cdp.dtsi | 4 ++++ qcom/sdxlemur-mtp-mbb.dtsi | 3 +++ qcom/sdxlemur-pcie.dtsi | 1 - qcom/sdxlemur-rcm-rc.dtsi | 3 +++ 4 files changed, 10 insertions(+), 1 deletion(-) diff --git a/qcom/sdxlemur-cdp.dtsi b/qcom/sdxlemur-cdp.dtsi index 0b6dc2969cd6..aad992261b6a 100644 --- a/qcom/sdxlemur-cdp.dtsi +++ b/qcom/sdxlemur-cdp.dtsi @@ -11,3 +11,7 @@ &usb { extcon = <&vbus_detect>; }; + +&pcie0 { + qcom,boot-option = <0x1>; +}; diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index cc3a833f430e..7b1f8063b8e6 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -3,3 +3,6 @@ }; +&pcie0 { + qcom,boot-option = <0x1>; +}; diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index 11ef2356d6b2..df3f98564a8c 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -91,7 +91,6 @@ iommu-map = <0x0 &apps_smmu 0x0200 0x1>, <0x100 &apps_smmu 0x0201 0x1>; - qcom,boot-option = <0x1>; qcom,use-19p2mhz-aux-clk; qcom,slv-addr-space-size = <0x40000000>; qcom,ep-latency = <10>; diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index cc3a833f430e..7b1f8063b8e6 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -3,3 +3,6 @@ }; +&pcie0 { + qcom,boot-option = <0x1>; +}; From 89ead7ab037685f37d37310f0f56d4521365f689 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Tue, 20 Oct 2020 16:38:32 -0700 Subject: [PATCH 32/66] ARM: dts: msm: add PCIe AUX clk freq for controller for sdxlemur Replace deprecated PCIe DT entry for PCIe AUX clock controller setting with the correct entry and value. PCIe core controller requires AUX clock to be 16.6MHz for sdxlemur. Change-Id: I2fa8d8c819bfd06f80b2e274f97b282caa90eb70 --- qcom/sdxlemur-pcie.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index df3f98564a8c..35e34a9c4b2d 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -91,7 +91,7 @@ iommu-map = <0x0 &apps_smmu 0x0200 0x1>, <0x100 &apps_smmu 0x0201 0x1>; - qcom,use-19p2mhz-aux-clk; + qcom,aux-clk-freq = <17>; /* 16.6 MHz */ qcom,slv-addr-space-size = <0x40000000>; qcom,ep-latency = <10>; From 2f8632e5758758c1051040898c328bc4e8fd7f4b Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Thu, 22 Oct 2020 14:28:25 +0800 Subject: [PATCH 33/66] ARM: dts: msm: Add cti trigger number to device tree for shima Add cti trigger number to device tree for shima. Since some platforms don't have swao cti, replace configuring cti trigger number as hard code. Change-Id: I52d53848cf23d25b8b8f5dc2ed6bb6175743d3d8 --- qcom/shima-coresight.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/qcom/shima-coresight.dtsi b/qcom/shima-coresight.dtsi index e6b90830fa55..4536aeb7d154 100644 --- a/qcom/shima-coresight.dtsi +++ b/qcom/shima-coresight.dtsi @@ -107,7 +107,9 @@ coresight-name = "coresight-tmc-etf"; coresight-csr = <&swao_csr>; - coresight-ctis = <&cti0 &cti6>; + coresight-ctis = <&cti0_swao &cti3_swao>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <1>; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; @@ -154,7 +156,9 @@ qcom,sw-usb; coresight-name = "coresight-tmc-etr"; - coresight-ctis = <&cti0 &cti6>; + coresight-ctis = <&cti0 &cti3_swao>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <3>; coresight-csr = <&csr>; clocks = <&aopcc QDSS_CLK>; From c6722d8be1374e4088a6d93eb9f1159b981a3eb5 Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Thu, 22 Oct 2020 21:01:22 +0530 Subject: [PATCH 34/66] ARM: dts: msm: Reduce the IOVA range for QUP usecase This change enables SMMU page table memory savings for QUP. No functional change but helps saving memory table space. Change-Id: Ie56582683eb594a1f8c3e6f746e7d7a0691598ef --- qcom/holi-qupv3.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/holi-qupv3.dtsi b/qcom/holi-qupv3.dtsi index 530d54e635a3..2d2975b0c717 100644 --- a/qcom/holi-qupv3.dtsi +++ b/qcom/holi-qupv3.dtsi @@ -26,7 +26,8 @@ ; qcom,vote-for-bw; iommus = <&apps_smmu 0x0003 0x0>; - qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; status = "ok"; }; @@ -190,7 +191,8 @@ ; qcom,vote-for-bw; iommus = <&apps_smmu 0x00c3 0x0>; - qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; status = "ok"; }; From 0b9756a23eb57a0403194790491df5fe32ce1ebd Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Thu, 22 Oct 2020 21:06:38 +0530 Subject: [PATCH 35/66] ARM: dts: msm: Reduce the IOVA range for slimbus and QUP usecases This change enables SMMU page table memory savings for qup and slim_aud. No functional change but helps saving memory table space. Change-Id: I094d0a18d6b5a0aab1ab5ac4f05dd183392f2e17 --- qcom/shima-qupv3.dtsi | 6 ++++-- qcom/shima.dtsi | 3 ++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/qcom/shima-qupv3.dtsi b/qcom/shima-qupv3.dtsi index aa158a9189e4..a4c05936d55c 100644 --- a/qcom/shima-qupv3.dtsi +++ b/qcom/shima-qupv3.dtsi @@ -29,7 +29,8 @@ , ; iommus = <&apps_smmu 0x4c3 0x0>; - qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; @@ -362,7 +363,8 @@ , ; iommus = <&apps_smmu 0x43 0x0>; - qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; }; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 5032f9039003..71796e666482 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -537,7 +537,8 @@ qcom,apps-ch-pipes = <0x0>; qcom,ea-pc = <0x3d0>; iommus = <&apps_smmu 0x2026 0x0>; - qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; qcom,iommu-dma = "fastmap"; status = "ok"; From eb33b85feccdd48914a0fee20f4729f75055200d Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Thu, 22 Oct 2020 09:18:48 -0700 Subject: [PATCH 36/66] ARM: dts: msm: Remove modem tsens QMI thermal zone for Lahaina Modem tsens sensors are directly accessible by APSS. So remove the QMI tsens thermal zones which will not be enabled for Lahaina. Change-Id: I7844ac68c3a723abafa1f43db6a853a98426dbe0 --- qcom/lahaina-thermal-modem.dtsi | 30 ------------------------------ 1 file changed, 30 deletions(-) diff --git a/qcom/lahaina-thermal-modem.dtsi b/qcom/lahaina-thermal-modem.dtsi index c13e66fa1abb..65c9a70346f0 100644 --- a/qcom/lahaina-thermal-modem.dtsi +++ b/qcom/lahaina-thermal-modem.dtsi @@ -292,36 +292,6 @@ }; }; - modem-0-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor - (QMI_MODEM_INST_ID+QMI_MODEM_TSENS)>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - - modem-1-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor - (QMI_MODEM_INST_ID+QMI_MODEM_TSENS_1)>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - modem-streamer-usr { polling-delay-passive = <0>; polling-delay = <0>; From bc71a4b4ad7ec85d680e6fe624940b2c5a47da62 Mon Sep 17 00:00:00 2001 From: Amine Najahi Date: Mon, 19 Oct 2020 12:52:06 -0400 Subject: [PATCH 37/66] ARM: dts: msm: add trusted touch support in PVM for Lahaina Add trusted nodes to focaltech touch controller in primary VM. This will allow PVM to enable/disable secure touch when starting/stopping a TUI session. Change-Id: Ia977e8e5269b874a0ad685926d02aa5f3f8054bc --- qcom/lahaina-cdp.dtsi | 6 ++++++ qcom/lahaina-mtp.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/qcom/lahaina-cdp.dtsi b/qcom/lahaina-cdp.dtsi index c9b2da960900..4989e97dd77e 100644 --- a/qcom/lahaina-cdp.dtsi +++ b/qcom/lahaina-cdp.dtsi @@ -102,6 +102,12 @@ panel = <&dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; + + focaltech,trusted-touch-mode = "vm_mode"; + focaltech,touch-environment = "pvm"; + focaltech,trusted-touch-spi-irq = <566>; + focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>; + focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; }; atmel_mxt_ts@4a { diff --git a/qcom/lahaina-mtp.dtsi b/qcom/lahaina-mtp.dtsi index b896ca9f97d0..39f56296aed0 100644 --- a/qcom/lahaina-mtp.dtsi +++ b/qcom/lahaina-mtp.dtsi @@ -104,6 +104,12 @@ panel = <&dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; + + focaltech,trusted-touch-mode = "vm_mode"; + focaltech,touch-environment = "pvm"; + focaltech,trusted-touch-spi-irq = <566>; + focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>; + focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; }; }; From 4c279b6998d68be58699e9c4556fb7d6b3476ce0 Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Fri, 23 Oct 2020 13:59:08 +0530 Subject: [PATCH 38/66] ARM: dts: msm: add l3 latfloor in shima target Add cpu7-l3 latfloor dcvs node to scale l3 based onthe prime core frequency in shima target. Change-Id: Ia9e1642b9a4fe38ee1c51a0a2da8df8d94d15b7e --- qcom/shima.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 5032f9039003..87ec75a4bedb 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -2373,6 +2373,16 @@ &epss_l3_cpu SLAVE_EPSS_L3_CPU7>; }; + cpu7_cpu_l3_latfloor: qcom,cpu7-cpu-l3-latfloor { + compatible = "qcom,devfreq-icc-l3"; + reg = <0x18590100 0xa0>; + reg-names = "ftbl-base"; + governor = "compute"; + interconnects = + <&epss_l3_cpu MASTER_EPSS_L3_APPS + &epss_l3_cpu SLAVE_EPSS_L3_SHARED>; + }; + cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat { compatible = "qcom,devfreq-icc"; governor = "mem_latency"; @@ -2549,6 +2559,15 @@ qcom,core-dev-table = <&cpu7_cpu_l3_tbl>; }; + cpu7_l3_computemon: qcom,cpu7-l3-computemon { + compatible = "qcom,arm-compute-mon"; + qcom,cpulist = <&CPU7>; + qcom,target-dev = <&cpu7_cpu_l3_latfloor>; + qcom,core-dev-table = + < 2169600 300000000 >, + < 2707200 1420800000 >; + }; + cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon { compatible = "qcom,arm-memlat-mon"; qcom,target-dev = <&cpu0_cpu_llcc_lat>; From 6e9f894884e2a32c2e1e2cc0f17f1cf135160e40 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Fri, 23 Oct 2020 14:11:28 +0530 Subject: [PATCH 39/66] ARM: dts: msm: Update S2C min voltage for shima Update SMPS regulator S2C's minimum voltage to 550mV to match with corresponding AOP constraint value, for WLAN use case. Change-Id: I4beb27c5691100abdb28ba77e93d384ae10e9714 --- qcom/shima-regulators.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/shima-regulators.dtsi b/qcom/shima-regulators.dtsi index e592f7a5df8e..1dcabd3c06b6 100644 --- a/qcom/shima-regulators.dtsi +++ b/qcom/shima-regulators.dtsi @@ -382,9 +382,9 @@ pm8350c_s2: regulator-pm8350c-s2 { regulator-name = "pm8350c_s2"; qcom,set = ; - regulator-min-microvolt = <722000>; + regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; - qcom,init-voltage = <722000>; + qcom,init-voltage = <550000>; }; }; From e5ffd6c671beb7d9db5c267a470ba0703670c3d1 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Thu, 24 Sep 2020 12:20:26 +0530 Subject: [PATCH 40/66] ARM: dts: msm: Add eMMC, SD card support for sdxlemur Add eMMC/SD card support for sdxlemur. Change-Id: If86007c079cf36382b65515976a3e82e9c6eba8f --- qcom/sdxlemur-cdp.dtsi | 18 ++++++++ qcom/sdxlemur-mtp-mbb.dtsi | 28 ++++++++++++ qcom/sdxlemur-mtp.dtsi | 18 ++++++++ qcom/sdxlemur-pinctrl.dtsi | 92 ++++++++++++++++++++++++++++++++++++++ qcom/sdxlemur.dtsi | 28 ++++++++++++ 5 files changed, 184 insertions(+) diff --git a/qcom/sdxlemur-cdp.dtsi b/qcom/sdxlemur-cdp.dtsi index aad992261b6a..6b6ff3fc2a0c 100644 --- a/qcom/sdxlemur-cdp.dtsi +++ b/qcom/sdxlemur-cdp.dtsi @@ -8,6 +8,24 @@ status = "ok"; }; +&sdhc_1 { + status = "ok"; + + vdd-supply = <&vreg_sd_vdd>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&vreg_vddpx_2>; + qcom,vdd-io-voltage-level = <1800000 2850000>; + qcom,vdd-io-current-level = <0 10000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &usb { extcon = <&vbus_detect>; }; diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index 7b1f8063b8e6..00c959d6e75b 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -6,3 +6,31 @@ &pcie0 { qcom,boot-option = <0x1>; }; + +&sdhc_1 { + reg = <0x08804000 0x1000>, <0x08805000 0x1000>; + reg-names = "hc_mem", "cqhci_mem"; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + bus-width = <8>; + non-removable; + supports-cqe; + + vdd-supply = <&vreg_sd_vdd>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L6B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 200000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + + status = "ok"; +}; diff --git a/qcom/sdxlemur-mtp.dtsi b/qcom/sdxlemur-mtp.dtsi index 0b6dc2969cd6..7213eb337afb 100644 --- a/qcom/sdxlemur-mtp.dtsi +++ b/qcom/sdxlemur-mtp.dtsi @@ -8,6 +8,24 @@ status = "ok"; }; +&sdhc_1 { + status = "ok"; + + vdd-supply = <&vreg_sd_vdd>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&vreg_vddpx_2>; + qcom,vdd-io-voltage-level = <1800000 2850000>; + qcom,vdd-io-current-level = <0 10000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &usb { extcon = <&vbus_detect>; }; diff --git a/qcom/sdxlemur-pinctrl.dtsi b/qcom/sdxlemur-pinctrl.dtsi index ef506863a580..7acc8527e1b9 100644 --- a/qcom/sdxlemur-pinctrl.dtsi +++ b/qcom/sdxlemur-pinctrl.dtsi @@ -40,6 +40,98 @@ }; }; + sdc1_on: sdc1_on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc1_off: sdc1_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_on: sdc2_on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio99"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio99"; + bias-disable; + drive-strength = <2>; + }; + }; + pcie0 { pcie0_clkreq_default: pcie0_clkreq_default { mux { diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index a3294e016f86..4bbf2a3f6d1e 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -432,6 +432,34 @@ status = "disabled"; }; + sdhc_1: sdhci@8804000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0x08804000 0x1000>; + reg-names = "hc_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", "iface"; + + bus-width = <4>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; + + qcom,devfreq,freq-table = <50000000 200000000>; + + status = "disabled"; + + qos0 { + mask = <0x1>; + vote = <44>; + }; + }; + apsscc: clock-controller@17808100 { compatible = "qcom,sdxlemur-apsscc"; clocks = <&rpmhcc RPMH_CXO_CLK_A>, <&gcc GPLL0_OUT_EVEN>; From 1959266810774ec04abc9dd8ad56a961ce5bd0d2 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Fri, 23 Oct 2020 13:19:48 -0700 Subject: [PATCH 41/66] ARM: dts: msm: add PCIe AUX CLK freq entry for PCIe0 and PCIe1 for lahaina Have both PCIe0 and PCIe1 explicitly program their respective controller PCIe AUX CLK frequency setting with 19.2MHz on lahaina. Change-Id: If1c2508f64aa2167d93d99d0248cfbd3d8ce27b6 --- qcom/lahaina-pcie.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi index f15c2e4eda1b..9c106f0bd059 100644 --- a/qcom/lahaina-pcie.dtsi +++ b/qcom/lahaina-pcie.dtsi @@ -100,6 +100,7 @@ <0x100 &apps_smmu 0x1c01 0x1>; qcom,boot-option = <0x1>; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,drv-supported; qcom,l1ss-sleep-disable = <0x1>; qcom,drv-l1ss-timeout-us = <5000>; @@ -328,6 +329,7 @@ <0x100 &apps_smmu 0x1c81 0x1>; qcom,boot-option = <0x1>; + qcom,aux-clk-freq = <20>; /* 19.2 MHz */ qcom,drv-supported; qcom,wr-halt-size = <0x8>; qcom,no-l0s-supported; From 697814b394b15dc53eb52fbaec9e2d811fdbce0f Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Tue, 27 Oct 2020 11:06:42 +0800 Subject: [PATCH 42/66] ARM: dts: msm: Add cti trigger number to device tree for lahaina Add cti trigger number to device tree for lahaina. Since some platforms don't have swao cti, replace configuring cti trigger number as hard code. Change-Id: I5ae1cc25210218f249ea8b34ee493e0b27fef237 --- qcom/lahaina-coresight.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/qcom/lahaina-coresight.dtsi b/qcom/lahaina-coresight.dtsi index 3342e9e9e0f5..ff7750e6f034 100644 --- a/qcom/lahaina-coresight.dtsi +++ b/qcom/lahaina-coresight.dtsi @@ -107,7 +107,9 @@ coresight-name = "coresight-tmc-etf"; coresight-csr = <&swao_csr>; - coresight-ctis = <&cti0 &cti6>; + coresight-ctis = <&cti0_swao &cti3_swao>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <1>; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; @@ -154,7 +156,9 @@ qcom,sw-usb; coresight-name = "coresight-tmc-etr"; - coresight-ctis = <&cti0 &cti6>; + coresight-ctis = <&cti0 &cti3_swao>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <3>; coresight-csr = <&csr>; clocks = <&clock_aop QDSS_CLK>; From c9a7ad232a9ea6df4312d2ba8a702d3ae0d8d4bf Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Tue, 27 Oct 2020 11:15:45 +0800 Subject: [PATCH 43/66] ARM: dts: msm: Add cti trigger number to device tree for holi Add cti trigger number to device tree for holi. Since some platforms don't have swao cti, replace configuring cti trigger number as hard code. Change-Id: Ibb96b02f966c765f8744a278bb6b6f18da2edd4c --- qcom/holi-coresight.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/holi-coresight.dtsi b/qcom/holi-coresight.dtsi index 95a7723749e2..817a8365d552 100644 --- a/qcom/holi-coresight.dtsi +++ b/qcom/holi-coresight.dtsi @@ -1959,6 +1959,9 @@ clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; coresight-ctis = <&cti0 &cti6>; + cti-reset-trig-num = <5>; + cti-flush-trig-num = <1>; + in-ports { port { tmc_etf_in_funnel_merge: endpoint { @@ -2039,6 +2042,8 @@ qcom,sw-usb; coresight-ctis = <&cti0 &cti6>; + cti-reset-trig-num = <5>; + cti-flush-trig-num = <3>; coresight-csr = <&csr>; interrupts = ; interrupt-names = "byte-cntr-irq"; From a949b458eaaf0afa4d2eaa1faf8c8f5a11607902 Mon Sep 17 00:00:00 2001 From: Prudhvi Yarlagadda Date: Tue, 27 Oct 2020 11:59:33 +0530 Subject: [PATCH 44/66] ARM: dts: msm: Add slimbus dtsi node for scuba Add slimbus dtsi node for scuba. Change-Id: I0ea801a7ac0fb697d45a32c015aeb32036eee864 --- qcom/scuba-iot.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi index bb28d23102ff..7ea545d63717 100644 --- a/qcom/scuba-iot.dtsi +++ b/qcom/scuba-iot.dtsi @@ -750,6 +750,21 @@ dcc: dcc_v2@1be2000 { #interrupt-cells = <2>; }; }; + + slim_aud: slim@a5c0000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0xa5c0000 0x2c000>, + <0xa584000 0x20000>, <0xa66e000 0x2000>; + reg-names = "slimbus_physical", + "slimbus_bam_physical","slimbus_lpass_mem"; + interrupts = , + ; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x0>; + qcom,ea-pc = <0x360>; + status = "ok"; + }; }; #include "pm2250.dtsi" From 44150e9089d3d119d79189f479f9ae60d5541707 Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Fri, 23 Oct 2020 14:51:18 +0530 Subject: [PATCH 45/66] ARM: dts: msm: Set emmc vdd-io regulator in NPM mode during sleep Set emmc vdd-io regulator in NPM mode during sleep to avoid OCP issue. This is done only for ATP platform. Change-Id: I32573627314dff29ef67d3bf3a8337c17f87d4db --- qcom/holi-atp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi-atp.dtsi b/qcom/holi-atp.dtsi index e16ecfc75980..974b08da18ae 100644 --- a/qcom/holi-atp.dtsi +++ b/qcom/holi-atp.dtsi @@ -21,7 +21,7 @@ qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; - qcom,vdd-io-current-level = <0 325000>; + qcom,vdd-io-current-level = <325000 325000>; }; &sdhc_2 { From 0bfa3e7d2065a1a5a03d4b48e09cac5570acf160 Mon Sep 17 00:00:00 2001 From: Laxminath Kasam Date: Tue, 20 Oct 2020 00:04:37 +0530 Subject: [PATCH 46/66] ARM: dts: qcom: add physical addr for swr tx slaves of Holi Add dt property to read physical addresses of TX soundwire master slaves of Holi. Change-Id: Id584ba30e2e62230dfb77f75958b7239b77a652f --- qcom/holi-audio-overlay.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/holi-audio-overlay.dtsi b/qcom/holi-audio-overlay.dtsi index 987572a7db74..238ccb951cd9 100644 --- a/qcom/holi-audio-overlay.dtsi +++ b/qcom/holi-audio-overlay.dtsi @@ -55,6 +55,11 @@ <3 SWRM_TX3_CH1 0x1>, <3 SWRM_TX3_CH2 0x2>, <3 SWRM_TX3_CH3 0x4>, <3 SWRM_TX3_CH4 0x8>; qcom,swr-num-dev = <1>; + qcom,swr-phy-dev-addr = <0x0A 0x01170223>, + <0x08 0x58350223>, + <0x08 0x58350222>, + <0x08 0x58350221>, + <0x08 0x58350220>; qcom,swr-clock-stop-mode0 = <1>; qcom,swr-mstr-irq-wakeup-capable = <1>; qcom,is-always-on = <1>; From e7a7ffd220373eef563f7d54ec5b4e4a1c7a6d42 Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Tue, 27 Oct 2020 10:07:28 -0700 Subject: [PATCH 47/66] ARM: dts: msm: Configure USB SMMU in atomic mode on sdxlemur Enable usb smmu in atomic mode by configuring the device tree setting on sdxlemur. Change-Id: Id5745e605eb242b1cb829e04de7bcb66af1958d0 --- qcom/sdxlemur-usb.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index 683efa443925..007c96f3e20f 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -7,7 +7,7 @@ reg-names = "core_base"; iommus = <&apps_smmu 0x1a0 0x0>; - qcom,iommu-dma = "bypass"; + qcom,iommu-dma = "atomic"; qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; #address-cells = <1>; #size-cells = <1>; From 0bd22990a564dd5b7da3c8087a8f91ea663ba253 Mon Sep 17 00:00:00 2001 From: Charan Teja Kalla Date: Tue, 18 Aug 2020 17:55:30 +0530 Subject: [PATCH 48/66] ARM: dts: msm: add smmu nodes on yupik Add SMMU device tree nodes, which is used by the clients for virtual to physical address transaltions, on yupik. Change-Id: Ia88dc0e18b530e364314f8468022519dd5dcf5e2 --- qcom/msm-arm-smmu-yupik.dtsi | 246 +++++++++++++++++++++++++++++++++++ qcom/yupik.dtsi | 5 + 2 files changed, 251 insertions(+) create mode 100644 qcom/msm-arm-smmu-yupik.dtsi diff --git a/qcom/msm-arm-smmu-yupik.dtsi b/qcom/msm-arm-smmu-yupik.dtsi new file mode 100644 index 000000000000..22ee8245eb6e --- /dev/null +++ b/qcom/msm-arm-smmu-yupik.dtsi @@ -0,0 +1,246 @@ +#include + +&soc { + kgsl_smmu: kgsl-smmu@3da0000 { + status = "disabled"; + compatible = "qcom,qsmmu-v500"; + reg = <0x3da0000 0x20000>, + <0x3dd6000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + #global-interrupts = <2>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + gfx_0_tbu: gfx_0_tbu@3dd9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3dd9000 0x1000>, + <0x3dd6200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + }; + + gfx_1_tbu: gfx_1_tbu@3ddd000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x3ddd000 0x1000>, + <0x3dd6208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + }; + + }; + + apps_smmu: apps-smmu@15000000 { + compatible = "qcom,qsmmu-v500"; + reg = <0x15000000 0x100000>, + <0x151da000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + #global-interrupts = <2>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + anoc_1_tbu: anoc_1_tbu@151dd000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151dd000 0x1000>, + <0x151da200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + }; + + anoc_2_tbu: anoc_2_tbu@151e1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151e1000 0x1000>, + <0x151da208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + }; + + mnoc_hf_0_tbu: mnoc_hf_0_tbu@151e5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151e5000 0x1000>, + <0x151da210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + }; + + mnoc_hf_1_tbu: mnoc_hf_1_tbu@151e9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151e9000 0x1000>, + <0x151da218 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0xc00 0x400>; + }; + + compute_dsp_1_tbu: compute_dsp_1_tbu@151ed000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151ed000 0x1000>, + <0x151da220 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1000 0x400>; + }; + + compute_dsp_0_tbu: compute_dsp_0_tbu@151f1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151f1000 0x1000>, + <0x151da228 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1400 0x400>; + }; + + adsp_tbu: adsp_tbu@151f5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151f5000 0x1000>, + <0x151da230 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1800 0x400>; + }; + + anoc_1_pcie_tbu: anoc_1_pcie_tbu@151f9000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151f9000 0x1000>, + <0x151da238 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x1c00 0x400>; + }; + + mnoc_sf_0_tbu: mnoc_sf_0_tbu@151fd000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x151fd000 0x1000>, + <0x151da240 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x2000 0x400>; + }; + }; + + kgsl_iommu_test_device { + status = "disabled"; + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x7 0>; + qcom,iommu-dma = "disabled"; + }; + + kgsl_iommu_coherent_test_device { + status = "disabled"; + compatible = "iommu-debug-test"; + iommus = <&kgsl_smmu 0x407 0>; + qcom,iommu-dma = "disabled"; + dma-coherent; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x0 0>; + qcom,iommu-dma = "disabled"; + }; + + apps_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + iommus = <&apps_smmu 0x1 0>; + qcom,iommu-dma = "disabled"; + dma-coherent; + }; +}; + diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index c07780c7eed8..f76e4684ff16 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1140,6 +1140,10 @@ mboxes = <&qmp_aop 0>; mbox-names = "aop"; }; + + qcom-secure-buffer { + compatible = "qcom,secure-buffer"; + }; }; #include "shima-gdsc.dtsi" @@ -1264,3 +1268,4 @@ }; #include "yupik-usb.dtsi" +#include "msm-arm-smmu-yupik.dtsi" From a574bcce71ec80aab53f1907c538743ad27dc0ec Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Fri, 23 Oct 2020 17:02:28 +0800 Subject: [PATCH 49/66] dt-bindings: arm: Add reset/flush CTI trigger number support Add binding document for configuring reset/flush CTI trigger number in device tree. Change-Id: I4052810ab6b31fb336d5d75bc88f349892fdf050 --- bindings/arm/coresight.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/bindings/arm/coresight.txt b/bindings/arm/coresight.txt index 1fadc1b562cc..8b5ff04914a5 100644 --- a/bindings/arm/coresight.txt +++ b/bindings/arm/coresight.txt @@ -137,6 +137,12 @@ its hardware characteristcs. * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely use the SG mode on this system. + * cti-reset-trig-num: Specifies the reset CTI trigger number for TMC + ETR and TMC ETF. + + * cti-flush-trig-num: Specifies the flush CTI trigger number for TMC + ETR and TMC ETF. + * Optional property for CATU and APSS : * interrupts : Exactly one SPI may be listed for reporting the address error for CATU and four interrupts for TGU to get trigger from four From ae7e54c0587be49920fa337dddee5f9c5811150f Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Wed, 28 Oct 2020 16:09:32 +0530 Subject: [PATCH 50/66] ARM: dts: msm: Add change for smmu memory optimizations This change enables smmu memory optimizations during smmu s1 enable for holi. Change-Id: Ie921ffd9b8df91474563d5171ad22df333a87a46 --- qcom/holi.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index a44459a09fe8..34fd9f97a15b 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2569,6 +2569,7 @@ qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal"; qcom,wlan-msa-fixed-region = <&pil_wlan_mem>; qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; + qcom,iommu-geometry = <0xa0000000 0x10010000>; vdd-cx-mx-supply = <&L4A>; vdd-1.8-xo-supply = <&L7A>; vdd-1.3-rfa-supply = <&L2E>; From f954a0cb57ae3307d0ea94047dab473a5345c012 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Thu, 22 Oct 2020 15:57:45 -0700 Subject: [PATCH 51/66] ARM: dts: msm: Add PMIC overlay to all sdxlemur platforms Add PMIC overlay to the board files of the complete range of sdxlemur platforms. Change-Id: Id7926f1b8c8cd77442f1afc3777bf7436ef95af8 --- qcom/sdxlemur-mtp-cpe.dtsi | 1 + qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 1 + qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi | 1 + qcom/sdxlemur-mtp-mbb.dtsi | 1 + qcom/sdxlemur-rcm-pcie-ep.dtsi | 1 + qcom/sdxlemur-rcm-rc.dtsi | 1 + 6 files changed, 6 insertions(+) diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi index cc3a833f430e..768d9aaa521c 100644 --- a/qcom/sdxlemur-mtp-cpe.dtsi +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -1,3 +1,4 @@ +#include "sdxlemur-pmic-overlay.dtsi" &soc { diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi index cc3a833f430e..768d9aaa521c 100644 --- a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -1,3 +1,4 @@ +#include "sdxlemur-pmic-overlay.dtsi" &soc { diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi index cc3a833f430e..768d9aaa521c 100644 --- a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi @@ -1,3 +1,4 @@ +#include "sdxlemur-pmic-overlay.dtsi" &soc { diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index 7b1f8063b8e6..7bfdc0e951d3 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -1,3 +1,4 @@ +#include "sdxlemur-pmic-overlay.dtsi" &soc { diff --git a/qcom/sdxlemur-rcm-pcie-ep.dtsi b/qcom/sdxlemur-rcm-pcie-ep.dtsi index cc3a833f430e..768d9aaa521c 100644 --- a/qcom/sdxlemur-rcm-pcie-ep.dtsi +++ b/qcom/sdxlemur-rcm-pcie-ep.dtsi @@ -1,3 +1,4 @@ +#include "sdxlemur-pmic-overlay.dtsi" &soc { diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 7b1f8063b8e6..7bfdc0e951d3 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -1,3 +1,4 @@ +#include "sdxlemur-pmic-overlay.dtsi" &soc { From 826180ecb6bcce2522cabe0026a231218ad4da06 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Thu, 22 Oct 2020 16:48:30 -0700 Subject: [PATCH 52/66] ARM: dts: msm: Add PM7250B to select sdxlemur boards Add PM7250B to MBB and RCM-RC boards. Change-Id: I5ea24325a31c6ed89b1f90f12a332ba26d7ffc17 --- qcom/sdxlemur-mtp-mbb.dtsi | 6 ++++++ qcom/sdxlemur-rcm-rc.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi index 7bfdc0e951d3..7e5f6471cab7 100644 --- a/qcom/sdxlemur-mtp-mbb.dtsi +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -1,4 +1,10 @@ #include "sdxlemur-pmic-overlay.dtsi" +#include "pm7250b.dtsi" + +&pm7250b_clkdiv { + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; +}; &soc { diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi index 7bfdc0e951d3..7e5f6471cab7 100644 --- a/qcom/sdxlemur-rcm-rc.dtsi +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -1,4 +1,10 @@ #include "sdxlemur-pmic-overlay.dtsi" +#include "pm7250b.dtsi" + +&pm7250b_clkdiv { + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; +}; &soc { From 504fe96b700c5f96007e5a0fc214073029f9eda7 Mon Sep 17 00:00:00 2001 From: Paras Sharma Date: Mon, 21 Sep 2020 12:38:24 +0530 Subject: [PATCH 53/66] ARM: dts: msm: Add QUPv3_0 and SE5 dt nodes for YUPIK Add QUPv3_0 device tree change for console UART on yupik. Change-Id: I9d0af197eda7c784aea127a5cc8848674d3c81fa --- qcom/yupik-pinctrl.dtsi | 28 ++++++++++++++++++++++++++++ qcom/yupik-qupv3.dtsi | 35 +++++++++++++++++++++++++++++++++++ qcom/yupik-rumi.dtsi | 5 +++++ qcom/yupik.dtsi | 1 + 4 files changed, 69 insertions(+) create mode 100644 qcom/yupik-qupv3.dtsi diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index baa6f7f738b5..01404eb41ded 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -8,5 +8,33 @@ interrupt-controller; #interrupt-cells = <2>; wakeup-parent = <&pdc>; + + qupv3_se5_2uart_pins: qupv3_se5_2uart_pins { + qupv3_se5_2uart_active: qupv3_se5_2uart_active { + mux { + pins = "gpio22", "gpio23"; + function = "qup05"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se5_2uart_sleep: qupv3_se5_2uart_sleep { + mux { + pins = "gpio22", "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; }; }; diff --git a/qcom/yupik-qupv3.dtsi b/qcom/yupik-qupv3.dtsi new file mode 100644 index 000000000000..a593d4406eda --- /dev/null +++ b/qcom/yupik-qupv3.dtsi @@ -0,0 +1,35 @@ +#include + +&soc { + /* QUPv3_0 wrapper instance */ + qupv3_0: qcom,qupv3_0_geni_se@9c0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x9c0000 0x2000>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-bus-ids = + , + ; + iommus = <&apps_smmu 0x123 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>; + qcom,iommu-geometry = <0x40000000 0x10000000>; + qcom,iommu-dma = "fastmap"; + status = "ok"; + }; + + /* Debug UART Instance */ + qupv3_se5_2uart: qcom,qup_uart@994000 { + compatible = "qcom,msm-geni-console"; + reg = <0x994000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se5_2uart_active>; + pinctrl-1 = <&qupv3_se5_2uart_sleep>; + qcom,wrapper-core = <&qupv3_0>; + status = "ok"; + }; +}; diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index a7544916452f..1efb6b32bfaa 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -70,3 +70,8 @@ status = "ok"; }; + +/* Debug UART console */ +&qupv3_se5_2uart { + qcom,rumi_platform; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index f76e4684ff16..8b749d15d51f 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1269,3 +1269,4 @@ #include "yupik-usb.dtsi" #include "msm-arm-smmu-yupik.dtsi" +#include "yupik-qupv3.dtsi" From 713fb502ade8fc525bc0477e20c3aaf76fb4d83f Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Thu, 8 Oct 2020 16:38:04 +0530 Subject: [PATCH 54/66] Revert "ARM: dts: msm: Add new DT entry for wan agg pkt size" This reverts commit 8bfb55bada068d97584c93ed9a95322f0df9720a. Change-Id: Ia33a38ba96893ca6c08d27c0f40852256b474aca --- qcom/shima.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index ca7fbbd667ae..4ff893da146a 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3725,8 +3725,6 @@ qcom,ipa-holb-monitor-max-cnt-usb = <10>; qcom,ipa-holb-monitor-max-cnt-11ad = <10>; qcom,tx-wrapper-cache-max-size = <400>; - /* Entry will be removed once shadow stack changes checked-in */ - qcom,ipa-wan-aggr-pkt-cnt = <2>; qcom,ipa-gpi-event-rp-ddr; clock-names = "core_clk"; clocks = <&rpmhcc RPMH_IPA_CLK>; From 12d8efb1bcdfcee57b78fd26dbae88998229bdac Mon Sep 17 00:00:00 2001 From: Charan Teja Kalla Date: Tue, 27 Oct 2020 15:03:42 +0530 Subject: [PATCH 55/66] ARM: dts: msm: add system ion heaps on yupik Add the system and system secure ion heaps on yupik. Change-Id: Icb1b6ebfbb92627b411d8404f60c4d101dba5ffa --- qcom/yupik-ion.dtsi | 20 ++++++++++++++++++++ qcom/yupik.dtsi | 1 + 2 files changed, 21 insertions(+) create mode 100644 qcom/yupik-ion.dtsi diff --git a/qcom/yupik-ion.dtsi b/qcom/yupik-ion.dtsi new file mode 100644 index 000000000000..c10aa1385e0e --- /dev/null +++ b/qcom/yupik-ion.dtsi @@ -0,0 +1,20 @@ +#include + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = ; + qcom,ion-heap-type = "MSM_SYSTEM"; + }; + + system_secure_heap: qcom,ion-heap@9 { + reg = ; + qcom,ion-heap-type = "SYSTEM_SECURE"; + }; + }; +}; + diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index f76e4684ff16..decd47425e54 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -1268,4 +1268,5 @@ }; #include "yupik-usb.dtsi" +#include "yupik-ion.dtsi" #include "msm-arm-smmu-yupik.dtsi" From a72b061a3b34a29f7d66afad8588e028f0185187 Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Fri, 30 Oct 2020 15:42:04 +0530 Subject: [PATCH 56/66] ARM: dts: msm: Update PCIe LDO clock from CXO to CXO_A LDO votes CXO clock in WLAN IMPS mode which causes CXO clock is always turned on, So changing PCIe LDO clock from CXO to CXO_A. Change-Id: I6b0ad98be2017e58e133751baa3febd69c77e83d --- qcom/shima-pcie.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index 32573d6def76..fce90dee366f 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -67,7 +67,7 @@ <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, From ccdcabbb381169377b87ee77b20bfe7ddf9c71ef Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Wed, 28 Oct 2020 17:21:50 +0800 Subject: [PATCH 57/66] ARM: dts: msm: disable GPU funnel The GPU funnel related clk cannot be voted on from kernel side, so disable it. Change-Id: I82914c8f9d37187943854822cac50b77df4632a7 --- qcom/holi-coresight.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi-coresight.dtsi b/qcom/holi-coresight.dtsi index 817a8365d552..75f31bf5d45e 100644 --- a/qcom/holi-coresight.dtsi +++ b/qcom/holi-coresight.dtsi @@ -1134,7 +1134,7 @@ clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; - + status = "disabled"; out-ports { port { funnel_gpu_out_tpda_center2: endpoint { From 26695258093b6eacba9ed761c3a8edb96411fa9c Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Wed, 21 Oct 2020 23:17:22 +0530 Subject: [PATCH 58/66] ARM: dts: qcom: Enable TSENS driver support for sdxlemur Enable TSENS devicetree details and user_space thermal zone configurations for all TSENS for sdxlemur. Change-Id: I992d4836cccc1d30cfb6fd2c9887a4083729c868 --- qcom/sdxlemur-thermal.dtsi | 155 +++++++++++++++++++++++++++++++++++++ qcom/sdxlemur.dtsi | 1 + 2 files changed, 156 insertions(+) create mode 100644 qcom/sdxlemur-thermal.dtsi diff --git a/qcom/sdxlemur-thermal.dtsi b/qcom/sdxlemur-thermal.dtsi new file mode 100644 index 000000000000..3aed3255d650 --- /dev/null +++ b/qcom/sdxlemur-thermal.dtsi @@ -0,0 +1,155 @@ +&soc { + tsens0: tsens@c222000 { + compatible = "qcom,tsens24xx"; + reg = <0xc222000 0x152>, + <0xc263000 0x1ff>; + reg-names = "tsens_srot_physical", + "tsens_tm_physical"; + interrupts = , + ; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + #thermal-sensor-cells = <1>; + }; +}; + +&thermal_zones { + aoss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 0>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 1>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmq6-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-0-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 3>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 4>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 5>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mdmss-3-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&tsens0 6>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; +}; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 4bbf2a3f6d1e..b89428868f9a 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -921,3 +921,4 @@ #include "sdxlemur-pcie.dtsi" #include "sdxlemur-blsp.dtsi" #include "sdxlemur-audio.dtsi" +#include "sdxlemur-thermal.dtsi" From 55d3df1c6075665b6e9feb65d648edcd575d4614 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 30 Oct 2020 15:32:48 +0530 Subject: [PATCH 59/66] ARM: dts: msm: Add acd registers for HOLI The GPU GX GDSC requires the ACD block/misc resets during GDSC power-up/down sequence, thus add the register offsets. Change-Id: Ica77fa0a270186ecdbafb4e8d0888ef0b81613bf --- qcom/holi-gdsc.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/holi-gdsc.dtsi b/qcom/holi-gdsc.dtsi index 5e2346aab191..14ad80e17363 100644 --- a/qcom/holi-gdsc.dtsi +++ b/qcom/holi-gdsc.dtsi @@ -97,6 +97,16 @@ reg = <0x5991008 0x4>; }; + gpu_gx_acd_reset: syscon@5991160 { + compatible = "syscon"; + reg = <0x5991160 0x4>; + }; + + gpu_gx_acd_misc_reset: syscon@5998004 { + compatible = "syscon"; + reg = <0x5998004 0x4>; + }; + gpu_cx_gdsc: qcom,gdsc@599106c { compatible = "qcom,gdsc"; reg = <0x599106c 0x4>; @@ -113,6 +123,8 @@ reg = <0x599100c 0x4>; regulator-name = "gpu_gx_gdsc"; sw-reset = <&gpu_gx_sw_reset>; + acd-reset = <&gpu_gx_acd_reset>; + acd-misc-reset = <&gpu_gx_acd_misc_reset>; domain-addr = <&gpu_gx_domain_addr>; qcom,reset-aon-logic; status = "disabled"; From 323a118d1d50f3dd133d2849f3218509265bf0c0 Mon Sep 17 00:00:00 2001 From: Asutosh Das Date: Mon, 2 Nov 2020 15:33:37 -0800 Subject: [PATCH 60/66] ARM: dts: msm: Keep default PM level setting for Lahaina The default settings are rpm-level = spm-level = 3. This translates to UFS_SLEEP_PWR_MODE & UIC_LINK_HIBERN8_STATE. Change-Id: I9c08875d193fbefe0846f53e8b95dd6e840485de --- qcom/lahaina.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 5a1ef7f0b987..692570e8d2bf 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -3148,9 +3148,6 @@ qcom,iommu-dma = "fastmap"; dma-coherent; - rpm-level = <3>; - spm-level = <5>; - status = "disabled"; qos0 { mask = <0xf0>; From 2c849413fa52991c25dbb38ea6f10644fc42aaed Mon Sep 17 00:00:00 2001 From: Bojun Pan Date: Mon, 2 Nov 2020 16:20:26 -0800 Subject: [PATCH 61/66] ARM: dts: msm: Disable dma-coherent for IPA CBs on SDXLEMUR DMA coherent is not required for MDM target. Change-Id: I9c115bbab9bdecc5573dbc2a264faff7da5f9e77 --- qcom/sdxlemur.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 06dcaf8c5ba6..e76f65c09b46 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -750,7 +750,6 @@ qcom,additional-mapping = /* modem tables in IMEM */ <0x14688000 0x14688000 0x3000>; - dma-coherent; qcom,iommu-dma = "fastmap"; qcom,ipa-q6-smem-size = <36864>; }; @@ -758,7 +757,6 @@ ipa_smmu_wlan: ipa_smmu_wlan { compatible = "qcom,ipa-smmu-wlan-cb"; iommus = <&apps_smmu 0x5E1 0x0>; - dma-coherent; qcom,iommu-dma = "atomic"; }; @@ -772,7 +770,6 @@ ipa_smmu_11ad: ipa_smmu_11ad { compatible = "qcom,ipa-smmu-11ad-cb"; iommus = <&apps_smmu 0x5E3 0x0>; - dma-coherent; qcom,shared-cb; qcom,iommu-group = <>; }; From 75d2c9ac76ef682404f1f3f4cb73007d0d4639e4 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Fri, 23 Oct 2020 16:16:35 +0530 Subject: [PATCH 62/66] ARM: dts: msm: Add CX and MX SDPM configuration for SHIMA Add CX SDPM configuration to monitor Camera, UFS clocks for SHIMA. Add MX SDPM configuration to monitor Camera, Video, and other misc clocks for SHIMA. Change-Id: I2d38c7d48cf4b05198f924dccb7b2858d679e6a6 --- qcom/shima-thermal.dtsi | 146 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 146 insertions(+) diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index 73aa20666ae0..25d67c087505 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -64,6 +64,44 @@ "msm_skin_therm"; }; }; + + mx_sdpm@0x00636000 { + compatible = "qcom,sdpm"; + reg = <0x00636000 0x1000>; + clock-names = "cam_cc_ipe", "video_cc_mvs0"; + clocks = <&camcc CAM_CC_IPE_0_CLK_SRC>, + <&videocc VIDEO_CC_MVS0_CLK_SRC>; + cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>; + video_cc_mvs0-supply = <&video_cc_mvs0_gdsc>; + csr-id = <1 3>; + }; + + cx_sdpm@0x00634000 { + compatible = "qcom,sdpm"; + reg = <0x00634000 0x1000>; + clock-names = "cam_cc_csi0phytiimer", "video_cc_mvs0", "disp_cc_mdss_mdp"; + clocks = <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&videocc VIDEO_CC_MVS0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + cam_cc_csi0phytiimer-supply = <&cam_cc_titan_top_gdsc>; + video_cc_mvs0-supply = <&video_cc_mvs0_gdsc>; + disp_cc_mdss-mdp-supply = <&disp_cc_mdss_core_gdsc>; + csr-id = <0 2 5>; + }; + + mx_pe: mx_rdpm_pe@0x00637000 { + compatible = "qcom,policy-engine"; + #thermal-sensor-cells = <0>; + reg = <0x00637000 0x1000>; + interrupts = ; + }; + + cx_pe: cx_rdpm_pe@0x00635000 { + compatible = "qcom,policy-engine"; + #thermal-sensor-cells = <0>; + reg = <0x00635000 0x1000>; + interrupts = ; + }; }; &cpufreq_hw { @@ -1366,4 +1404,112 @@ }; }; }; + + mx-pe-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&mx_pe>; + thermal-governor = "step_wise"; + trips { + mx_pe_config1: mx-pe-config1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + + mx_pe_config2: mx-pe-config2 { + temperature = <2>; + hysteresis = <1>; + type = "passive"; + }; + + mx_pe_config3: mx-pe-config3 { + temperature = <3>; + hysteresis = <1>; + type = "passive"; + }; + }; + + cooling-maps { + mx_pe_cdev_1 { + trip = <&mx_pe_config1>; + cooling-device = <&cdsp_sw 0 0>; + }; + + mx_pe_cdev_2 { + trip = <&mx_pe_config2>; + cooling-device = <&msm_gpu 0 0>; + }; + + mx_pe_cdev_3 { + trip = <&mx_pe_config3>; + cooling-device = <&modem_tj 0 0>; + }; + }; + }; + + cx-pe-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&cx_pe>; + thermal-governor = "step_wise"; + trips { + cx_pe_config1: cx-pe-config1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config2: cx-pe-config2 { + temperature = <2>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config3: cx-pe-config3 { + temperature = <3>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config4: cx-pe-config4 { + temperature = <4>; + hysteresis = <1>; + type = "passive"; + }; + + cx_pe_config5: cx-pe-config5 { + temperature = <5>; + hysteresis = <2>; + type = "passive"; + }; + }; + + cooling-maps { + cx_pe_cdev_1 { + trip = <&cx_pe_config1>; + cooling-device = <&cdsp_sw 0 0>; + }; + + cx_pe_cdev_2 { + trip = <&cx_pe_config2>; + cooling-device = <&cdsp_sw 0 0>; + }; + + cx_pe_cdev_3 { + trip = <&cx_pe_config3>; + cooling-device = <&cdsp_sw 0 0>; + }; + + cx_pe_cdev_4 { + trip = <&cx_pe_config4>; + cooling-device = <&modem_tj 0 0>; + }; + + cx_pe_cdev_5 { + trip = <&cx_pe_config5>; + cooling-device = <&cdsp_sw 0 0>; + }; + }; + }; }; From 5e679a8be0020455b6b8a0d34dd82c1bd9173729 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 3 Nov 2020 17:50:55 +0530 Subject: [PATCH 63/66] ARM: dts: msm: Add configuration for vref regulator vote for SHIMA Add regulator configuration for vref regulators so that LMH driver can place a active only vote for shima. Change-Id: I67ffdf7cac820ddcc81b901d4652c4f44aa8fdaf --- qcom/shima-thermal.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index 25d67c087505..0568cabd69b5 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -191,6 +191,14 @@ }; }; + qcom,limits-dcvs { + compatible = "qcom,msm-hw-limits"; + isens_vref_0p8-supply = <&pm8350c_l10_ao>; + isens-vref-0p8-settings = <880000 880000 30000>; + isens_vref_1p8-supply = <&pm8350c_l1_ao>; + isens-vref-1p8-settings = <1800000 1800000 20000>; + }; + qcom,cpu-voltage-cdev { compatible = "qcom,cc-cooling-devices"; apc1_cluster: qcom,apc1-cluster { From 91c737ada2aa41881e124c95cb16364abc37232f Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 15 Oct 2020 12:06:50 +0530 Subject: [PATCH 64/66] ARM: dts: msm: Add cphy video/cmd mode touch support on shima Add cphy video/cmd mode touch support on shima target. Change-Id: I7a089bc246b428c79adb3e09cf94c357e8447a65 --- qcom/shima-idp.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index b02db7983bda..61ac7628134b 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -189,7 +189,9 @@ &dsi_r66451_amoled_video &dsi_r66451_amoled_60hz_video &dsi_r66451_amoled_60hz_cmd - &dsi_r66451_amoled_144hz_cmd>; + &dsi_r66451_amoled_144hz_cmd + &dsi_r66451_amoled_video_cphy + &dsi_r66451_amoled_cmd_cphy>; focaltech,trusted-touch-mode = "vm_mode"; focaltech,touch-environment = "pvm"; From 2432f0dd54d19ff6bb2287ce20037431cf85e50f Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Thu, 15 Oct 2020 13:57:29 +0530 Subject: [PATCH 65/66] ARM: dts: msm: Enable touch for Dual DSI panel on shima Enable touch for Dual DSI panel on shima. Change-Id: Icb198d7831b1932b199c0e680af0f32c72f0913f --- qcom/shima-idp.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index 61ac7628134b..9b4e69e21615 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -199,6 +199,27 @@ focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x988000 0x00910000>; focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; }; + + atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + interrupt-parent = <&tlmm>; + interrupts = <23 0x2008>; + avdd-supply = <&L3C>; + vdd-supply = <&L8C>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + atmel,xy_switch; + atmel,inverty; + atmel,invertx; + reset-gpios = <&tlmm 22 0x00>; + irq-gpios = <&tlmm 23 0x2008>; + atmel,panel-coords = <0 0 479 799>; + atmel,display-coords = <0 0 339 729>; + panel = <&dsi_sharp_qhd_plus_dsc_cmd>; + }; }; &dai_mi2s2 { From 68591d577880af21d196b8c0db04b4073d3c81d1 Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Wed, 4 Nov 2020 12:41:48 +0800 Subject: [PATCH 66/66] ARM: dts: msm: adjust pm6150a_l1 initial voltage for Holi platforms Set pm6150a_l1 initial voltage to 1.8V by default and set it to 1.86V specific for Holi QRD platform to meet the display panel power requirement. Change-Id: I19beed5a3025a3e96653a4762ab8c2d73b7a0068 --- qcom/holi-qrd.dtsi | 4 ++++ qcom/holi-regulators.dtsi | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index 51c11a11dd60..5811c29a8d04 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -232,6 +232,10 @@ }; }; +&pm6150a_l1 { + qcom,init-voltage = <1860000>; +}; + &pm6150a_amoled { status = "ok"; }; diff --git a/qcom/holi-regulators.dtsi b/qcom/holi-regulators.dtsi index df74687f3251..1e5ef3a2bf65 100644 --- a/qcom/holi-regulators.dtsi +++ b/qcom/holi-regulators.dtsi @@ -459,7 +459,7 @@ L1E: pm6150a_l1: regulator-l1 { regulator-min-microvolt = <1650000>; regulator-max-microvolt = <1980000>; - qcom,init-voltage = <1650000>; + qcom,init-voltage = <1800000>; qcom,proxy-consumer-enable; qcom,proxy-consumer-current = <62000>; status = "okay";