From eec5318ae8d0755ea89e4a866efc875eab1be12c Mon Sep 17 00:00:00 2001 From: Jack Pham Date: Tue, 28 Jan 2020 12:45:18 -0800 Subject: [PATCH] ARM: dts: msm: Add interconnects to USB on Lahaina Specify the interconnect paths for the USB devices on Lahaina. Change-Id: Ic2cdb7e2f143ba73f01e48aa57972cbc98f4ff7e --- qcom/lahaina-usb.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi index e94628ce378c..97c4385d779f 100644 --- a/qcom/lahaina-usb.dtsi +++ b/qcom/lahaina-usb.dtsi @@ -47,6 +47,11 @@ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>; + dwc3@a600000 { compatible = "snps,dwc3"; reg = <0xa600000 0xcd00>; @@ -350,6 +355,11 @@ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_1 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_USB3_1 &config_noc SLAVE_IPA_CFG>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>; + dwc3@a800000 { compatible = "snps,dwc3"; reg = <0xa800000 0xcd00>;