From 7149f8914feadda406888f029c8adf673830e47c Mon Sep 17 00:00:00 2001 From: Can Guo Date: Wed, 28 Apr 2021 20:51:59 -0700 Subject: [PATCH] msm: ep-pcie: Give BAR0 and BAR2 the right size dev->mmio_res_size is not initialized, so during D3_COLD -> D0 transition, when the driver re-initializes the BAR registers, they are overwritten by dev->mmio_res_size. Fix it by calculating the size of MMIO resource and using the calculated size in ep_pcie_bar_init(). Change-Id: Ifad54ed1ffbcf205e89f9ab6d54e54350d5e7788 Signed-off-by: Can Guo --- drivers/platform/msm/ep_pcie/ep_pcie_com.h | 1 - drivers/platform/msm/ep_pcie/ep_pcie_core.c | 9 +++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_com.h b/drivers/platform/msm/ep_pcie/ep_pcie_com.h index 7776b6bae902..4445153d0977 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_com.h +++ b/drivers/platform/msm/ep_pcie/ep_pcie_com.h @@ -330,7 +330,6 @@ struct ep_pcie_dev_t { struct ep_pcie_irq_info_t irq[EP_PCIE_MAX_IRQ]; struct ep_pcie_res_info_t res[EP_PCIE_MAX_RES]; - u32 mmio_res_size; void __iomem *parf; void __iomem *phy; void __iomem *mmio; diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_core.c b/drivers/platform/msm/ep_pcie/ep_pcie_core.c index 59068faa1b77..20b2df67c039 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_core.c +++ b/drivers/platform/msm/ep_pcie/ep_pcie_core.c @@ -528,16 +528,18 @@ static void ep_pcie_pipe_clk_deinit(struct ep_pcie_dev_t *dev) static void ep_pcie_bar_init(struct ep_pcie_dev_t *dev) { + struct resource *res = dev->res[EP_PCIE_RES_MMIO].resource; + u32 mask = res->end - res->start; u32 properties = 0x4; EP_PCIE_DBG(dev, "PCIe V%d: BAR mask to program is 0x%x\n", - dev->rev, dev->mmio_res_size); + dev->rev, mask); /* Configure BAR mask via CS2 */ ep_pcie_write_mask(dev->elbi + PCIE20_ELBI_CS2_ENABLE, 0, BIT(0)); - ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0, dev->mmio_res_size); + ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0, mask); ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0 + 0x4, 0); - ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0 + 0x8, dev->mmio_res_size); + ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0 + 0x8, mask); ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0 + 0xc, 0); ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0 + 0x10, 0); ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0 + 0x14, 0); @@ -1294,7 +1296,6 @@ static int ep_pcie_get_resources(struct ep_pcie_dev_t *dev, goto out; } } - dev->mmio_res_size = res->end = res->start; } else { EP_PCIE_DBG(dev, "start addr for %s is %pa\n", res_info->name, &res->start);