From 7296789b5ef958b43dad737ce4b940a12ebce481 Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Wed, 10 Mar 2021 19:39:11 +0530 Subject: [PATCH 01/11] msm: ipa3: Adding BW monitor and QUOTA support for yupik target Adding FnR stats, BW monitor and QUOTA support for yupik target. Change-Id: If9b2b2480bb7ece08d906b06b676f63e1e778a2c Signed-off-by: Ashok Vuyyuru --- drivers/platform/msm/ipa/ipa_v3/ipa.c | 42 +++++++++++++++++++- drivers/platform/msm/ipa/ipa_v3/ipa_i.h | 8 +++- drivers/platform/msm/ipa/ipa_v3/ipa_uc.c | 38 +++++++++++++----- drivers/platform/msm/ipa/ipa_v3/ipa_utils.c | 16 ++++---- drivers/platform/msm/ipa/ipa_v3/ipa_wdi3_i.c | 7 ++-- drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c | 7 ++-- 6 files changed, 93 insertions(+), 25 deletions(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c index 40aab9eee4c4..1fea493f24c6 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #include @@ -1866,6 +1866,7 @@ static long ipa3_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) size_t sz; int pre_entry; int hdl; + u32 hw_feature_support = 0; IPADBG("cmd=%x nr=%d\n", cmd, _IOC_NR(cmd)); @@ -3080,7 +3081,24 @@ static long ipa3_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) retval = ipa3_app_clk_vote( (enum ipa_app_clock_vote_type) arg); break; + case IPA_IOC_GET_HW_FEATURE_SUPPORT: + pyld_sz = sizeof(u32); + /*Add new HW feature support to sent to userspace*/ + hw_feature_support |= (ipa3_ctx->is_eth_bridging_supported << + ETH_BRIDGING_SUPPORT); + param = kmemdup(&hw_feature_support, pyld_sz, + GFP_KERNEL); + if (!param) { + retval = -ENOMEM; + break; + } + if (copy_to_user((void __user *)arg, param, pyld_sz)) { + retval = -EFAULT; + break; + } + + break; default: IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); return -ENOTTY; @@ -7166,6 +7184,9 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p, } ipa3_ctx->ipa_endp_delay_wa = resource_p->ipa_endp_delay_wa; ipa3_ctx->ipa_endp_delay_wa_v2 = resource_p->ipa_endp_delay_wa_v2; + ipa3_ctx->is_eth_bridging_supported = + resource_p->is_eth_bridging_supported; + ipa3_ctx->is_bw_monitor_supported = resource_p->is_bw_monitor_supported; WARN(ipa3_ctx->ipa3_hw_mode != IPA_HW_MODE_NORMAL, "Non NORMAL IPA HW mode, is this emulation platform ?"); @@ -7914,6 +7935,8 @@ static int get_ipa_dts_configuration(struct platform_device *pdev, ipa_drv_res->manual_fw_load = false; ipa_drv_res->max_num_smmu_cb = IPA_SMMU_CB_MAX; ipa_drv_res->ipa_endp_delay_wa_v2 = false; + ipa_drv_res->is_eth_bridging_supported = false; + ipa_drv_res->is_bw_monitor_supported = false; /* Get IPA HW Version */ result = of_property_read_u32(pdev->dev.of_node, "qcom,ipa-hw-ver", @@ -8013,6 +8036,23 @@ static int get_ipa_dts_configuration(struct platform_device *pdev, ipa_drv_res->ipa_endp_delay_wa_v2 ? "True" : "False"); + if (of_property_read_bool(pdev->dev.of_node, + "qcom,eth-bridging-not-supported")) + ipa_drv_res->is_eth_bridging_supported = false; + else + ipa_drv_res->is_eth_bridging_supported = true; + + IPADBG(": ETH bridging supported = %s\n", + ipa_drv_res->is_eth_bridging_supported + ? "True" : "False"); + + ipa_drv_res->is_bw_monitor_supported = + of_property_read_bool(pdev->dev.of_node, + "qcom,bw-monitor-supported"); + + IPADBG(": BW Monitor and QUOTA stats supported = %s\n", + ipa_drv_res->is_bw_monitor_supported + ? "True" : "False"); ipa_drv_res->ipa_wdi3_over_gsi = of_property_read_bool(pdev->dev.of_node, diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h index a8b1094a8a1f..bee9c53054a0 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #ifndef _IPA3_I_H_ @@ -1951,6 +1951,8 @@ struct ipa3_app_clock_vote { * @manual_fw_load: bool,if fw load is done manually * @max_num_smmu_cb: number of smmu s1 cb supported * @ipa_config_is_auto: flag to indicate auto config + * @is_eth_bridging_supported: Flag to check eth bridging supported or not + * @is_bw_monitor_supported: Flag to check BW monitor supported or not. */ struct ipa3_context { struct ipa3_char_device_context cdev; @@ -2147,6 +2149,8 @@ struct ipa3_context { u32 num_smmu_cb_probed; u32 max_num_smmu_cb; bool ipa_endp_delay_wa_v2; + bool is_eth_bridging_supported; + bool is_bw_monitor_supported; }; struct ipa3_plat_drv_res { @@ -2216,6 +2220,8 @@ struct ipa3_plat_drv_res { bool ipa_config_is_auto; u32 max_num_smmu_cb; bool ipa_endp_delay_wa_v2; + bool is_eth_bridging_supported; + bool is_bw_monitor_supported; }; /** diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_uc.c b/drivers/platform/msm/ipa/ipa_v3/ipa_uc.c index f68246c851ad..9baf455257d1 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_uc.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_uc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #include "ipa_i.h" @@ -98,6 +98,10 @@ enum ipa3_cpu_2_hw_commands { FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 19), IPA_CPU_2_HW_CMD_DISABLE_HOLB_MONITOR = FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 20), + IPA_CPU_2_HW_CMD_QUOTA_MONITORING_YUPIK = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 21), + IPA_CPU_2_HW_CMD_BW_MONITORING_YUPIK = + FEATURE_ENUM_VAL(IPA_HW_FEATURE_COMMON, 22), }; /** @@ -1574,6 +1578,7 @@ int ipa3_uc_quota_monitor(uint64_t quota) struct ipa_mem_buffer cmd; struct IpaQuotaMonitoring_t *quota_info; + IPADBG("Enter\n"); cmd.size = sizeof(*quota_info); cmd.base = dma_alloc_coherent(ipa3_ctx->uc_pdev, cmd.size, &cmd.phys_base, GFP_KERNEL); @@ -1608,11 +1613,17 @@ int ipa3_uc_quota_monitor(uint64_t quota) IPA_UC_MON_INTERVAL; IPA_ACTIVE_CLIENTS_INC_SIMPLE(); - res = ipa3_uc_send_cmd((u32)(cmd.phys_base), - IPA_CPU_2_HW_CMD_QUOTA_MONITORING, - IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS, - false, 10 * HZ); + if (ipa3_ctx->ipa_hw_type != IPA_HW_v4_11) { + res = ipa3_uc_send_cmd((u32)(cmd.phys_base), + IPA_CPU_2_HW_CMD_QUOTA_MONITORING, + IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS, + false, 10 * HZ); + } else { + res = ipa3_uc_send_cmd((u32)(cmd.phys_base), + IPA_CPU_2_HW_CMD_QUOTA_MONITORING_YUPIK, 0, + false, 10 * HZ); + } if (res) { IPAERR(" faile to set quota %d, number offset %d\n", quota_info->params.WdiQM.Quota, @@ -1630,6 +1641,7 @@ free_cmd: dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base); IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + IPADBG("Exit\n"); return res; } @@ -1638,6 +1650,7 @@ int ipa3_uc_bw_monitor(struct ipa_wdi_bw_info *info) int i, ind, res = 0; struct ipa_mem_buffer cmd; struct IpaBwMonitoring_t *bw_info; + IPADBG("Enter\n"); if (!info) return -EINVAL; @@ -1712,10 +1725,16 @@ int ipa3_uc_bw_monitor(struct ipa_wdi_bw_info *info) IPA_ACTIVE_CLIENTS_INC_SIMPLE(); - res = ipa3_uc_send_cmd((u32)(cmd.phys_base), - IPA_CPU_2_HW_CMD_BW_MONITORING, - IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS, - false, 10 * HZ); + if (ipa3_ctx->ipa_hw_type != IPA_HW_v4_11) { + res = ipa3_uc_send_cmd((u32)(cmd.phys_base), + IPA_CPU_2_HW_CMD_BW_MONITORING, + IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS, + false, 10 * HZ); + } else { + res = ipa3_uc_send_cmd((u32)(cmd.phys_base), + IPA_CPU_2_HW_CMD_BW_MONITORING_YUPIK, 0, + false, 10 * HZ); + } if (res) { IPAERR(" faile to set bw %d level with %d coutners\n", @@ -1728,6 +1747,7 @@ free_cmd: dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base); IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); + IPADBG("Exit\n"); return res; } diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c index 4758fd2c7d8a..4d00cf315deb 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #include @@ -3994,14 +3994,14 @@ static struct ipa3_mem_partition ipa_4_11_mem_part = { .apps_hdr_proc_ctx_size = 0x200, .apps_hdr_proc_ctx_size_ddr = 0x0, .nat_tbl_ofst = 0x17A0, - .nat_tbl_size = 0x800, - .pdn_config_ofst = 0x24A8, + .nat_tbl_size = 0x500, + .pdn_config_ofst = 0x1CA8, .pdn_config_size = 0x50, - .stats_quota_q6_ofst = 0x2500, + .stats_quota_q6_ofst = 0x1D00, .stats_quota_q6_size = 0x30, - .stats_quota_ap_ofst = 0x2530, + .stats_quota_ap_ofst = 0x1D30, .stats_quota_ap_size = 0x48, - .stats_tethering_ofst = 0x2578, + .stats_tethering_ofst = 0x1D78, .stats_tethering_size = 0x238, .stats_flt_v4_ofst = 0, .stats_flt_v4_size = 0, @@ -4011,8 +4011,8 @@ static struct ipa3_mem_partition ipa_4_11_mem_part = { .stats_rt_v4_size = 0, .stats_rt_v6_ofst = 0, .stats_rt_v6_size = 0, - .stats_fnr_ofst = 0x27B0, - .stats_fnr_size = 0x0, + .stats_fnr_ofst = 0x1FB0, + .stats_fnr_size = 0x800, .stats_drop_ofst = 0x27B0, .stats_drop_size = 0x20, .modem_comp_decomp_ofst = 0x0, diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_wdi3_i.c b/drivers/platform/msm/ipa/ipa_v3/ipa_wdi3_i.c index 28636d8e5c7a..54f9f23b3b71 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_wdi3_i.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_wdi3_i.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2018 - 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2018 - 2021, The Linux Foundation. All rights reserved. */ #include "ipa_i.h" @@ -849,8 +849,9 @@ int ipa3_enable_wdi3_pipes(int ipa_ep_idx_tx, int ipa_ep_idx_rx) IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(ipa_ep_idx_tx)); /* start uC event ring */ - if (ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && - ipa3_ctx->ipa_hw_type != IPA_HW_v4_11) { + if ((ipa3_ctx->ipa_hw_type >= IPA_HW_v4_5 && + ipa3_ctx->ipa_hw_type != IPA_HW_v4_11) || + ipa3_ctx->is_bw_monitor_supported) { if (ipa3_ctx->uc_ctx.uc_loaded && !ipa3_ctx->uc_ctx.uc_event_ring_valid) { if (ipa3_uc_setup_event_ring()) { diff --git a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c index 5cc4a5e02ade..84aaf08df871 100644 --- a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved. */ /* @@ -3290,8 +3290,9 @@ static int rmnet_ipa3_set_data_quota_wifi(struct wan_ioctl_set_data_quota *data) IPAWANDBG("iface name %s, quota %lu\n", data->interface_name, (unsigned long) data->quota_mbytes); - if (ipa3_ctx_get_type(IPA_HW_TYPE) >= IPA_HW_v4_5 && - ipa3_ctx_get_type(IPA_HW_TYPE) != IPA_HW_v4_11) { + if ((ipa3_ctx_get_type(IPA_HW_TYPE) >= IPA_HW_v4_5 && + ipa3_ctx_get_type(IPA_HW_TYPE) != IPA_HW_v4_11) || + ipa3_ctx->is_bw_monitor_supported) { IPADBG("use ipa-uc for quota\n"); rc = ipa3_uc_quota_monitor(data->set_quota); } else { From 1d895c493c07d194a68bd4486c22210c5e5f65b3 Mon Sep 17 00:00:00 2001 From: Armaan Siddiqui Date: Thu, 1 Apr 2021 23:43:33 +0530 Subject: [PATCH 02/11] ipa: save registers on graceful shutdown Save registers - when gsi channel setup fails in post init - on graceful shutdown Handle printing registers when ipahal is not intialized. --- drivers/platform/msm/gsi/gsi.c | 10 +++- drivers/platform/msm/ipa/ipa_v3/ipa.c | 15 ++++++ .../platform/msm/ipa/ipa_v3/ipahal/ipahal.c | 18 ++++--- .../msm/ipa/ipa_v3/ipahal/ipahal_reg.c | 48 ++++++++++++++++--- 4 files changed, 77 insertions(+), 14 deletions(-) diff --git a/drivers/platform/msm/gsi/gsi.c b/drivers/platform/msm/gsi/gsi.c index 5725a40c1ea7..93a644eda17b 100644 --- a/drivers/platform/msm/gsi/gsi.c +++ b/drivers/platform/msm/gsi/gsi.c @@ -1820,6 +1820,7 @@ int gsi_alloc_evt_ring(struct gsi_evt_ring_props *props, unsigned long dev_hdl, ((op << GSI_EE_n_EV_CH_CMD_OPCODE_SHFT) & GSI_EE_n_EV_CH_CMD_OPCODE_BMSK)); ee = gsi_ctx->per.ee; + GSIDBG("Sending alloc evt command for %lu\n", evt_id); gsi_writel(val, gsi_ctx->base + GSI_EE_n_EV_CH_CMD_OFFS(ee)); res = wait_for_completion_timeout(&ctx->compl, GSI_CMD_TIMEOUT); @@ -3035,7 +3036,14 @@ EXPORT_SYMBOL(gsi_query_channel_db_addr); int gsi_pending_irq_type(void) { - int ee = gsi_ctx->per.ee; + int ee; + + if (!gsi_ctx->per_registered) { + GSIERR("no client registered\n"); + return 0; + } + + ee = gsi_ctx->per.ee; return gsi_readl(gsi_ctx->base + GSI_EE_n_CNTXT_TYPE_IRQ_OFFS(ee)); diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c index ce8a234e16f5..80e9558cd675 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c @@ -154,6 +154,7 @@ static struct clk *ipa3_clk; struct ipa3_context *ipa3_ctx = NULL; +void ipa3_plat_drv_shutdown(struct platform_device *pdev_p); int ipa3_plat_drv_probe(struct platform_device *pdev_p); int ipa3_pci_drv_probe( struct pci_dev *pci_dev, @@ -443,6 +444,7 @@ static const struct dev_pm_ops ipa_pm_ops = { static struct platform_driver ipa_plat_drv = { .probe = ipa3_plat_drv_probe, + .shutdown = ipa3_plat_drv_shutdown, .driver = { .name = DRV_NAME, .pm = &ipa_pm_ops, @@ -6524,6 +6526,8 @@ fail_teth_bridge_driver_init: ipa3_teardown_apps_pipes(); fail_alloc_gsi_channel: fail_setup_apps_pipes: + ipahal_print_all_regs(false); + ipa_save_registers(); gsi_deregister_device(ipa3_ctx->gsi_dev_hdl, false); fail_register_device: ipa3_destroy_flt_tbl_idrs(); @@ -8998,6 +9002,17 @@ static void ipa_smmu_update_fw_loader(void) } } +void ipa3_plat_drv_shutdown(struct platform_device *pdev_p) +{ + pr_debug("ipa: driver shutdown invoked for %s\n", + pdev_p->dev.of_node->name); + if (ipa3_ctx && atomic_read(&ipa3_ctx->ipa_clk_vote)) { + ipahal_print_all_regs(false); + ipa_save_registers(); + } + return; +} + int ipa3_plat_drv_probe(struct platform_device *pdev_p) { int result; diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c index 4fdd04437455..d7233b9e218b 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.c @@ -617,8 +617,9 @@ static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_ip_v4_filter_init( static struct ipahal_imm_cmd_pyld *ipa_imm_cmd_construct_dummy( enum ipahal_imm_cmd_name cmd, const void *params, bool is_atomic_ctx) { - IPAHAL_ERR("no construct function for IMM_CMD=%s, IPA ver %d\n", - ipahal_imm_cmd_name_str(cmd), ipahal_ctx->hw_type); + IPAHAL_ERR("no construct function for IMM_CMD=%s IPA ver=%d\n", + ipahal_imm_cmd_name_str(cmd), ipahal_ctx?ipahal_ctx->hw_type:-1); + WARN_ON(1); return NULL; } @@ -779,6 +780,11 @@ static u16 ipahal_imm_cmd_get_opcode(enum ipahal_imm_cmd_name cmd) { u32 opcode; + if (!ipahal_ctx) { + IPAHAL_ERR("Invalid ctx\n"); + return -EFAULT; + } + if (cmd >= IPA_IMM_CMD_MAX) { IPAHAL_ERR("Invalid immediate command imm_cmd=%u\n", cmd); ipa_assert(); @@ -813,8 +819,8 @@ struct ipahal_imm_cmd_pyld *ipahal_construct_imm_cmd( return NULL; } - if (cmd >= IPA_IMM_CMD_MAX) { - IPAHAL_ERR("Invalid immediate command %u\n", cmd); + if (!ipahal_ctx || cmd >= IPA_IMM_CMD_MAX) { + IPAHAL_ERR("Invalid ctx/immediate command %u\n", cmd); return NULL; } @@ -1196,7 +1202,7 @@ u32 ipahal_pkt_status_get_size(void) void ipahal_pkt_status_parse(const void *unparsed_status, struct ipahal_pkt_status *status) { - if (!unparsed_status || !status) { + if (!ipahal_ctx || !unparsed_status || !status) { IPAHAL_ERR("Input Error: unparsed_status=%pK status=%pK\n", unparsed_status, status); return; @@ -1218,7 +1224,7 @@ void ipahal_pkt_status_parse(const void *unparsed_status, void ipahal_pkt_status_parse_thin(const void *unparsed_status, struct ipahal_pkt_status_thin *status) { - if (!unparsed_status || !status) { + if (!ipahal_ctx || !unparsed_status || !status) { IPAHAL_ERR("Input Error: unparsed_status=%pK status=%pK\n", unparsed_status, status); return; diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c index 5bead393638c..0e053455de79 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c @@ -3068,8 +3068,11 @@ static struct ipahal_reg_obj ipahal_reg_objs[IPA_HW_MAX][IPA_REG_MAX] = { ipareg_construct_single_ndp_mode, ipareg_parse_single_ndp_mode, -1, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_QSB_MAX_READS] = { - ipareg_construct_qsb_max_reads_v4_0, ipareg_parse_dummy, + ipareg_construct_qsb_max_reads_v4_0, ipareg_parse_qsb_max_reads, 0x00000078, 0, 0, 0, 0}, + [IPA_HW_v4_0][IPA_QSB_MAX_WRITES] = { + ipareg_construct_qsb_max_writes, ipareg_parse_qsb_max_writes, + 0x00000074, 0, 0, 0, 0}, [IPA_HW_v4_0][IPA_FILT_ROUT_HASH_FLUSH] = { ipareg_construct_dummy, ipareg_parse_dummy, 0x0000014c, 0, 0, 0, 0}, @@ -3629,15 +3632,16 @@ void ipahal_print_all_regs(bool print_to_dmesg) int i, j; struct ipahal_reg_obj *reg; - IPAHAL_DBG("Printing all registers for ipa_hw_type %d\n", - ipahal_ctx->hw_type); - - if ((ipahal_ctx->hw_type < IPA_HW_v4_0) || + if (!ipahal_ctx || (ipahal_ctx->hw_type < IPA_HW_v4_0) || (ipahal_ctx->hw_type >= IPA_HW_MAX)) { - IPAHAL_ERR("invalid IPA HW type (%d)\n", ipahal_ctx->hw_type); + IPAHAL_ERR("invalid IPA HW type (%d)\n", + ipahal_ctx?ipahal_ctx->hw_type:-1); return; } + IPAHAL_DBG("Printing all registers for ipa_hw_type %d\n", + ipahal_ctx->hw_type); + for (i = 0; i < IPA_REG_MAX ; i++) { reg = &(ipahal_reg_objs[ipahal_ctx->hw_type][i]); @@ -3753,6 +3757,11 @@ u32 ipahal_read_reg_n(enum ipahal_reg_name reg, u32 n) { u32 offset; + if (!ipahal_ctx) { + IPAHAL_DBG("Invalid ipahal context\n"); + return -EINVAL; + } + if (reg >= IPA_REG_MAX) { IPAHAL_ERR("Invalid register reg=%u\n", reg); WARN_ON(1); @@ -3780,6 +3789,11 @@ u32 ipahal_read_reg_mn(enum ipahal_reg_name reg, u32 m, u32 n) { u32 offset; + if (!ipahal_ctx) { + IPAHAL_DBG("Invalid ipahal context\n"); + return -EINVAL; + } + if (reg >= IPA_REG_MAX) { IPAHAL_ERR("Invalid register reg=%u\n", reg); WARN_ON(1); @@ -3813,6 +3827,11 @@ void ipahal_write_reg_mn(enum ipahal_reg_name reg, u32 m, u32 n, u32 val) { u32 offset; + if (!ipahal_ctx) { + IPAHAL_DBG("Invalid ipahal context\n"); + return; + } + if (reg >= IPA_REG_MAX) { IPAHAL_ERR("Invalid register reg=%u\n", reg); WARN_ON(1); @@ -3847,6 +3866,11 @@ u32 ipahal_read_reg_n_fields(enum ipahal_reg_name reg, u32 n, void *fields) u32 val = 0; u32 offset; + if (!ipahal_ctx) { + IPAHAL_DBG("Invalid ipahal context\n"); + return -EINVAL; + } + if (!fields) { IPAHAL_ERR("Input error fields\n"); WARN_ON(1); @@ -3884,6 +3908,11 @@ void ipahal_write_reg_n_fields(enum ipahal_reg_name reg, u32 n, u32 val = 0; u32 offset; + if (!ipahal_ctx) { + IPAHAL_DBG("Invalid ipahal context\n"); + return; + } + if (!fields) { IPAHAL_ERR("Input error fields=%pK\n", fields); WARN_ON(1); @@ -3918,6 +3947,11 @@ u32 ipahal_get_reg_mn_ofst(enum ipahal_reg_name reg, u32 m, u32 n) { u32 offset; + if (!ipahal_ctx) { + IPAHAL_DBG("Invalid ipahal context\n"); + return -EINVAL; + } + if (reg >= IPA_REG_MAX) { IPAHAL_ERR("Invalid register reg=%u\n", reg); WARN_ON(1); @@ -3967,7 +4001,7 @@ void ipahal_get_aggr_force_close_valmask(int ep_idx, u32 shft = 0; u32 bmsk = 0; - if (!valmask) { + if (!ipahal_ctx || !valmask) { IPAHAL_ERR("Input error\n"); return; } From 7117d2256ac8d10df297382547adf41d6d95d482 Mon Sep 17 00:00:00 2001 From: Sivan Reinstein Date: Mon, 26 Apr 2021 16:03:44 +0300 Subject: [PATCH 03/11] msm: gsi: add gsi profiling stats and fw version to debugfs Add GSI profiling stats data and the GSI FW version to debug fs. Change-Id: I5749339f5ec9656e636a512668025bb09a97a3ec Acked-by: Nadav Levintov Signed-off-by: Sivan Reinstein --- drivers/platform/msm/gsi/gsi.c | 71 ++++++++++++++++++ drivers/platform/msm/gsi/gsi.h | 45 ++++++++++++ drivers/platform/msm/gsi/gsi_dbg.c | 102 +++++++++++++++++++++++++- drivers/platform/msm/gsi/gsi_reg_v2.h | 40 ++++++++++ 4 files changed, 256 insertions(+), 2 deletions(-) diff --git a/drivers/platform/msm/gsi/gsi.c b/drivers/platform/msm/gsi/gsi.c index 5725a40c1ea7..6bdc0f3c640f 100644 --- a/drivers/platform/msm/gsi/gsi.c +++ b/drivers/platform/msm/gsi/gsi.c @@ -38,6 +38,14 @@ #define GSI_STTS_REG_BITS 32 +#define GSI_INST_RAM_FW_VER_OFFSET (0) +#define GSI_INST_RAM_FW_VER_HW_MASK (0xFC00) +#define GSI_INST_RAM_FW_VER_HW_SHIFT (10) +#define GSI_INST_RAM_FW_VER_FLAVOR_MASK (0x380) +#define GSI_INST_RAM_FW_VER_FLAVOR_SHIFT (7) +#define GSI_INST_RAM_FW_VER_FW_MASK (0x7f) +#define GSI_INST_RAM_FW_VER_FW_SHIFT (0) + #ifndef CONFIG_DEBUG_FS void gsi_debugfs_init(void) { @@ -5051,6 +5059,69 @@ static union __packed gsi_channel_scratch __gsi_update_mhi_channel_scratch( return scr; } +/** + * gsi_get_hw_profiling_stats() - Query GSI HW profiling stats + * @stats: [out] stats blob from client populated by driver + * + * Returns: 0 on success, negative on failure + * + */ +int gsi_get_hw_profiling_stats(struct gsi_hw_profiling_data *stats) +{ + if (stats == NULL) { + GSIERR("bad parms NULL stats == NULL\n"); + return -EINVAL; + } + + stats->bp_cnt = (u64)gsi_readl(gsi_ctx->base + + GSI_GSI_MCS_PROFILING_BP_CNT_LSB_OFFS) + + ((u64)gsi_readl(gsi_ctx->base + + GSI_GSI_MCS_PROFILING_BP_CNT_MSB_OFFS) << 32); + stats->bp_and_pending_cnt = (u64)gsi_readl( gsi_ctx->base + + GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_OFFS) + + ((u64)gsi_readl(gsi_ctx->base + + GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_OFFS) + << 32); + stats->mcs_busy_cnt = (u64)gsi_readl(gsi_ctx->base + + GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_OFFS) + + ((u64)gsi_readl(gsi_ctx->base + + GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_OFFS) << 32); + stats->mcs_idle_cnt = (u64)gsi_readl(gsi_ctx->base + + GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_OFFS) + + ((u64)gsi_readl(gsi_ctx->base + + GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_OFFS) << 32); + + return 0; +} + +/** + * gsi_get_fw_version() - Query GSI FW version + * @ver: [out] ver blob from client populated by driver + * + * Returns: 0 on success, negative on failure + * + */ +int gsi_get_fw_version(struct gsi_fw_version *ver) +{ + u32 raw = 0; + + if (ver == NULL) { + GSIERR("bad parms: ver == NULL\n"); + return -EINVAL; + } + + raw = gsi_readl(gsi_ctx->base + + GSI_V2_5_GSI_INST_RAM_n_OFFS(GSI_INST_RAM_FW_VER_OFFSET)); + + ver->hw = (raw & GSI_INST_RAM_FW_VER_HW_MASK) >> + GSI_INST_RAM_FW_VER_HW_SHIFT; + ver->flavor = (raw & GSI_INST_RAM_FW_VER_FLAVOR_MASK) >> + GSI_INST_RAM_FW_VER_FLAVOR_SHIFT; + ver->fw = (raw & GSI_INST_RAM_FW_VER_FW_MASK) >> + GSI_INST_RAM_FW_VER_FW_SHIFT; + + return 0; +} static int msm_gsi_probe(struct platform_device *pdev) { diff --git a/drivers/platform/msm/gsi/gsi.h b/drivers/platform/msm/gsi/gsi.h index bd60e67528ff..261575ff3542 100644 --- a/drivers/platform/msm/gsi/gsi.h +++ b/drivers/platform/msm/gsi/gsi.h @@ -1412,6 +1412,32 @@ enum gsi_generic_ee_cmd_return_code { GSI_GEN_EE_CMD_RETURN_CODE_OUT_OF_RESOURCES = 0x7, }; +/** + * struct gsi_hw_profiling_data - GSI profiling data + * @bp_cnt_lsb: Back Pressure occurences count + * @bp_and_pending_cnt_lsb: Back Pressure with pending back pressure count + * @mcs_busy_cnt_lsb: Cycle count for MCS busy + * @mcs_idle_cnt_lsb: Cycle count for MCS idle + */ +struct gsi_hw_profiling_data { + u64 bp_cnt; + u64 bp_and_pending_cnt; + u64 mcs_busy_cnt; + u64 mcs_idle_cnt; +}; + +/** + * struct gsi_fw_version - GSI fw version data + * @hw: HW version + * @flavor: Flavor identifier + * @fw: FW version + */ +struct gsi_fw_version { + u32 hw; + u32 flavor; + u32 fw; +}; + enum gsi_generic_ee_cmd_query_retun_val { GSI_GEN_EE_CMD_RETURN_VAL_FLOW_CONTROL_PRIMARY = 0, GSI_GEN_EE_CMD_RETURN_VAL_FLOW_CONTROL_SECONDARY = 1, @@ -2127,6 +2153,25 @@ int gsi_alloc_channel_ee(unsigned int chan_idx, unsigned int ee, int *code); */ int gsi_enable_flow_control_ee(unsigned int chan_idx, unsigned int ee, int *code); + +/** + * gsi_get_hw_profiling_stats() - Query GSI HW profiling stats + * @stats: [out] stats blob from client populated by driver + * + * Returns: 0 on success, negative on failure + * + */ +int gsi_get_hw_profiling_stats(struct gsi_hw_profiling_data *stats); + +/** + * gsi_get_fw_version() - Query GSI FW version + * @ver: [out] ver blob from client populated by driver + * + * Returns: 0 on success, negative on failure + * + */ +int gsi_get_fw_version(struct gsi_fw_version *ver); + int gsi_flow_control_ee(unsigned int chan_idx, unsigned int ee, bool enable, bool prmy_scnd_fc, int *code); int gsi_query_flow_control_state_ee(unsigned int chan_idx, unsigned int ee, diff --git a/drivers/platform/msm/gsi/gsi_dbg.c b/drivers/platform/msm/gsi/gsi_dbg.c index e264ea68250d..5ffd2c8e22f5 100644 --- a/drivers/platform/msm/gsi/gsi_dbg.c +++ b/drivers/platform/msm/gsi/gsi_dbg.c @@ -12,6 +12,8 @@ #include "gsi_reg.h" #include "gsi.h" +#define GSI_MAX_MSG_LEN 4096 + #define TERR(fmt, args...) \ pr_err("%s:%d " fmt, __func__, __LINE__, ## args) #define TDBG(fmt, args...) \ @@ -20,7 +22,7 @@ pr_err(fmt, ## args) static struct dentry *dent; -static char dbg_buff[4096]; +static char dbg_buff[GSI_MAX_MSG_LEN]; static void *gsi_ipc_logbuf_low; static void gsi_wq_print_dp_stats(struct work_struct *work); @@ -662,6 +664,79 @@ static ssize_t gsi_enable_ipc_low(struct file *file, return count; } +static ssize_t gsi_read_gsi_hw_profiling_stats(struct file *file, + char __user *buf, size_t count, loff_t *ppos) +{ + struct gsi_hw_profiling_data stats; + int nbytes, cnt = 0; + u64 totalCycles = 0, util = 0; + + if (gsi_ctx->per.ver < GSI_VER_2_9) { + nbytes = scnprintf(dbg_buff, GSI_MAX_MSG_LEN, + "This feature only support on GSI2.9+\n"); + cnt += nbytes; + goto done; + } + if (!gsi_get_hw_profiling_stats(&stats)) { + totalCycles = stats.mcs_busy_cnt + stats.mcs_idle_cnt + + stats.bp_and_pending_cnt; + if (totalCycles != 0) + util = (100 * (stats.mcs_busy_cnt + stats.bp_and_pending_cnt)) / + totalCycles; + else + util = 0; + + nbytes = scnprintf(dbg_buff, GSI_MAX_MSG_LEN, + "bp_count=0x%llx\n" + "bp_and_pending_count=0x%llx\n" + "mcs_busy=0x%llx\n" + "mcs_idle=0x%llx\n" + "total_cycle_count=0x%llx\n" + "utilization_percentage=%llu%%\n", + stats.bp_cnt, + stats.bp_and_pending_cnt, + stats.mcs_busy_cnt, + stats.mcs_idle_cnt, + totalCycles, + util); + cnt += nbytes; + } else { + nbytes = scnprintf(dbg_buff, GSI_MAX_MSG_LEN, + "Fail to read GSI HW Profiling stats\n"); + cnt += nbytes; + } +done: + return simple_read_from_buffer(buf, count, ppos, dbg_buff, cnt); +} + +static ssize_t gsi_read_gsi_fw_version(struct file *file, + char __user *buf, size_t count, loff_t *ppos) +{ + struct gsi_fw_version ver; + int nbytes, cnt = 0; + + if (gsi_ctx->per.ver < GSI_VER_2_9) { + nbytes = scnprintf(dbg_buff, GSI_MAX_MSG_LEN, + "This feature only support on GSI2.9+\n"); + cnt += nbytes; + goto done; + } + if (!gsi_get_fw_version(&ver)) { + nbytes = scnprintf(dbg_buff, GSI_MAX_MSG_LEN, + "hw=%d\nflavor=%d\nfw=%d\n", + ver.hw, + ver.flavor, + ver.fw); + cnt += nbytes; + } else { + nbytes = scnprintf(dbg_buff, GSI_MAX_MSG_LEN, + "Fail to read GSI FW version\n"); + cnt += nbytes; + } +done: + return simple_read_from_buffer(buf, count, ppos, dbg_buff, cnt); +} + static const struct file_operations gsi_ev_dump_ops = { .write = gsi_dump_evt, }; @@ -694,10 +769,19 @@ static const struct file_operations gsi_ipc_low_ops = { .write = gsi_enable_ipc_low, }; +static const struct file_operations gsi_hw_profiling_ops = { + .read = gsi_read_gsi_hw_profiling_stats, +}; + +static const struct file_operations gsi_ver_ops = { + .read = gsi_read_gsi_fw_version, +}; + void gsi_debugfs_init(void) { static struct dentry *dfile; const mode_t write_only_mode = 0220; + const mode_t read_only_mode = 0440; dent = debugfs_create_dir("gsi", 0); if (IS_ERR(dent)) { @@ -761,8 +845,22 @@ void gsi_debugfs_init(void) goto fail; } + dfile = debugfs_create_file("gsi_hw_profiling_stats", read_only_mode, + dent, 0, &gsi_hw_profiling_ops); + if (!dfile || IS_ERR(dfile)) { + TERR("could not create gsi_hw_profiling_stats\n"); + goto fail; + } + + dfile = debugfs_create_file("gsi_fw_version", read_only_mode, dent, 0, + &gsi_ver_ops); + if (!dfile || IS_ERR(dfile)) { + TERR("could not create gsi_fw_version\n"); + goto fail; + } + return; + fail: debugfs_remove_recursive(dent); } - diff --git a/drivers/platform/msm/gsi/gsi_reg_v2.h b/drivers/platform/msm/gsi/gsi_reg_v2.h index 8fdc83f00ff9..defe28fac99c 100644 --- a/drivers/platform/msm/gsi/gsi_reg_v2.h +++ b/drivers/platform/msm/gsi/gsi_reg_v2.h @@ -1212,4 +1212,44 @@ #define GSI_V2_5_GSI_MAP_EE_n_CH_k_VP_TABLE_PHY_CH_BMSK 0x1f #define GSI_V2_5_GSI_MAP_EE_n_CH_k_VP_TABLE_PHY_CH_SHFT 0x0 +#define GSI_GSI_MCS_PROFILING_BP_CNT_LSB_OFFS \ + (GSI_GSI_REG_BASE_OFFS + 0x0000185c) +#define GSI_GSI_MCS_PROFILING_BP_CNT_LSB_RMSK 0xffffffff +#define GSI_GSI_MCS_PROFILING_BP_CNT_LSB_SHFT 0x0 + +#define GSI_GSI_MCS_PROFILING_BP_CNT_MSB_OFFS \ + (GSI_GSI_REG_BASE_OFFS + 0x00001860) +#define GSI_GSI_MCS_PROFILING_BP_CNT_MSB_RMSK 0xffffffff +#define GSI_GSI_MCS_PROFILING_BP_CNT_MSB_SHFT 0x0 + +#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_OFFS \ + (GSI_GSI_REG_BASE_OFFS + 0x00001864) +#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_RMSK 0xffffffff +#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_SHFT 0x0 + +#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_OFFS \ + (GSI_GSI_REG_BASE_OFFS + 0x00001868) +#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_RMSK 0xffffffff +#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_SHFT 0x0 + +#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_OFFS \ + (GSI_GSI_REG_BASE_OFFS + 0x0000186c) +#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_RMSK 0xffffffff +#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_SHFT 0x0 + +#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_OFFS \ + (GSI_GSI_REG_BASE_OFFS + 0x00001870) +#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_RMSK 0xffffffff +#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_SHFT 0x0 + +#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_OFFS \ + (GSI_GSI_REG_BASE_OFFS + 0x00001874) +#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_RMSK 0xffffffff +#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_SHFT 0x0 + +#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_OFFS \ + (GSI_GSI_REG_BASE_OFFS + 0x00001878) +#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_RMSK 0xffffffff +#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_SHFT 0x0 + #endif /* __GSI_REG_V2_H__ */ From 1c9ee39e9018f10071589eb5150ca5c4123e4d2c Mon Sep 17 00:00:00 2001 From: Akshay Pandit Date: Sat, 13 Mar 2021 14:53:48 +0530 Subject: [PATCH 04/11] techpack: dataipa: Enable Regdump for msmnile Enable support to save regump for msmnile target. Change-Id: I47add92e8eb82a546d4217815699fccd52b7b5b8 --- config/dataipa_gsi_V1.h | 5 +- config/dataipa_gsi_V1_GKI.conf | 2 + config/dataipa_gsi_V1_QGKI.conf | 2 + drivers/platform/msm/Makefile | 3 + .../msm/ipa/ipa_v3/dump/ipa4.1/gsi_hwio.h | 2346 +++ .../msm/ipa/ipa_v3/dump/ipa4.1/gsi_hwio_def.h | 539 + .../ipa_v3/dump/ipa4.1/ipa_access_control.h | 50 + .../msm/ipa/ipa_v3/dump/ipa4.1/ipa_gcc_hwio.h | 16806 ++++++++++++++++ .../ipa/ipa_v3/dump/ipa4.1/ipa_gcc_hwio_def.h | 29 + .../ipa/ipa_v3/dump/ipa4.1/ipa_hw_common_ex.h | 610 + .../msm/ipa/ipa_v3/dump/ipa4.1/ipa_hwio.h | 10293 ++++++++++ .../msm/ipa/ipa_v3/dump/ipa4.1/ipa_hwio_def.h | 2775 +++ .../ipa/ipa_v3/dump/ipa4.1/ipa_pkt_cntxt.h | 190 + .../ipa/ipa_v3/dump/ipa4.5/ipa_hw_common_ex.h | 103 +- .../msm/ipa/ipa_v3/dump/ipa_reg_dump.c | 58 +- .../msm/ipa/ipa_v3/dump/ipa_reg_dump.h | 157 +- 16 files changed, 33834 insertions(+), 134 deletions(-) create mode 100644 drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/gsi_hwio.h create mode 100644 drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/gsi_hwio_def.h create mode 100644 drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_access_control.h create mode 100644 drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_gcc_hwio.h create mode 100644 drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_gcc_hwio_def.h create mode 100644 drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_hw_common_ex.h create mode 100644 drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_hwio.h create mode 100644 drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_hwio_def.h create mode 100644 drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_pkt_cntxt.h diff --git a/config/dataipa_gsi_V1.h b/config/dataipa_gsi_V1.h index 883e6b8c6e9c..e28569e35d1e 100644 --- a/config/dataipa_gsi_V1.h +++ b/config/dataipa_gsi_V1.h @@ -1,9 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* -* Copyright (c) 2020, The Linux Foundation. All rights reserved. +* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */ #define CONFIG_GSI 1 #define CONFIG_RMNET_IPA3 1 #define CONFIG_RNDIS_IPA 1 #define CONFIG_IPA_WDI_UNIFIED_API 1 +#define CONFIG_IPA3_REGDUMP 1 +#define CONFIG_IPA3_REGDUMP_IPA_4_1 1 +#define CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS 0 diff --git a/config/dataipa_gsi_V1_GKI.conf b/config/dataipa_gsi_V1_GKI.conf index 075a7198f28b..f911fa362d95 100644 --- a/config/dataipa_gsi_V1_GKI.conf +++ b/config/dataipa_gsi_V1_GKI.conf @@ -3,3 +3,5 @@ export CONFIG_IPA_CLIENTS_MANAGER=m export CONFIG_IPA_WDI_UNIFIED_API=y export CONFIG_RMNET_IPA3=y export CONFIG_RNDIS_IPA=m +export CONFIG_IPA3_REGDUMP=y +export CONFIG_IPA3_REGDUMP_IPA_4_1=y diff --git a/config/dataipa_gsi_V1_QGKI.conf b/config/dataipa_gsi_V1_QGKI.conf index 14c5fa85fb3f..96f8bd893d63 100644 --- a/config/dataipa_gsi_V1_QGKI.conf +++ b/config/dataipa_gsi_V1_QGKI.conf @@ -3,3 +3,5 @@ export CONFIG_IPA_CLIENTS_MANAGER=y export CONFIG_IPA_WDI_UNIFIED_API=y export CONFIG_RMNET_IPA3=y export CONFIG_RNDIS_IPA=y +export CONFIG_IPA3_REGDUMP=y +export CONFIG_IPA3_REGDUMP_IPA_4_1=y diff --git a/drivers/platform/msm/Makefile b/drivers/platform/msm/Makefile index 378e128dfd55..8572a5cf2cb7 100644 --- a/drivers/platform/msm/Makefile +++ b/drivers/platform/msm/Makefile @@ -57,6 +57,9 @@ ifneq (,$(filter $(CONFIG_IPA3_REGDUMP_IPA_4_5),y m)) LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa/ipa_v3/dump/ipa4.5 endif +ifneq (,$(filter $(CONFIG_IPA3_REGDUMP_IPA_4_1),y m)) +LINUXINCLUDE += -I$(DATAIPADRVTOP)/ipa/ipa_v3/dump/ipa4.1 +endif obj-$(CONFIG_GSI) += gsi/ obj-$(CONFIG_IPA3) += ipa/ diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/gsi_hwio.h b/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/gsi_hwio.h new file mode 100644 index 000000000000..6fa6dff6b226 --- /dev/null +++ b/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/gsi_hwio.h @@ -0,0 +1,2346 @@ +/* + * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 and only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ +#if !defined(_GSI_HWIO_H_) +#define _GSI_HWIO_H_ + +/* ***************************************************************************** + * + * HWIO register definitions. + * + * ***************************************************************************** + */ + +#define GSI_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00004000) +#define GSI_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00004000) +#define GSI_REG_BASE_OFFS 0x00004000 +#define HWIO_GSI_CFG_ADDR (GSI_REG_BASE + 0x00000000) +#define HWIO_GSI_CFG_PHYS (GSI_REG_BASE_PHYS + 0x00000000) +#define HWIO_GSI_CFG_OFFS (GSI_REG_BASE_OFFS + 0x00000000) +#define HWIO_GSI_CFG_RMSK 0x3f +#define HWIO_GSI_CFG_ATTR 0x3 +#define HWIO_GSI_CFG_IN in_dword_masked(HWIO_GSI_CFG_ADDR, \ + HWIO_GSI_CFG_RMSK) +#define HWIO_GSI_CFG_INM(m) in_dword_masked(HWIO_GSI_CFG_ADDR, m) +#define HWIO_GSI_CFG_OUT(v) out_dword(HWIO_GSI_CFG_ADDR, v) +#define HWIO_GSI_CFG_OUTM(m, v) out_dword_masked_ns(HWIO_GSI_CFG_ADDR, \ + m, \ + v, \ + HWIO_GSI_CFG_IN) +#define HWIO_GSI_CFG_BP_MTRIX_DISABLE_BMSK 0x20 +#define HWIO_GSI_CFG_BP_MTRIX_DISABLE_SHFT 0x5 +#define HWIO_GSI_CFG_GSI_PWR_CLPS_BMSK 0x10 +#define HWIO_GSI_CFG_GSI_PWR_CLPS_SHFT 0x4 +#define HWIO_GSI_CFG_UC_IS_MCS_BMSK 0x8 +#define HWIO_GSI_CFG_UC_IS_MCS_SHFT 0x3 +#define HWIO_GSI_CFG_DOUBLE_MCS_CLK_FREQ_BMSK 0x4 +#define HWIO_GSI_CFG_DOUBLE_MCS_CLK_FREQ_SHFT 0x2 +#define HWIO_GSI_CFG_MCS_ENABLE_BMSK 0x2 +#define HWIO_GSI_CFG_MCS_ENABLE_SHFT 0x1 +#define HWIO_GSI_CFG_GSI_ENABLE_BMSK 0x1 +#define HWIO_GSI_CFG_GSI_ENABLE_SHFT 0x0 +#define HWIO_GSI_MANAGER_MCS_CODE_VER_ADDR (GSI_REG_BASE + 0x00000008) +#define HWIO_GSI_MANAGER_MCS_CODE_VER_PHYS (GSI_REG_BASE_PHYS + 0x00000008) +#define HWIO_GSI_MANAGER_MCS_CODE_VER_OFFS (GSI_REG_BASE_OFFS + 0x00000008) +#define HWIO_GSI_ZEROS_ADDR (GSI_REG_BASE + 0x00000010) +#define HWIO_GSI_ZEROS_PHYS (GSI_REG_BASE_PHYS + 0x00000010) +#define HWIO_GSI_ZEROS_OFFS (GSI_REG_BASE_OFFS + 0x00000010) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_ADDR (GSI_REG_BASE + 0x00000018) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_PHYS (GSI_REG_BASE_PHYS + 0x00000018) +#define HWIO_GSI_PERIPH_BASE_ADDR_LSB_OFFS (GSI_REG_BASE_OFFS + 0x00000018) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_ADDR (GSI_REG_BASE + 0x0000001c) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_PHYS (GSI_REG_BASE_PHYS + 0x0000001c) +#define HWIO_GSI_PERIPH_BASE_ADDR_MSB_OFFS (GSI_REG_BASE_OFFS + 0x0000001c) +#define HWIO_GSI_PERIPH_PENDING_ADDR (GSI_REG_BASE + 0x00000020) +#define HWIO_GSI_PERIPH_PENDING_PHYS (GSI_REG_BASE_PHYS + 0x00000020) +#define HWIO_GSI_PERIPH_PENDING_OFFS (GSI_REG_BASE_OFFS + 0x00000020) +#define HWIO_GSI_MOQA_CFG_ADDR (GSI_REG_BASE + 0x00000030) +#define HWIO_GSI_MOQA_CFG_PHYS (GSI_REG_BASE_PHYS + 0x00000030) +#define HWIO_GSI_MOQA_CFG_OFFS (GSI_REG_BASE_OFFS + 0x00000030) +#define HWIO_GSI_REE_CFG_ADDR (GSI_REG_BASE + 0x00000038) +#define HWIO_GSI_REE_CFG_PHYS (GSI_REG_BASE_PHYS + 0x00000038) +#define HWIO_GSI_REE_CFG_OFFS (GSI_REG_BASE_OFFS + 0x00000038) +#define HWIO_GSI_REE_CFG_RMSK 0xff01 +#define HWIO_GSI_REE_CFG_ATTR 0x3 +#define HWIO_GSI_REE_CFG_IN in_dword_masked(HWIO_GSI_REE_CFG_ADDR, \ + HWIO_GSI_REE_CFG_RMSK) +#define HWIO_GSI_REE_CFG_INM(m) in_dword_masked(HWIO_GSI_REE_CFG_ADDR, m) +#define HWIO_GSI_REE_CFG_OUT(v) out_dword(HWIO_GSI_REE_CFG_ADDR, v) +#define HWIO_GSI_REE_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_GSI_REE_CFG_ADDR, \ + m, \ + v, \ + HWIO_GSI_REE_CFG_IN) +#define HWIO_GSI_REE_CFG_MAX_BURST_SIZE_BMSK 0xff00 +#define HWIO_GSI_REE_CFG_MAX_BURST_SIZE_SHFT 0x8 +#define HWIO_GSI_REE_CFG_MOVE_TO_ESC_CLR_MODE_TRSH_BMSK 0x1 +#define HWIO_GSI_REE_CFG_MOVE_TO_ESC_CLR_MODE_TRSH_SHFT 0x0 +#define HWIO_GSI_SHRAM_WR_WRR_ADDR (GSI_REG_BASE + 0x00000050) +#define HWIO_GSI_SHRAM_WR_WRR_PHYS (GSI_REG_BASE_PHYS + 0x00000050) +#define HWIO_GSI_SHRAM_WR_WRR_OFFS (GSI_REG_BASE_OFFS + 0x00000050) +#define HWIO_GSI_SHRAM_RD_WRR_ADDR (GSI_REG_BASE + 0x00000058) +#define HWIO_GSI_SHRAM_RD_WRR_PHYS (GSI_REG_BASE_PHYS + 0x00000058) +#define HWIO_GSI_SHRAM_RD_WRR_OFFS (GSI_REG_BASE_OFFS + 0x00000058) +#define HWIO_GSI_CGC_CTRL_ADDR (GSI_REG_BASE + 0x00000060) +#define HWIO_GSI_CGC_CTRL_PHYS (GSI_REG_BASE_PHYS + 0x00000060) +#define HWIO_GSI_CGC_CTRL_OFFS (GSI_REG_BASE_OFFS + 0x00000060) +#define HWIO_GSI_MSI_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000080) +#define HWIO_GSI_MSI_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000080) +#define HWIO_GSI_MSI_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000080) +#define HWIO_GSI_EVENT_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000084) +#define HWIO_GSI_EVENT_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000084) +#define HWIO_GSI_EVENT_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000084) +#define HWIO_GSI_DATA_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000088) +#define HWIO_GSI_DATA_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000088) +#define HWIO_GSI_DATA_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000088) +#define HWIO_GSI_TRE_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000090) +#define HWIO_GSI_TRE_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000090) +#define HWIO_GSI_TRE_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000090) +#define HWIO_IC_DISABLE_CHNL_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000a0) +#define HWIO_IC_DISABLE_CHNL_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000a0) +#define HWIO_IC_DISABLE_CHNL_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000a0) +#define HWIO_IC_DISABLE_CHNL_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000a4) +#define HWIO_IC_DISABLE_CHNL_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000a4) +#define HWIO_IC_DISABLE_CHNL_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000a4) +#define HWIO_IC_GEN_EVNT_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000a8) +#define HWIO_IC_GEN_EVNT_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + 0x000000a8) +#define HWIO_IC_GEN_EVNT_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + 0x000000a8) +#define HWIO_IC_GEN_EVNT_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000ac) +#define HWIO_IC_GEN_EVNT_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + 0x000000ac) +#define HWIO_IC_GEN_EVNT_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + 0x000000ac) +#define HWIO_IC_GEN_INT_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000b0) +#define HWIO_IC_GEN_INT_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + 0x000000b0) +#define HWIO_IC_GEN_INT_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + 0x000000b0) +#define HWIO_IC_GEN_INT_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000b4) +#define HWIO_IC_GEN_INT_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + 0x000000b4) +#define HWIO_IC_GEN_INT_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + 0x000000b4) +#define HWIO_IC_STOP_INT_MOD_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000b8) +#define HWIO_IC_STOP_INT_MOD_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000b8) +#define HWIO_IC_STOP_INT_MOD_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000b8) +#define HWIO_IC_STOP_INT_MOD_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000bc) +#define HWIO_IC_STOP_INT_MOD_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000bc) +#define HWIO_IC_STOP_INT_MOD_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000bc) +#define HWIO_IC_PROCESS_DESC_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000c0) +#define HWIO_IC_PROCESS_DESC_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000c0) +#define HWIO_IC_PROCESS_DESC_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000c0) +#define HWIO_IC_PROCESS_DESC_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000c4) +#define HWIO_IC_PROCESS_DESC_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000c4) +#define HWIO_IC_PROCESS_DESC_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000c4) +#define HWIO_IC_TLV_STOP_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000c8) +#define HWIO_IC_TLV_STOP_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + 0x000000c8) +#define HWIO_IC_TLV_STOP_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + 0x000000c8) +#define HWIO_IC_TLV_STOP_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000cc) +#define HWIO_IC_TLV_STOP_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + 0x000000cc) +#define HWIO_IC_TLV_STOP_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + 0x000000cc) +#define HWIO_IC_TLV_RESET_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000d0) +#define HWIO_IC_TLV_RESET_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + 0x000000d0) +#define HWIO_IC_TLV_RESET_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + 0x000000d0) +#define HWIO_IC_TLV_RESET_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000d4) +#define HWIO_IC_TLV_RESET_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + 0x000000d4) +#define HWIO_IC_TLV_RESET_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + 0x000000d4) +#define HWIO_IC_RGSTR_TIMER_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000d8) +#define HWIO_IC_RGSTR_TIMER_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000d8) +#define HWIO_IC_RGSTR_TIMER_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000d8) +#define HWIO_IC_RGSTR_TIMER_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000dc) +#define HWIO_IC_RGSTR_TIMER_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000dc) +#define HWIO_IC_RGSTR_TIMER_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000dc) +#define HWIO_IC_READ_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000e0) +#define HWIO_IC_READ_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + 0x000000e0) +#define HWIO_IC_READ_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + 0x000000e0) +#define HWIO_IC_READ_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000e4) +#define HWIO_IC_READ_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + 0x000000e4) +#define HWIO_IC_READ_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + 0x000000e4) +#define HWIO_IC_WRITE_BCK_PRS_LSB_ADDR (GSI_REG_BASE + 0x000000e8) +#define HWIO_IC_WRITE_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + 0x000000e8) +#define HWIO_IC_WRITE_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + 0x000000e8) +#define HWIO_IC_WRITE_BCK_PRS_MSB_ADDR (GSI_REG_BASE + 0x000000ec) +#define HWIO_IC_WRITE_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + 0x000000ec) +#define HWIO_IC_WRITE_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + 0x000000ec) +#define HWIO_IC_UCONTROLLER_GPR_BCK_PRS_LSB_ADDR (GSI_REG_BASE + \ + 0x000000f0) +#define HWIO_IC_UCONTROLLER_GPR_BCK_PRS_LSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000f0) +#define HWIO_IC_UCONTROLLER_GPR_BCK_PRS_LSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000f0) +#define HWIO_IC_UCONTROLLER_GPR_BCK_PRS_MSB_ADDR (GSI_REG_BASE + \ + 0x000000f4) +#define HWIO_IC_UCONTROLLER_GPR_BCK_PRS_MSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x000000f4) +#define HWIO_IC_UCONTROLLER_GPR_BCK_PRS_MSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x000000f4) +#define HWIO_IC_INT_WEIGHT_REE_ADDR (GSI_REG_BASE + 0x00000100) +#define HWIO_IC_INT_WEIGHT_REE_PHYS (GSI_REG_BASE_PHYS + 0x00000100) +#define HWIO_IC_INT_WEIGHT_REE_OFFS (GSI_REG_BASE_OFFS + 0x00000100) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_ADDR (GSI_REG_BASE + 0x00000104) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000104) +#define HWIO_IC_INT_WEIGHT_EVT_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000104) +#define HWIO_IC_INT_WEIGHT_INT_ENG_ADDR (GSI_REG_BASE + 0x00000108) +#define HWIO_IC_INT_WEIGHT_INT_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000108) +#define HWIO_IC_INT_WEIGHT_INT_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000108) +#define HWIO_IC_INT_WEIGHT_CSR_ADDR (GSI_REG_BASE + 0x0000010c) +#define HWIO_IC_INT_WEIGHT_CSR_PHYS (GSI_REG_BASE_PHYS + 0x0000010c) +#define HWIO_IC_INT_WEIGHT_CSR_OFFS (GSI_REG_BASE_OFFS + 0x0000010c) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_ADDR (GSI_REG_BASE + 0x00000110) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000110) +#define HWIO_IC_INT_WEIGHT_TLV_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000110) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_ADDR (GSI_REG_BASE + 0x00000114) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000114) +#define HWIO_IC_INT_WEIGHT_TIMER_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000114) +#define HWIO_IC_INT_WEIGHT_DB_ENG_ADDR (GSI_REG_BASE + 0x00000118) +#define HWIO_IC_INT_WEIGHT_DB_ENG_PHYS (GSI_REG_BASE_PHYS + 0x00000118) +#define HWIO_IC_INT_WEIGHT_DB_ENG_OFFS (GSI_REG_BASE_OFFS + 0x00000118) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_ADDR (GSI_REG_BASE + 0x0000011c) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_PHYS (GSI_REG_BASE_PHYS + 0x0000011c) +#define HWIO_IC_INT_WEIGHT_RD_WR_ENG_OFFS (GSI_REG_BASE_OFFS + 0x0000011c) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR (GSI_REG_BASE + 0x00000120) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000120) +#define HWIO_IC_INT_WEIGHT_UCONTROLLER_ENG_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000120) +#define HWIO_IC_INT_WEIGHT_SDMA_ADDR (GSI_REG_BASE + 0x00000124) +#define HWIO_IC_INT_WEIGHT_SDMA_PHYS (GSI_REG_BASE_PHYS + 0x00000124) +#define HWIO_IC_INT_WEIGHT_SDMA_OFFS (GSI_REG_BASE_OFFS + 0x00000124) +#define HWIO_GSI_SDMA_CFG_ADDR (GSI_REG_BASE + 0x0000003c) +#define HWIO_GSI_SDMA_CFG_PHYS (GSI_REG_BASE_PHYS + 0x0000003c) +#define HWIO_GSI_SDMA_CFG_OFFS (GSI_REG_BASE_OFFS + 0x0000003c) +#define HWIO_GSI_SDMA_CACHEATTR_ADDR (GSI_REG_BASE + 0x00000094) +#define HWIO_GSI_SDMA_CACHEATTR_PHYS (GSI_REG_BASE_PHYS + 0x00000094) +#define HWIO_GSI_SDMA_CACHEATTR_OFFS (GSI_REG_BASE_OFFS + 0x00000094) +#define HWIO_GSI_SDMA_SG_IOVEC_LSB_n_ADDR(n) (GSI_REG_BASE + 0x00000140 + \ + 0x8 * (n)) +#define HWIO_GSI_SDMA_SG_IOVEC_LSB_n_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00000140 + 0x8 * (n)) +#define HWIO_GSI_SDMA_SG_IOVEC_LSB_n_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00000140 + 0x8 * (n)) +#define HWIO_GSI_SDMA_SG_IOVEC_MSB_n_ADDR(n) (GSI_REG_BASE + 0x00000144 + \ + 0x8 * (n)) +#define HWIO_GSI_SDMA_SG_IOVEC_MSB_n_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00000144 + 0x8 * (n)) +#define HWIO_GSI_SDMA_SG_IOVEC_MSB_n_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00000144 + 0x8 * (n)) +#define HWIO_GSI_MANAGER_EE_QOS_n_ADDR(n) (GSI_REG_BASE + 0x00000300 + \ + 0x4 * (n)) +#define HWIO_GSI_MANAGER_EE_QOS_n_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00000300 + 0x4 * (n)) +#define HWIO_GSI_MANAGER_EE_QOS_n_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00000300 + 0x4 * (n)) +#define HWIO_GSI_MANAGER_EE_QOS_n_RMSK 0x1f1f03 +#define HWIO_GSI_MANAGER_EE_QOS_n_MAXn 2 +#define HWIO_GSI_MANAGER_EE_QOS_n_ATTR 0x0 +#define HWIO_GSI_MANAGER_EE_QOS_n_INI(n) in_dword_masked( \ + HWIO_GSI_MANAGER_EE_QOS_n_ADDR(n), \ + HWIO_GSI_MANAGER_EE_QOS_n_RMSK) +#define HWIO_GSI_MANAGER_EE_QOS_n_INMI(n, mask) in_dword_masked( \ + HWIO_GSI_MANAGER_EE_QOS_n_ADDR(n), \ + mask) +#define HWIO_GSI_MANAGER_EE_QOS_n_OUTI(n, val) out_dword( \ + HWIO_GSI_MANAGER_EE_QOS_n_ADDR(n), \ + val) +#define HWIO_GSI_MANAGER_EE_QOS_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_GSI_MANAGER_EE_QOS_n_ADDR(n), \ + mask, \ + val, \ + HWIO_GSI_MANAGER_EE_QOS_n_INI(n)) +#define HWIO_GSI_MANAGER_EE_QOS_n_MAX_EV_ALLOC_BMSK 0x1f0000 +#define HWIO_GSI_MANAGER_EE_QOS_n_MAX_EV_ALLOC_SHFT 0x10 +#define HWIO_GSI_MANAGER_EE_QOS_n_MAX_CH_ALLOC_BMSK 0x1f00 +#define HWIO_GSI_MANAGER_EE_QOS_n_MAX_CH_ALLOC_SHFT 0x8 +#define HWIO_GSI_MANAGER_EE_QOS_n_EE_PRIO_BMSK 0x3 +#define HWIO_GSI_MANAGER_EE_QOS_n_EE_PRIO_SHFT 0x0 +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000200) +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000200) +#define HWIO_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000200) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000204) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000204) +#define HWIO_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000204) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000208) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000208) +#define HWIO_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000208) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x0000020c) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x0000020c) +#define HWIO_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x0000020c) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000240) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000240) +#define HWIO_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000240) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000244) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000244) +#define HWIO_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000244) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000248) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000248) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000248) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x0000024c) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS \ + + 0x0000024c) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS \ + + 0x0000024c) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR (GSI_REG_BASE + \ + 0x00000250) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_PHYS (GSI_REG_BASE_PHYS \ + + 0x00000250) +#define HWIO_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_OFFS (GSI_REG_BASE_OFFS \ + + 0x00000250) +#define HWIO_GSI_IRAM_PTR_CH_CMD_ADDR (GSI_REG_BASE + 0x00000400) +#define HWIO_GSI_IRAM_PTR_CH_CMD_PHYS (GSI_REG_BASE_PHYS + 0x00000400) +#define HWIO_GSI_IRAM_PTR_CH_CMD_OFFS (GSI_REG_BASE_OFFS + 0x00000400) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR (GSI_REG_BASE + 0x00000404) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000404) +#define HWIO_GSI_IRAM_PTR_EE_GENERIC_CMD_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000404) +#define HWIO_GSI_IRAM_PTR_CH_DB_ADDR (GSI_REG_BASE + 0x00000418) +#define HWIO_GSI_IRAM_PTR_CH_DB_PHYS (GSI_REG_BASE_PHYS + 0x00000418) +#define HWIO_GSI_IRAM_PTR_CH_DB_OFFS (GSI_REG_BASE_OFFS + 0x00000418) +#define HWIO_GSI_IRAM_PTR_EV_DB_ADDR (GSI_REG_BASE + 0x0000041c) +#define HWIO_GSI_IRAM_PTR_EV_DB_PHYS (GSI_REG_BASE_PHYS + 0x0000041c) +#define HWIO_GSI_IRAM_PTR_EV_DB_OFFS (GSI_REG_BASE_OFFS + 0x0000041c) +#define HWIO_GSI_IRAM_PTR_NEW_RE_ADDR (GSI_REG_BASE + 0x00000420) +#define HWIO_GSI_IRAM_PTR_NEW_RE_PHYS (GSI_REG_BASE_PHYS + 0x00000420) +#define HWIO_GSI_IRAM_PTR_NEW_RE_OFFS (GSI_REG_BASE_OFFS + 0x00000420) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_ADDR (GSI_REG_BASE + 0x00000424) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_PHYS (GSI_REG_BASE_PHYS + 0x00000424) +#define HWIO_GSI_IRAM_PTR_CH_DIS_COMP_OFFS (GSI_REG_BASE_OFFS + 0x00000424) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_ADDR (GSI_REG_BASE + 0x00000428) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_PHYS (GSI_REG_BASE_PHYS + 0x00000428) +#define HWIO_GSI_IRAM_PTR_CH_EMPTY_OFFS (GSI_REG_BASE_OFFS + 0x00000428) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR (GSI_REG_BASE + 0x0000042c) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_PHYS (GSI_REG_BASE_PHYS + \ + 0x0000042c) +#define HWIO_GSI_IRAM_PTR_EVENT_GEN_COMP_OFFS (GSI_REG_BASE_OFFS + \ + 0x0000042c) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR (GSI_REG_BASE + \ + 0x00000430) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000430) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000430) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR (GSI_REG_BASE + \ + 0x00000434) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000434) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000434) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR (GSI_REG_BASE + \ + 0x00000438) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000438) +#define HWIO_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000438) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR (GSI_REG_BASE + 0x0000043c) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_PHYS (GSI_REG_BASE_PHYS + \ + 0x0000043c) +#define HWIO_GSI_IRAM_PTR_TIMER_EXPIRED_OFFS (GSI_REG_BASE_OFFS + \ + 0x0000043c) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR (GSI_REG_BASE + 0x00000440) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000440) +#define HWIO_GSI_IRAM_PTR_WRITE_ENG_COMP_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000440) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_ADDR (GSI_REG_BASE + 0x00000444) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000444) +#define HWIO_GSI_IRAM_PTR_READ_ENG_COMP_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000444) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_ADDR (GSI_REG_BASE + 0x00000448) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_PHYS (GSI_REG_BASE_PHYS + 0x00000448) +#define HWIO_GSI_IRAM_PTR_UC_GP_INT_OFFS (GSI_REG_BASE_OFFS + 0x00000448) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPPED_ADDR (GSI_REG_BASE + 0x0000044c) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPPED_PHYS (GSI_REG_BASE_PHYS + \ + 0x0000044c) +#define HWIO_GSI_IRAM_PTR_INT_MOD_STOPPED_OFFS (GSI_REG_BASE_OFFS + \ + 0x0000044c) +#define HWIO_GSI_IRAM_PTR_SDMA_INT_n_ADDR(n) (GSI_REG_BASE + 0x00000450 + \ + 0x4 * (n)) +#define HWIO_GSI_IRAM_PTR_SDMA_INT_n_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00000450 + 0x4 * (n)) +#define HWIO_GSI_IRAM_PTR_SDMA_INT_n_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00000450 + 0x4 * (n)) +#define HWIO_GSI_INST_RAM_n_ADDR(n) (GSI_REG_BASE + 0x00004000 + 0x4 * (n)) +#define HWIO_GSI_INST_RAM_n_PHYS(n) (GSI_REG_BASE_PHYS + 0x00004000 + \ + 0x4 * (n)) +#define HWIO_GSI_INST_RAM_n_OFFS(n) (GSI_REG_BASE_OFFS + 0x00004000 + \ + 0x4 * (n)) +#define HWIO_GSI_SHRAM_n_ADDR(n) (GSI_REG_BASE + 0x00002000 + 0x4 * (n)) +#define HWIO_GSI_SHRAM_n_PHYS(n) (GSI_REG_BASE_PHYS + 0x00002000 + 0x4 * \ + (n)) +#define HWIO_GSI_SHRAM_n_OFFS(n) (GSI_REG_BASE_OFFS + 0x00002000 + 0x4 * \ + (n)) +#define HWIO_GSI_SHRAM_n_RMSK 0xffffffff +#define HWIO_GSI_SHRAM_n_MAXn 1023 +#define HWIO_GSI_SHRAM_n_ATTR 0x3 +#define HWIO_GSI_SHRAM_n_INI(n) in_dword_masked(HWIO_GSI_SHRAM_n_ADDR( \ + n), \ + HWIO_GSI_SHRAM_n_RMSK) +#define HWIO_GSI_SHRAM_n_INMI(n, mask) in_dword_masked( \ + HWIO_GSI_SHRAM_n_ADDR(n), \ + mask) +#define HWIO_GSI_SHRAM_n_OUTI(n, val) out_dword(HWIO_GSI_SHRAM_n_ADDR( \ + n), val) +#define HWIO_GSI_SHRAM_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_GSI_SHRAM_n_ADDR(n), \ + mask, \ + val, \ + HWIO_GSI_SHRAM_n_INI(n)) +#define HWIO_GSI_SHRAM_n_SHRAM_BMSK 0xffffffff +#define HWIO_GSI_SHRAM_n_SHRAM_SHFT 0x0 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n, k) (GSI_REG_BASE + \ + 0x00003800 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00003800 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00003800 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_RMSK 0x3f +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_MAXn 2 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_MAXk 22 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ATTR 0x3 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_INI2(n, k) in_dword_masked( \ + HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n, k), \ + HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_RMSK) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_INMI2(n, k, mask) in_dword_masked( \ + HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n, k), \ + mask) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_OUTI2(n, k, val) out_dword( \ + HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n, k), \ + val) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_INI2(n, k)) +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_VALID_BMSK 0x20 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_VALID_SHFT 0x5 +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_PHY_CH_BMSK 0x1f +#define HWIO_GSI_MAP_EE_n_CH_k_VP_TABLE_PHY_CH_SHFT 0x0 +#define HWIO_GSI_TEST_BUS_SEL_ADDR (GSI_REG_BASE + 0x00001000) +#define HWIO_GSI_TEST_BUS_SEL_PHYS (GSI_REG_BASE_PHYS + 0x00001000) +#define HWIO_GSI_TEST_BUS_SEL_OFFS (GSI_REG_BASE_OFFS + 0x00001000) +#define HWIO_GSI_TEST_BUS_SEL_RMSK 0xf00ff +#define HWIO_GSI_TEST_BUS_SEL_ATTR 0x3 +#define HWIO_GSI_TEST_BUS_SEL_IN in_dword_masked( \ + HWIO_GSI_TEST_BUS_SEL_ADDR, \ + HWIO_GSI_TEST_BUS_SEL_RMSK) +#define HWIO_GSI_TEST_BUS_SEL_INM(m) in_dword_masked( \ + HWIO_GSI_TEST_BUS_SEL_ADDR, \ + m) +#define HWIO_GSI_TEST_BUS_SEL_OUT(v) out_dword(HWIO_GSI_TEST_BUS_SEL_ADDR, \ + v) +#define HWIO_GSI_TEST_BUS_SEL_OUTM(m, v) out_dword_masked_ns( \ + HWIO_GSI_TEST_BUS_SEL_ADDR, \ + m, \ + v, \ + HWIO_GSI_TEST_BUS_SEL_IN) +#define HWIO_GSI_TEST_BUS_SEL_GSI_HW_EVENTS_SEL_BMSK 0xf0000 +#define HWIO_GSI_TEST_BUS_SEL_GSI_HW_EVENTS_SEL_SHFT 0x10 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_BMSK 0xff +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SHFT 0x0 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_ZEROS_FVAL 0x0 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_0_FVAL 0x1 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_1_FVAL 0x2 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_2_FVAL 0x3 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_3_FVAL 0x4 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_4_FVAL 0x5 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_DB_ENG_FVAL 0x9 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_0_FVAL 0xb +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_1_FVAL 0xc +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_2_FVAL 0xd +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_3_FVAL 0xe +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_4_FVAL 0xf +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_5_FVAL 0x10 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_6_FVAL 0x11 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_7_FVAL 0x12 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_0_FVAL 0x13 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_1_FVAL 0x14 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_2_FVAL 0x15 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_3_FVAL 0x16 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_4_FVAL 0x17 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_5_FVAL 0x18 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_0_FVAL 0x1b +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_1_FVAL 0x1c +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_0_FVAL 0x1f +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_1_FVAL 0x20 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_2_FVAL 0x21 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_3_FVAL 0x22 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_4_FVAL 0x23 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_0_FVAL 0x27 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_1_FVAL 0x28 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_2_FVAL 0x29 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_3_FVAL 0x2a +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_0_FVAL 0x2b +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_1_FVAL 0x2c +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_2_FVAL 0x2d +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_3_FVAL 0x2e +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_0_FVAL 0x33 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_1_FVAL 0x34 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_2_FVAL 0x35 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_3_FVAL 0x36 +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_FVAL 0x3a +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SDMA_0_FVAL 0x3c +#define HWIO_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SMDA_1_FVAL 0x3d +#define HWIO_GSI_TEST_BUS_REG_ADDR (GSI_REG_BASE + 0x00001008) +#define HWIO_GSI_TEST_BUS_REG_PHYS (GSI_REG_BASE_PHYS + 0x00001008) +#define HWIO_GSI_TEST_BUS_REG_OFFS (GSI_REG_BASE_OFFS + 0x00001008) +#define HWIO_GSI_TEST_BUS_REG_RMSK 0xffffffff +#define HWIO_GSI_TEST_BUS_REG_ATTR 0x1 +#define HWIO_GSI_TEST_BUS_REG_IN in_dword_masked( \ + HWIO_GSI_TEST_BUS_REG_ADDR, \ + HWIO_GSI_TEST_BUS_REG_RMSK) +#define HWIO_GSI_TEST_BUS_REG_INM(m) in_dword_masked( \ + HWIO_GSI_TEST_BUS_REG_ADDR, \ + m) +#define HWIO_GSI_TEST_BUS_REG_GSI_TESTBUS_REG_BMSK 0xffffffff +#define HWIO_GSI_TEST_BUS_REG_GSI_TESTBUS_REG_SHFT 0x0 +#define HWIO_GSI_DEBUG_BUSY_REG_ADDR (GSI_REG_BASE + 0x00001010) +#define HWIO_GSI_DEBUG_BUSY_REG_PHYS (GSI_REG_BASE_PHYS + 0x00001010) +#define HWIO_GSI_DEBUG_BUSY_REG_OFFS (GSI_REG_BASE_OFFS + 0x00001010) +#define HWIO_GSI_DEBUG_EVENT_PENDING_ADDR (GSI_REG_BASE + 0x00001014) +#define HWIO_GSI_DEBUG_EVENT_PENDING_PHYS (GSI_REG_BASE_PHYS + 0x00001014) +#define HWIO_GSI_DEBUG_EVENT_PENDING_OFFS (GSI_REG_BASE_OFFS + 0x00001014) +#define HWIO_GSI_DEBUG_TIMER_PENDING_ADDR (GSI_REG_BASE + 0x00001018) +#define HWIO_GSI_DEBUG_TIMER_PENDING_PHYS (GSI_REG_BASE_PHYS + 0x00001018) +#define HWIO_GSI_DEBUG_TIMER_PENDING_OFFS (GSI_REG_BASE_OFFS + 0x00001018) +#define HWIO_GSI_DEBUG_RD_WR_PENDING_ADDR (GSI_REG_BASE + 0x0000101c) +#define HWIO_GSI_DEBUG_RD_WR_PENDING_PHYS (GSI_REG_BASE_PHYS + 0x0000101c) +#define HWIO_GSI_DEBUG_RD_WR_PENDING_OFFS (GSI_REG_BASE_OFFS + 0x0000101c) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_ADDR(n) (GSI_REG_BASE + 0x00001200 + \ + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00001200 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTER_CFGn_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00001200 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTERn_ADDR(n) (GSI_REG_BASE + 0x00001240 + 0x4 * \ + (n)) +#define HWIO_GSI_DEBUG_COUNTERn_PHYS(n) (GSI_REG_BASE_PHYS + 0x00001240 + \ + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTERn_OFFS(n) (GSI_REG_BASE_OFFS + 0x00001240 + \ + 0x4 * (n)) +#define HWIO_GSI_DEBUG_COUNTERn_RMSK 0xffff +#define HWIO_GSI_DEBUG_COUNTERn_MAXn 7 +#define HWIO_GSI_DEBUG_COUNTERn_ATTR 0x1 +#define HWIO_GSI_DEBUG_COUNTERn_INI(n) in_dword_masked( \ + HWIO_GSI_DEBUG_COUNTERn_ADDR(n), \ + HWIO_GSI_DEBUG_COUNTERn_RMSK) +#define HWIO_GSI_DEBUG_COUNTERn_INMI(n, mask) in_dword_masked( \ + HWIO_GSI_DEBUG_COUNTERn_ADDR(n), \ + mask) +#define HWIO_GSI_DEBUG_COUNTERn_COUNTER_VALUE_BMSK 0xffff +#define HWIO_GSI_DEBUG_COUNTERn_COUNTER_VALUE_SHFT 0x0 +#define HWIO_GSI_DEBUG_PC_FROM_SW_ADDR (GSI_REG_BASE + 0x00001040) +#define HWIO_GSI_DEBUG_PC_FROM_SW_PHYS (GSI_REG_BASE_PHYS + 0x00001040) +#define HWIO_GSI_DEBUG_PC_FROM_SW_OFFS (GSI_REG_BASE_OFFS + 0x00001040) +#define HWIO_GSI_DEBUG_SW_STALL_ADDR (GSI_REG_BASE + 0x00001044) +#define HWIO_GSI_DEBUG_SW_STALL_PHYS (GSI_REG_BASE_PHYS + 0x00001044) +#define HWIO_GSI_DEBUG_SW_STALL_OFFS (GSI_REG_BASE_OFFS + 0x00001044) +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_ADDR (GSI_REG_BASE + 0x00001048) +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_PHYS (GSI_REG_BASE_PHYS + 0x00001048) +#define HWIO_GSI_DEBUG_PC_FOR_DEBUG_OFFS (GSI_REG_BASE_OFFS + 0x00001048) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_ADDR (GSI_REG_BASE + 0x00001050) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_PHYS (GSI_REG_BASE_PHYS + 0x00001050) +#define HWIO_GSI_DEBUG_QSB_LOG_SEL_OFFS (GSI_REG_BASE_OFFS + 0x00001050) +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_ADDR (GSI_REG_BASE + 0x00001058) +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_PHYS (GSI_REG_BASE_PHYS + 0x00001058) +#define HWIO_GSI_DEBUG_QSB_LOG_CLR_OFFS (GSI_REG_BASE_OFFS + 0x00001058) +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR (GSI_REG_BASE + 0x00001060) +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_PHYS (GSI_REG_BASE_PHYS + \ + 0x00001060) +#define HWIO_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_OFFS (GSI_REG_BASE_OFFS + \ + 0x00001060) +#define HWIO_GSI_DEBUG_QSB_LOG_0_ADDR (GSI_REG_BASE + 0x00001064) +#define HWIO_GSI_DEBUG_QSB_LOG_0_PHYS (GSI_REG_BASE_PHYS + 0x00001064) +#define HWIO_GSI_DEBUG_QSB_LOG_0_OFFS (GSI_REG_BASE_OFFS + 0x00001064) +#define HWIO_GSI_DEBUG_QSB_LOG_1_ADDR (GSI_REG_BASE + 0x00001068) +#define HWIO_GSI_DEBUG_QSB_LOG_1_PHYS (GSI_REG_BASE_PHYS + 0x00001068) +#define HWIO_GSI_DEBUG_QSB_LOG_1_OFFS (GSI_REG_BASE_OFFS + 0x00001068) +#define HWIO_GSI_DEBUG_QSB_LOG_2_ADDR (GSI_REG_BASE + 0x0000106c) +#define HWIO_GSI_DEBUG_QSB_LOG_2_PHYS (GSI_REG_BASE_PHYS + 0x0000106c) +#define HWIO_GSI_DEBUG_QSB_LOG_2_OFFS (GSI_REG_BASE_OFFS + 0x0000106c) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n) (GSI_REG_BASE + \ + 0x00001070 + 0x4 * \ + (n)) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00001070 + 0x4 * \ + (n)) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00001070 + 0x4 * \ + (n)) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MAXn 3 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ATTR 0x1 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_INI(n) in_dword_masked( \ + HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n), \ + HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_RMSK) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_INMI(n, mask) in_dword_masked( \ + HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n), \ + mask) +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MID_BMSK 0xf8000000 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MID_SHFT 0x1b +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_TID_BMSK 0x7c00000 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_TID_SHFT 0x16 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_WRITE_BMSK 0x200000 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_WRITE_SHFT 0x15 +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR_20_0_BMSK 0x1fffff +#define HWIO_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR_20_0_SHFT 0x0 +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_ADDR(n) (GSI_REG_BASE + 0x00001080 + \ + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00001080 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_WRITE_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00001080 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_ADDR(n) (GSI_REG_BASE + 0x00001100 + \ + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00001100 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00001100 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_RMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_RF_n_READ_MAXn 31 +#define HWIO_GSI_DEBUG_SW_RF_n_READ_ATTR 0x1 +#define HWIO_GSI_DEBUG_SW_RF_n_READ_INI(n) in_dword_masked( \ + HWIO_GSI_DEBUG_SW_RF_n_READ_ADDR(n), \ + HWIO_GSI_DEBUG_SW_RF_n_READ_RMSK) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_INMI(n, mask) in_dword_masked( \ + HWIO_GSI_DEBUG_SW_RF_n_READ_ADDR(n), \ + mask) +#define HWIO_GSI_DEBUG_SW_RF_n_READ_RF_REG_BMSK 0xffffffff +#define HWIO_GSI_DEBUG_SW_RF_n_READ_RF_REG_SHFT 0x0 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n, k) (GSI_REG_BASE + \ + 0x00001400 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00001400 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00001400 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_RMSK 0x3f +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_MAXn 3 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_MAXk 16 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ATTR 0x1 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_INI2(n, k) in_dword_masked( \ + HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n, k), \ + HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_RMSK) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n, \ + k), \ + mask) +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_VALID_BMSK 0x20 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_VALID_SHFT 0x5 +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHY_CH_BMSK 0x1f +#define HWIO_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHY_CH_SHFT 0x0 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n, k) (GSI_REG_BASE + \ + 0x00001600 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x00001600 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x00001600 + 0x80 * \ + (n) + 0x4 * (k)) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_RMSK 0x3f +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_MAXn 3 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_MAXk 11 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ATTR 0x1 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_INI2(n, k) in_dword_masked( \ + HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n, k), \ + HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_RMSK) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n, \ + k), \ + mask) +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_VALID_BMSK 0x20 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_VALID_SHFT 0x5 +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHY_EV_CH_BMSK 0x1f +#define HWIO_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHY_EV_CH_SHFT 0x0 +#define HWIO_GSI_DEBUG_SDMA_TRANS_DB_n_ADDR(n) (GSI_REG_BASE + \ + 0x00001800 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SDMA_TRANS_DB_n_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00001800 + 0x4 * (n)) +#define HWIO_GSI_DEBUG_SDMA_TRANS_DB_n_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00001800 + 0x4 * (n)) +#define HWIO_GSI_UC_SRC_IRQ_ADDR (GSI_REG_BASE + 0x00000500) +#define HWIO_GSI_UC_SRC_IRQ_PHYS (GSI_REG_BASE_PHYS + 0x00000500) +#define HWIO_GSI_UC_SRC_IRQ_OFFS (GSI_REG_BASE_OFFS + 0x00000500) +#define HWIO_GSI_UC_SRC_IRQ_MSK_ADDR (GSI_REG_BASE + 0x00000504) +#define HWIO_GSI_UC_SRC_IRQ_MSK_PHYS (GSI_REG_BASE_PHYS + 0x00000504) +#define HWIO_GSI_UC_SRC_IRQ_MSK_OFFS (GSI_REG_BASE_OFFS + 0x00000504) +#define HWIO_GSI_UC_SRC_IRQ_CLR_ADDR (GSI_REG_BASE + 0x00000508) +#define HWIO_GSI_UC_SRC_IRQ_CLR_PHYS (GSI_REG_BASE_PHYS + 0x00000508) +#define HWIO_GSI_UC_SRC_IRQ_CLR_OFFS (GSI_REG_BASE_OFFS + 0x00000508) +#define HWIO_GSI_ACC_ARGS_n_ADDR(n) (GSI_REG_BASE + 0x0000050c + 0x4 * (n)) +#define HWIO_GSI_ACC_ARGS_n_PHYS(n) (GSI_REG_BASE_PHYS + 0x0000050c + \ + 0x4 * (n)) +#define HWIO_GSI_ACC_ARGS_n_OFFS(n) (GSI_REG_BASE_OFFS + 0x0000050c + \ + 0x4 * (n)) +#define HWIO_GSI_ACC_ROUTINE_ADDR (GSI_REG_BASE + 0x00000524) +#define HWIO_GSI_ACC_ROUTINE_PHYS (GSI_REG_BASE_PHYS + 0x00000524) +#define HWIO_GSI_ACC_ROUTINE_OFFS (GSI_REG_BASE_OFFS + 0x00000524) +#define HWIO_GSI_ACC_GO_ADDR (GSI_REG_BASE + 0x00000528) +#define HWIO_GSI_ACC_GO_PHYS (GSI_REG_BASE_PHYS + 0x00000528) +#define HWIO_GSI_ACC_GO_OFFS (GSI_REG_BASE_OFFS + 0x00000528) +#define HWIO_GSI_ACC_2_UC_MCS_STTS_ADDR (GSI_REG_BASE + 0x0000052c) +#define HWIO_GSI_ACC_2_UC_MCS_STTS_PHYS (GSI_REG_BASE_PHYS + 0x0000052c) +#define HWIO_GSI_ACC_2_UC_MCS_STTS_OFFS (GSI_REG_BASE_OFFS + 0x0000052c) +#define HWIO_GSI_ACC_2_UC_MCS_RET_VAL_LSB_ADDR (GSI_REG_BASE + 0x00000530) +#define HWIO_GSI_ACC_2_UC_MCS_RET_VAL_LSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000530) +#define HWIO_GSI_ACC_2_UC_MCS_RET_VAL_LSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000530) +#define HWIO_GSI_ACC_2_UC_MCS_RET_VAL_MSB_ADDR (GSI_REG_BASE + 0x00000534) +#define HWIO_GSI_ACC_2_UC_MCS_RET_VAL_MSB_PHYS (GSI_REG_BASE_PHYS + \ + 0x00000534) +#define HWIO_GSI_ACC_2_UC_MCS_RET_VAL_MSB_OFFS (GSI_REG_BASE_OFFS + \ + 0x00000534) +#define HWIO_GSI_IC_2_UC_MCS_VLD_ADDR (GSI_REG_BASE + 0x00000538) +#define HWIO_GSI_IC_2_UC_MCS_VLD_PHYS (GSI_REG_BASE_PHYS + 0x00000538) +#define HWIO_GSI_IC_2_UC_MCS_VLD_OFFS (GSI_REG_BASE_OFFS + 0x00000538) +#define HWIO_GSI_IC_2_UC_MCS_PC_ADDR (GSI_REG_BASE + 0x0000053c) +#define HWIO_GSI_IC_2_UC_MCS_PC_PHYS (GSI_REG_BASE_PHYS + 0x0000053c) +#define HWIO_GSI_IC_2_UC_MCS_PC_OFFS (GSI_REG_BASE_OFFS + 0x0000053c) +#define HWIO_GSI_IC_2_UC_MCS_ARGS_n_ADDR(n) (GSI_REG_BASE + 0x00000540 + \ + 0x4 * (n)) +#define HWIO_GSI_IC_2_UC_MCS_ARGS_n_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00000540 + 0x4 * (n)) +#define HWIO_GSI_IC_2_UC_MCS_ARGS_n_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00000540 + 0x4 * (n)) +#define HWIO_GSI_UC_TLV_IN_VLD_ADDR (GSI_REG_BASE + 0x00000558) +#define HWIO_GSI_UC_TLV_IN_VLD_PHYS (GSI_REG_BASE_PHYS + 0x00000558) +#define HWIO_GSI_UC_TLV_IN_VLD_OFFS (GSI_REG_BASE_OFFS + 0x00000558) +#define HWIO_GSI_UC_TLV_IN_ROUTINE_ADDR (GSI_REG_BASE + 0x0000055c) +#define HWIO_GSI_UC_TLV_IN_ROUTINE_PHYS (GSI_REG_BASE_PHYS + 0x0000055c) +#define HWIO_GSI_UC_TLV_IN_ROUTINE_OFFS (GSI_REG_BASE_OFFS + 0x0000055c) +#define HWIO_GSI_UC_TLV_IN_ARGS_n_ADDR(n) (GSI_REG_BASE + 0x00000560 + \ + 0x4 * (n)) +#define HWIO_GSI_UC_TLV_IN_ARGS_n_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x00000560 + 0x4 * (n)) +#define HWIO_GSI_UC_TLV_IN_ARGS_n_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x00000560 + 0x4 * (n)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, k) (GSI_REG_BASE + 0x0001c000 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c000 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c000 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_RMSK 0xfff7dfff +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_0_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_CNTXT_0_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK 0xff000000 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_NOT_ALLOCATED_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_ALLOCATED_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STARTED_FVAL 0x2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STOPPED_FVAL 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STOP_IN_PROC_FVAL 0x4 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_ERROR_FVAL 0xf +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ERINDEX_BMSK 0x7c000 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_ERINDEX_SHFT 0xe +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHID_BMSK 0x1f00 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHID_SHFT 0x8 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_EE_BMSK 0xf0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_EE_SHFT 0x4 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_BMSK 0x8 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_SHFT 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_INBOUND_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_OUTBOUND_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_BMSK 0x7 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MHI_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_XHCI_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_GPI_FVAL 0x2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_XDCI_FVAL 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, k) (GSI_REG_BASE + 0x0001c004 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c004 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c004 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_RMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_1_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_CNTXT_1_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, k) (GSI_REG_BASE + 0x0001c008 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c008 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c008 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_2_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_CNTXT_2_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, k) (GSI_REG_BASE + 0x0001c00c + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c00c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c00c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_3_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_CNTXT_3_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, k) (GSI_REG_BASE + 0x0001c010 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c010 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c010 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_4_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_CNTXT_4_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_READ_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_4_READ_PTR_LSB_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_ADDR(n, k) (GSI_REG_BASE + 0x0001c014 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c014 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c014 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_ATTR 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_5_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_5_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_5_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_READ_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_5_READ_PTR_MSB_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_ADDR(n, k) (GSI_REG_BASE + 0x0001c018 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c018 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c018 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_ATTR 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_6_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_6_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_6_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_6_WRITE_PTR_LSB_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_ADDR(n, k) (GSI_REG_BASE + 0x0001c01c + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c01c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c01c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_ATTR 0x1 +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_7_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_CNTXT_7_RMSK) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_CNTXT_7_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_CNTXT_7_WRITE_PTR_MSB_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001c054 + \ + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_PHYS(n, \ + k) (GSI_REG_BASE_PHYS + \ + 0x0001c054 + \ + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OFFS(n, \ + k) (GSI_REG_BASE_OFFS + \ + 0x0001c054 + \ + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_RMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_RMSK) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, \ + k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR( \ + n, \ + k), mask, val, \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_READ_PTR_BMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_READ_PTR_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001c058 + \ + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_PHYS(n, \ + k) (GSI_REG_BASE_PHYS + \ + 0x0001c058 + \ + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OFFS(n, \ + k) (GSI_REG_BASE_OFFS + \ + 0x0001c058 + \ + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RMSK) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, \ + k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR( \ + n, \ + k), mask, val, \ + HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INI2(n, \ + k)) +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RE_INTR_DB_BMSK 0xffff +#define HWIO_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RE_INTR_DB_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_QOS_ADDR(n, k) (GSI_REG_BASE + 0x0001c05c + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_QOS_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c05c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_QOS_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c05c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_QOS_RMSK 0x70f +#define HWIO_EE_n_GSI_CH_k_QOS_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_QOS_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_QOS_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_QOS_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_QOS_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_QOS_RMSK) +#define HWIO_EE_n_GSI_CH_k_QOS_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_QOS_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_QOS_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_QOS_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_QOS_OUTMI2(n, k, mask, val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_QOS_ADDR(n, k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_QOS_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_QOS_USE_ESCAPE_BUF_ONLY_BMSK 0x400 +#define HWIO_EE_n_GSI_CH_k_QOS_USE_ESCAPE_BUF_ONLY_SHFT 0xa +#define HWIO_EE_n_GSI_CH_k_QOS_USE_DB_ENG_BMSK 0x200 +#define HWIO_EE_n_GSI_CH_k_QOS_USE_DB_ENG_SHFT 0x9 +#define HWIO_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_BMSK 0x100 +#define HWIO_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_SHFT 0x8 +#define HWIO_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_ONE_PREFETCH_SEG_FVAL 0x0 +#define HWIO_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_TWO_PREFETCH_SEG_FVAL 0x1 +#define HWIO_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_BMSK 0xf +#define HWIO_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001c060 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c060 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c060 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_SCRATCH_0_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_SCRATCH_0_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_0_SCRATCH_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001c064 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c064 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c064 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_SCRATCH_1_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_SCRATCH_1_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_1_SCRATCH_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001c068 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c068 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c068 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_SCRATCH_2_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_SCRATCH_2_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_2_SCRATCH_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001c06c + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001c06c + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001c06c + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_RMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_MAXn 2 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_MAXk 16 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_ATTR 0x3 +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, k), \ + HWIO_EE_n_GSI_CH_k_SCRATCH_3_RMSK) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, k), \ + mask) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, k), \ + val) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_GSI_CH_k_SCRATCH_3_INI2(n, k)) +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_GSI_CH_k_SCRATCH_3_SCRATCH_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001c070 + \ + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_PHYS(n, \ + k) (GSI_REG_BASE_PHYS + \ + 0x0001c070 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_OFFS(n, \ + k) (GSI_REG_BASE_OFFS + \ + 0x0001c070 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n, k) (GSI_REG_BASE + 0x0001d000 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d000 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d000 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_RMSK 0xfff1ffff +#define HWIO_EE_n_EV_CH_k_CNTXT_0_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_0_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_0_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_0_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK 0xff000000 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHSTATE_NOT_ALLOCATED_FVAL 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHSTATE_ALLOCATED_FVAL 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INTYPE_BMSK 0x10000 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INTYPE_SHFT 0x10 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INTYPE_MSI_FVAL 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_INTYPE_IRQ_FVAL 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_EVCHID_BMSK 0xff00 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_EVCHID_SHFT 0x8 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_EE_BMSK 0xf0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_EE_SHFT 0x4 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_BMSK 0xf +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_MHI_EV_FVAL 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_XHCI_EV_FVAL 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_GPI_EV_FVAL 0x2 +#define HWIO_EE_n_EV_CH_k_CNTXT_0_CHTYPE_XDCI_FVAL 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n, k) (GSI_REG_BASE + 0x0001d004 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d004 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d004 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_RMSK 0xffff +#define HWIO_EE_n_EV_CH_k_CNTXT_1_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_1_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_1_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_1_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_1_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_1_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_1_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffff +#define HWIO_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n, k) (GSI_REG_BASE + 0x0001d008 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d008 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d008 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_2_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_2_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_2_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_2_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_2_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_2_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_2_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n, k) (GSI_REG_BASE + 0x0001d00c + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d00c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d00c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_3_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_3_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_3_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_3_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_3_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_3_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_3_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n, k) (GSI_REG_BASE + 0x0001d010 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d010 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d010 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_4_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_4_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_4_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_4_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_4_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_4_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_4_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_4_READ_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_4_READ_PTR_LSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_5_ADDR(n, k) (GSI_REG_BASE + 0x0001d014 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d014 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d014 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_5_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_5_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_5_ATTR 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_5_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_5_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_5_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_5_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_5_READ_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_5_READ_PTR_MSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_6_ADDR(n, k) (GSI_REG_BASE + 0x0001d018 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d018 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d018 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_6_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_6_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_6_ATTR 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_6_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_6_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_6_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_6_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_6_WRITE_PTR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_6_WRITE_PTR_LSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_7_ADDR(n, k) (GSI_REG_BASE + 0x0001d01c + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d01c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d01c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_7_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_7_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_7_ATTR 0x1 +#define HWIO_EE_n_EV_CH_k_CNTXT_7_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_7_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_7_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_7_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_7_WRITE_PTR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_7_WRITE_PTR_MSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n, k) (GSI_REG_BASE + 0x0001d020 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d020 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d020 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_8_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_8_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_8_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_8_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_BMSK 0xff000000 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_SHFT 0x18 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MODC_BMSK 0xff0000 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MODC_SHFT 0x10 +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MODT_BMSK 0xffff +#define HWIO_EE_n_EV_CH_k_CNTXT_8_INT_MODT_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n, k) (GSI_REG_BASE + 0x0001d024 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d024 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d024 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_9_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_9_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_9_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_9_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_9_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_9_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_9_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_9_INTVEC_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_9_INTVEC_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n, k) (GSI_REG_BASE + 0x0001d028 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d028 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d028 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_10_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_10_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_10_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_10_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_10_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_10_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_10_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n, k) (GSI_REG_BASE + 0x0001d02c + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d02c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d02c + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_11_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_11_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_11_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_11_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_11_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_11_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_11_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n, k) (GSI_REG_BASE + 0x0001d030 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d030 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d030 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_12_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_12_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_12_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_12_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_12_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_12_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_12_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n, k) (GSI_REG_BASE + 0x0001d034 + \ + 0x4000 * (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d034 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d034 + 0x4000 * (n) + \ + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_13_MAXn 2 +#define HWIO_EE_n_EV_CH_k_CNTXT_13_MAXk 11 +#define HWIO_EE_n_EV_CH_k_CNTXT_13_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_CNTXT_13_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_CNTXT_13_RMSK) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_CNTXT_13_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_CNTXT_13_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001d048 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d048 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d048 + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_MAXn 2 +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_MAXk 11 +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_SCRATCH_0_RMSK) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_SCRATCH_0_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_0_SCRATCH_SHFT 0x0 +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001d04c + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001d04c + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001d04c + 0x4000 * \ + (n) + 0x80 * (k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_RMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_MAXn 2 +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_MAXk 11 +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_ATTR 0x3 +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_INI2(n, k) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, k), \ + HWIO_EE_n_EV_CH_k_SCRATCH_1_RMSK) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_INMI2(n, k, mask) in_dword_masked( \ + HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, k), \ + mask) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_OUTI2(n, k, val) out_dword( \ + HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, k), \ + val) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_EE_n_EV_CH_k_SCRATCH_1_INI2(n, k)) +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_EV_CH_k_SCRATCH_1_SCRATCH_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001e000 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001e000 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_0_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001e000 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001e004 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001e004 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_CH_k_DOORBELL_1_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001e004 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001e100 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001e100 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_0_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001e100 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_ADDR(n, k) (GSI_REG_BASE + \ + 0x0001e104 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_PHYS(n, k) (GSI_REG_BASE_PHYS + \ + 0x0001e104 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_EV_CH_k_DOORBELL_1_OFFS(n, k) (GSI_REG_BASE_OFFS + \ + 0x0001e104 + 0x4000 * \ + (n) + 0x8 * (k)) +#define HWIO_EE_n_GSI_STATUS_ADDR(n) (GSI_REG_BASE + 0x0001f000 + 0x4000 * \ + (n)) +#define HWIO_EE_n_GSI_STATUS_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f000 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_STATUS_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f000 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_STATUS_RMSK 0x1 +#define HWIO_EE_n_GSI_STATUS_MAXn 2 +#define HWIO_EE_n_GSI_STATUS_ATTR 0x1 +#define HWIO_EE_n_GSI_STATUS_INI(n) in_dword_masked( \ + HWIO_EE_n_GSI_STATUS_ADDR(n), \ + HWIO_EE_n_GSI_STATUS_RMSK) +#define HWIO_EE_n_GSI_STATUS_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_GSI_STATUS_ADDR(n), \ + mask) +#define HWIO_EE_n_GSI_STATUS_ENABLED_BMSK 0x1 +#define HWIO_EE_n_GSI_STATUS_ENABLED_SHFT 0x0 +#define HWIO_EE_n_GSI_CH_CMD_ADDR(n) (GSI_REG_BASE + 0x0001f008 + 0x4000 * \ + (n)) +#define HWIO_EE_n_GSI_CH_CMD_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f008 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_CH_CMD_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f008 + \ + 0x4000 * (n)) +#define HWIO_EE_n_EV_CH_CMD_ADDR(n) (GSI_REG_BASE + 0x0001f010 + 0x4000 * \ + (n)) +#define HWIO_EE_n_EV_CH_CMD_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f010 + \ + 0x4000 * (n)) +#define HWIO_EE_n_EV_CH_CMD_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f010 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_ADDR(n) (GSI_REG_BASE + 0x0001f018 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f018 + 0x4000 * (n)) +#define HWIO_EE_n_GSI_EE_GENERIC_CMD_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f018 + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_0_ADDR(n) (GSI_REG_BASE + 0x0001f038 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_0_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f038 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_0_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f038 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_1_ADDR(n) (GSI_REG_BASE + 0x0001f03c + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_1_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f03c + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_1_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f03c + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_2_ADDR(n) (GSI_REG_BASE + 0x0001f040 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_2_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f040 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_2_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f040 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_SW_VERSION_ADDR(n) (GSI_REG_BASE + 0x0001f044 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_SW_VERSION_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f044 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_SW_VERSION_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f044 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_MCS_CODE_VER_ADDR(n) (GSI_REG_BASE + 0x0001f048 + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_MCS_CODE_VER_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f048 + 0x4000 * (n)) +#define HWIO_EE_n_GSI_MCS_CODE_VER_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f048 + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_3_ADDR(n) (GSI_REG_BASE + 0x0001f04c + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_3_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f04c + \ + 0x4000 * (n)) +#define HWIO_EE_n_GSI_HW_PARAM_3_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f04c + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_ADDR(n) (GSI_REG_BASE + 0x0001f080 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f080 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f080 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_RMSK 0x7f +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MAXn 2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_ATTR 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_TYPE_IRQ_ADDR(n), \ + HWIO_EE_n_CNTXT_TYPE_IRQ_RMSK) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_TYPE_IRQ_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_GENERAL_BMSK 0x40 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_GENERAL_SHFT 0x6 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_BMSK 0x20 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_SHFT 0x5 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_BMSK 0x10 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_SHFT 0x4 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_IEOB_BMSK 0x8 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_IEOB_SHFT 0x3 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_BMSK 0x4 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_SHFT 0x2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_BMSK 0x2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_SHFT 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_BMSK 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_SHFT 0x0 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n) (GSI_REG_BASE + 0x0001f088 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f088 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f088 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_RMSK 0x7f +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_MAXn 2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ATTR 0x3 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), \ + HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_RMSK) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INI(n)) +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_GENERAL_BMSK 0x40 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_GENERAL_SHFT 0x6 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_EV_CTRL_BMSK 0x20 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_EV_CTRL_SHFT 0x5 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_CH_CTRL_BMSK 0x10 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_CH_CTRL_SHFT 0x4 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_IEOB_BMSK 0x8 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_IEOB_SHFT 0x3 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_GLOB_EE_BMSK 0x4 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_GLOB_EE_SHFT 0x2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL_BMSK 0x2 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL_SHFT 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL_BMSK 0x1 +#define HWIO_EE_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_ADDR(n) (GSI_REG_BASE + \ + 0x0001f090 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f090 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f090 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_ATTR 0x1 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_ADDR(n), \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_RMSK) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_GSI_CH_BIT_MAP_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_ADDR(n) (GSI_REG_BASE + 0x0001f094 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f094 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f094 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_ATTR 0x1 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_ADDR(n), \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_RMSK) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_EV_CH_BIT_MAP_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR(n) (GSI_REG_BASE + \ + 0x0001f098 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f098 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f098 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_RMSK 0x1ffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR(n), \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_RMSK) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_INI(n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_GSI_CH_BIT_MAP_MSK_BMSK 0x1ffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_GSI_CH_BIT_MAP_MSK_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR(n) (GSI_REG_BASE + \ + 0x0001f09c + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f09c + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f09c + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_RMSK 0xfff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR(n), \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_RMSK) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_INI(n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_EV_CH_BIT_MAP_MSK_BMSK 0xfff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_EV_CH_BIT_MAP_MSK_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_ADDR(n) (GSI_REG_BASE + \ + 0x0001f0a0 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f0a0 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f0a0 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_ATTR 0x2 +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_GSI_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_GSI_CH_BIT_MAP_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_ADDR(n) (GSI_REG_BASE + \ + 0x0001f0a4 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f0a4 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f0a4 + 0x4000 * \ + (n)) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_ATTR 0x2 +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_EV_CH_BIT_MAP_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_ADDR(n) (GSI_REG_BASE + 0x0001f0b0 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f0b0 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f0b0 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_ATTR 0x1 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_ADDR(n), \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_RMSK) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_EV_CH_BIT_MAP_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR(n) (GSI_REG_BASE + \ + 0x0001f0b8 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f0b8 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f0b8 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_RMSK 0xfff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR(n), \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_RMSK) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_INI(n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_EV_CH_BIT_MAP_MSK_BMSK 0xfff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_EV_CH_BIT_MAP_MSK_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_ADDR(n) (GSI_REG_BASE + \ + 0x0001f0c0 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f0c0 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f0c0 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_MAXn 2 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_ATTR 0x2 +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_EV_CH_BIT_MAP_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_EV_CH_BIT_MAP_SHFT 0x0 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n) (GSI_REG_BASE + 0x0001f100 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f100 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f100 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_RMSK 0xf +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_MAXn 2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ATTR 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n), \ + HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_RMSK) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_BMSK 0x8 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_SHFT 0x3 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_BMSK 0x4 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_SHFT 0x2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_BMSK 0x2 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_SHFT 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_BMSK 0x1 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_SHFT 0x0 +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n) (GSI_REG_BASE + 0x0001f108 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f108 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_EN_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f108 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_ADDR(n) (GSI_REG_BASE + 0x0001f110 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f110 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GLOB_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f110 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n) (GSI_REG_BASE + 0x0001f118 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f118 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f118 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_RMSK 0xf +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_MAXn 2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_ATTR 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n), \ + HWIO_EE_n_CNTXT_GSI_IRQ_STTS_RMSK) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_BMSK 0x8 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_SHFT 0x3 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_BMSK 0x4 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_SHFT 0x2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_BMSK 0x2 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_SHFT 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_BMSK 0x1 +#define HWIO_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_SHFT 0x0 +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n) (GSI_REG_BASE + 0x0001f120 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f120 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_EN_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f120 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_ADDR(n) (GSI_REG_BASE + 0x0001f128 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f128 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_GSI_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f128 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_INTSET_ADDR(n) (GSI_REG_BASE + 0x0001f180 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_INTSET_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f180 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_INTSET_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f180 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n) (GSI_REG_BASE + 0x0001f188 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f188 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_LSB_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f188 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n) (GSI_REG_BASE + 0x0001f18c + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f18c + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_MSI_BASE_MSB_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f18c + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_INT_VEC_ADDR(n) (GSI_REG_BASE + 0x0001f190 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_INT_VEC_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f190 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_INT_VEC_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f190 + \ + 0x4000 * (n)) +#define HWIO_EE_n_ERROR_LOG_ADDR(n) (GSI_REG_BASE + 0x0001f200 + 0x4000 * \ + (n)) +#define HWIO_EE_n_ERROR_LOG_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f200 + \ + 0x4000 * (n)) +#define HWIO_EE_n_ERROR_LOG_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f200 + \ + 0x4000 * (n)) +#define HWIO_EE_n_ERROR_LOG_RMSK 0xffffffff +#define HWIO_EE_n_ERROR_LOG_MAXn 2 +#define HWIO_EE_n_ERROR_LOG_ATTR 0x3 +#define HWIO_EE_n_ERROR_LOG_INI(n) in_dword_masked( \ + HWIO_EE_n_ERROR_LOG_ADDR(n), \ + HWIO_EE_n_ERROR_LOG_RMSK) +#define HWIO_EE_n_ERROR_LOG_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_ERROR_LOG_ADDR(n), \ + mask) +#define HWIO_EE_n_ERROR_LOG_OUTI(n, val) out_dword( \ + HWIO_EE_n_ERROR_LOG_ADDR(n), \ + val) +#define HWIO_EE_n_ERROR_LOG_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_EE_n_ERROR_LOG_ADDR(n), \ + mask, \ + val, \ + HWIO_EE_n_ERROR_LOG_INI(n)) +#define HWIO_EE_n_ERROR_LOG_ERROR_LOG_BMSK 0xffffffff +#define HWIO_EE_n_ERROR_LOG_ERROR_LOG_SHFT 0x0 +#define HWIO_EE_n_ERROR_LOG_CLR_ADDR(n) (GSI_REG_BASE + 0x0001f210 + \ + 0x4000 * (n)) +#define HWIO_EE_n_ERROR_LOG_CLR_PHYS(n) (GSI_REG_BASE_PHYS + 0x0001f210 + \ + 0x4000 * (n)) +#define HWIO_EE_n_ERROR_LOG_CLR_OFFS(n) (GSI_REG_BASE_OFFS + 0x0001f210 + \ + 0x4000 * (n)) +#define HWIO_EE_n_ERROR_LOG_CLR_RMSK 0xffffffff +#define HWIO_EE_n_ERROR_LOG_CLR_MAXn 2 +#define HWIO_EE_n_ERROR_LOG_CLR_ATTR 0x2 +#define HWIO_EE_n_ERROR_LOG_CLR_OUTI(n, val) out_dword( \ + HWIO_EE_n_ERROR_LOG_CLR_ADDR(n), \ + val) +#define HWIO_EE_n_ERROR_LOG_CLR_ERROR_LOG_CLR_BMSK 0xffffffff +#define HWIO_EE_n_ERROR_LOG_CLR_ERROR_LOG_CLR_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n) (GSI_REG_BASE + 0x0001f400 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_0_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f400 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_0_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f400 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_0_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SCRATCH_0_MAXn 2 +#define HWIO_EE_n_CNTXT_SCRATCH_0_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SCRATCH_0_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n), \ + HWIO_EE_n_CNTXT_SCRATCH_0_RMSK) +#define HWIO_EE_n_CNTXT_SCRATCH_0_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SCRATCH_0_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SCRATCH_0_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_EE_n_CNTXT_SCRATCH_0_ADDR(n), \ + mask, \ + val, \ + HWIO_EE_n_CNTXT_SCRATCH_0_INI(n)) +#define HWIO_EE_n_CNTXT_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SCRATCH_0_SCRATCH_SHFT 0x0 +#define HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n) (GSI_REG_BASE + 0x0001f404 + \ + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_1_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0001f404 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_1_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0001f404 + 0x4000 * (n)) +#define HWIO_EE_n_CNTXT_SCRATCH_1_RMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SCRATCH_1_MAXn 2 +#define HWIO_EE_n_CNTXT_SCRATCH_1_ATTR 0x3 +#define HWIO_EE_n_CNTXT_SCRATCH_1_INI(n) in_dword_masked( \ + HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n), \ + HWIO_EE_n_CNTXT_SCRATCH_1_RMSK) +#define HWIO_EE_n_CNTXT_SCRATCH_1_INMI(n, mask) in_dword_masked( \ + HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n), \ + mask) +#define HWIO_EE_n_CNTXT_SCRATCH_1_OUTI(n, val) out_dword( \ + HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n), \ + val) +#define HWIO_EE_n_CNTXT_SCRATCH_1_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_EE_n_CNTXT_SCRATCH_1_ADDR(n), \ + mask, \ + val, \ + HWIO_EE_n_CNTXT_SCRATCH_1_INI(n)) +#define HWIO_EE_n_CNTXT_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_EE_n_CNTXT_SCRATCH_1_SCRATCH_SHFT 0x0 +#define HWIO_GSI_MCS_CFG_ADDR (GSI_REG_BASE + 0x0000b000) +#define HWIO_GSI_MCS_CFG_PHYS (GSI_REG_BASE_PHYS + 0x0000b000) +#define HWIO_GSI_MCS_CFG_OFFS (GSI_REG_BASE_OFFS + 0x0000b000) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_ADDR (GSI_REG_BASE + 0x0000b008) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_PHYS (GSI_REG_BASE_PHYS + 0x0000b008) +#define HWIO_GSI_TZ_FW_AUTH_LOCK_OFFS (GSI_REG_BASE_OFFS + 0x0000b008) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_ADDR (GSI_REG_BASE + 0x0000b010) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_PHYS (GSI_REG_BASE_PHYS + 0x0000b010) +#define HWIO_GSI_MSA_FW_AUTH_LOCK_OFFS (GSI_REG_BASE_OFFS + 0x0000b010) +#define HWIO_GSI_SP_FW_AUTH_LOCK_ADDR (GSI_REG_BASE + 0x0000b018) +#define HWIO_GSI_SP_FW_AUTH_LOCK_PHYS (GSI_REG_BASE_PHYS + 0x0000b018) +#define HWIO_GSI_SP_FW_AUTH_LOCK_OFFS (GSI_REG_BASE_OFFS + 0x0000b018) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_ADDR(n) (GSI_REG_BASE + 0x0000c000 + \ + 0x1000 * (n)) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c000 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_ORIGINATOR_EE_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c000 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_GSI_CH_CMD_ADDR(n) (GSI_REG_BASE + 0x0000c008 + \ + 0x1000 * (n)) +#define HWIO_INTER_EE_n_GSI_CH_CMD_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c008 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_GSI_CH_CMD_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c008 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_EV_CH_CMD_ADDR(n) (GSI_REG_BASE + 0x0000c010 + \ + 0x1000 * (n)) +#define HWIO_INTER_EE_n_EV_CH_CMD_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c010 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_EV_CH_CMD_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c010 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_ADDR(n) (GSI_REG_BASE + \ + 0x0000c018 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c018 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c018 + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_ADDR(n) (GSI_REG_BASE + 0x0000c01c + \ + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c01c + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c01c + 0x1000 * (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_ADDR(n) (GSI_REG_BASE + \ + 0x0000c020 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c020 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c020 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_ADDR(n) (GSI_REG_BASE + \ + 0x0000c024 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c024 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_MSK_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c024 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_ADDR(n) (GSI_REG_BASE + \ + 0x0000c028 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c028 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c028 + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_ADDR(n) (GSI_REG_BASE + \ + 0x0000c02c + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_PHYS(n) (GSI_REG_BASE_PHYS + \ + 0x0000c02c + 0x1000 * \ + (n)) +#define HWIO_INTER_EE_n_SRC_EV_CH_IRQ_CLR_OFFS(n) (GSI_REG_BASE_OFFS + \ + 0x0000c02c + 0x1000 * \ + (n)) +#endif diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/gsi_hwio_def.h b/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/gsi_hwio_def.h new file mode 100644 index 000000000000..29bf3d015da3 --- /dev/null +++ b/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/gsi_hwio_def.h @@ -0,0 +1,539 @@ +/* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#if !defined(_GSI_HWIO_DEF_H_) +#define _GSI_HWIO_DEF_H_ + +/* ***************************************************************************** + * + * HWIO register definitions + * + * ***************************************************************************** + */ +struct gsi_hwio_def_gsi_cfg_s { + u32 gsi_enable : 1; + u32 mcs_enable : 1; + u32 double_mcs_clk_freq : 1; + u32 uc_is_mcs : 1; + u32 gsi_pwr_clps : 1; + u32 bp_mtrix_disable : 1; + u32 reserved0 : 26; +}; +union gsi_hwio_def_gsi_cfg_u { + struct gsi_hwio_def_gsi_cfg_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_ree_cfg_s { + u32 move_to_esc_clr_mode_trsh : 1; + u32 reserved0 : 7; + u32 max_burst_size : 8; + u32 reserved1 : 16; +}; +union gsi_hwio_def_gsi_ree_cfg_u { + struct gsi_hwio_def_gsi_ree_cfg_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_manager_ee_qos_n_s { + u32 ee_prio : 2; + u32 reserved0 : 6; + u32 max_ch_alloc : 5; + u32 reserved1 : 3; + u32 max_ev_alloc : 5; + u32 reserved2 : 11; +}; +union gsi_hwio_def_gsi_manager_ee_qos_n_u { + struct gsi_hwio_def_gsi_manager_ee_qos_n_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_shram_n_s { + u32 shram : 32; +}; +union gsi_hwio_def_gsi_shram_n_u { + struct gsi_hwio_def_gsi_shram_n_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_test_bus_sel_s { + u32 gsi_testbus_sel : 8; + u32 reserved0 : 8; + u32 gsi_hw_events_sel : 4; + u32 reserved1 : 12; +}; +union gsi_hwio_def_gsi_test_bus_sel_u { + struct gsi_hwio_def_gsi_test_bus_sel_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_test_bus_reg_s { + u32 gsi_testbus_reg : 32; +}; +union gsi_hwio_def_gsi_test_bus_reg_u { + struct gsi_hwio_def_gsi_test_bus_reg_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_debug_countern_s { + u32 counter_value : 16; + u32 reserved0 : 16; +}; +union gsi_hwio_def_gsi_debug_countern_u { + struct gsi_hwio_def_gsi_debug_countern_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_s { + u32 addr_20_0 : 21; + u32 write : 1; + u32 tid : 5; + u32 mid : 5; +}; +union gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_u { + struct gsi_hwio_def_gsi_debug_qsb_log_last_misc_idn_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_debug_sw_rf_n_read_s { + u32 rf_reg : 32; +}; +union gsi_hwio_def_gsi_debug_sw_rf_n_read_u { + struct gsi_hwio_def_gsi_debug_sw_rf_n_read_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_s { + u32 phy_ch : 5; + u32 valid : 1; + u32 reserved0 : 26; +}; +union gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_u { + struct gsi_hwio_def_gsi_map_ee_n_ch_k_vp_table_s def; + u32 value; +}; +struct gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_s { + u32 phy_ev_ch : 5; + u32 valid : 1; + u32 reserved0 : 26; +}; +union gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_u { + struct gsi_hwio_def_gsi_debug_ee_n_ev_k_vp_table_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_s { + u32 chtype_protocol : 3; + u32 chtype_dir : 1; + u32 ee : 4; + u32 chid : 5; + u32 reserved0 : 1; + u32 erindex : 5; + u32 reserved1 : 1; + u32 chstate : 4; + u32 element_size : 8; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_0_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_s { + u32 r_length : 16; + u32 reserved0 : 16; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_1_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_s { + u32 r_base_addr_lsbs : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_2_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_s { + u32 r_base_addr_msbs : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_3_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_s { + u32 read_ptr_lsb : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_4_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_s { + u32 read_ptr_msb : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_5_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_s { + u32 write_ptr_lsb : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_6_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_s { + u32 write_ptr_msb : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_cntxt_7_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_s { + u32 read_ptr : 16; + u32 reserved0 : 16; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_read_ptr_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_s { + u32 re_intr_db : 16; + u32 reserved0 : 16; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_re_fetch_write_ptr_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_qos_s { + u32 wrr_weight : 4; + u32 reserved0 : 4; + u32 max_prefetch : 1; + u32 use_db_eng : 1; + u32 use_escape_buf_only : 1; + u32 reserved1 : 21; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_qos_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_qos_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_0_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_1_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_2_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_u { + struct gsi_hwio_def_ee_n_gsi_ch_k_scratch_3_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_s { + u32 chtype : 4; + u32 ee : 4; + u32 evchid : 8; + u32 intype : 1; + u32 reserved0 : 3; + u32 chstate : 4; + u32 element_size : 8; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_0_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_s { + u32 r_length : 16; + u32 reserved0 : 16; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_1_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_s { + u32 r_base_addr_lsbs : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_2_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_s { + u32 r_base_addr_msbs : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_3_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_s { + u32 read_ptr_lsb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_4_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_s { + u32 read_ptr_msb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_5_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_s { + u32 write_ptr_lsb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_6_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_s { + u32 write_ptr_msb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_7_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_s { + u32 int_modt : 16; + u32 int_modc : 8; + u32 int_mod_cnt : 8; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_8_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_s { + u32 intvec : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_9_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_s { + u32 msi_addr_lsb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_10_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_s { + u32 msi_addr_msb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_11_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_s { + u32 rp_update_addr_lsb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_12_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_s { + u32 rp_update_addr_msb : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_u { + struct gsi_hwio_def_ee_n_ev_ch_k_cntxt_13_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_scratch_0_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_scratch_0_u { + struct gsi_hwio_def_ee_n_ev_ch_k_scratch_0_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_ev_ch_k_scratch_1_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_ev_ch_k_scratch_1_u { + struct gsi_hwio_def_ee_n_ev_ch_k_scratch_1_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_gsi_status_s { + u32 enabled : 1; + u32 reserved0 : 31; +}; +union gsi_hwio_def_ee_n_gsi_status_u { + struct gsi_hwio_def_ee_n_gsi_status_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_type_irq_s { + u32 ch_ctrl : 1; + u32 ev_ctrl : 1; + u32 glob_ee : 1; + u32 ieob : 1; + u32 inter_ee_ch_ctrl : 1; + u32 inter_ee_ev_ctrl : 1; + u32 general : 1; + u32 reserved0 : 25; +}; +union gsi_hwio_def_ee_n_cntxt_type_irq_u { + struct gsi_hwio_def_ee_n_cntxt_type_irq_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_type_irq_msk_s { + u32 ch_ctrl : 1; + u32 ev_ctrl : 1; + u32 glob_ee : 1; + u32 ieob : 1; + u32 inter_ee_ch_ctrl : 1; + u32 inter_ee_ev_ctrl : 1; + u32 general : 1; + u32 reserved0 : 25; +}; +union gsi_hwio_def_ee_n_cntxt_type_irq_msk_u { + struct gsi_hwio_def_ee_n_cntxt_type_irq_msk_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_s { + u32 gsi_ch_bit_map : 32; +}; +union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_u { + struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_s { + u32 ev_ch_bit_map : 32; +}; +union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_u { + struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_s { + u32 gsi_ch_bit_map_msk : 17; + u32 reserved0 : 15; +}; +union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_u { + struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_msk_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_s { + u32 ev_ch_bit_map_msk : 12; + u32 reserved0 : 20; +}; +union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_u { + struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_msk_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_s { + u32 gsi_ch_bit_map : 32; +}; +union gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_u { + struct gsi_hwio_def_ee_n_cntxt_src_gsi_ch_irq_clr_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_s { + u32 ev_ch_bit_map : 32; +}; +union gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_u { + struct gsi_hwio_def_ee_n_cntxt_src_ev_ch_irq_clr_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_s { + u32 ev_ch_bit_map : 32; +}; +union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_u { + struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_s { + u32 ev_ch_bit_map_msk : 12; + u32 reserved0 : 20; +}; +union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_u { + struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_msk_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_s { + u32 ev_ch_bit_map : 32; +}; +union gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_u { + struct gsi_hwio_def_ee_n_cntxt_src_ieob_irq_clr_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_glob_irq_stts_s { + u32 error_int : 1; + u32 gp_int1 : 1; + u32 gp_int2 : 1; + u32 gp_int3 : 1; + u32 reserved0 : 28; +}; +union gsi_hwio_def_ee_n_cntxt_glob_irq_stts_u { + struct gsi_hwio_def_ee_n_cntxt_glob_irq_stts_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_s { + u32 gsi_break_point : 1; + u32 gsi_bus_error : 1; + u32 gsi_cmd_fifo_ovrflow : 1; + u32 gsi_mcs_stack_ovrflow : 1; + u32 reserved0 : 28; +}; +union gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_u { + struct gsi_hwio_def_ee_n_cntxt_gsi_irq_stts_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_intset_s { + u32 intype : 1; + u32 reserved0 : 31; +}; +union gsi_hwio_def_ee_n_cntxt_intset_u { + struct gsi_hwio_def_ee_n_cntxt_intset_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_msi_base_lsb_s { + u32 msi_addr_lsb : 32; +}; +union gsi_hwio_def_ee_n_cntxt_msi_base_lsb_u { + struct gsi_hwio_def_ee_n_cntxt_msi_base_lsb_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_msi_base_msb_s { + u32 msi_addr_msb : 32; +}; +union gsi_hwio_def_ee_n_cntxt_msi_base_msb_u { + struct gsi_hwio_def_ee_n_cntxt_msi_base_msb_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_error_log_s { + u32 error_log : 32; +}; +union gsi_hwio_def_ee_n_error_log_u { + struct gsi_hwio_def_ee_n_error_log_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_error_log_clr_s { + u32 error_log_clr : 32; +}; +union gsi_hwio_def_ee_n_error_log_clr_u { + struct gsi_hwio_def_ee_n_error_log_clr_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_scratch_0_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_cntxt_scratch_0_u { + struct gsi_hwio_def_ee_n_cntxt_scratch_0_s def; + u32 value; +}; +struct gsi_hwio_def_ee_n_cntxt_scratch_1_s { + u32 scratch : 32; +}; +union gsi_hwio_def_ee_n_cntxt_scratch_1_u { + struct gsi_hwio_def_ee_n_cntxt_scratch_1_s def; + u32 value; +}; +#endif diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_access_control.h b/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_access_control.h new file mode 100644 index 000000000000..8e72c63001bd --- /dev/null +++ b/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_access_control.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 and only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ +#if !defined(_IPA_ACCESS_CONTROL_H_) +#define _IPA_ACCESS_CONTROL_H_ + +#include "ipa_reg_dump.h" + +/* + * The following is target specific. + */ +static struct reg_mem_access_map_t mem_access_map[] = { + /*------------------------------------------------------------*/ + /* Range Use when Use when */ + /* Begin End SD_ENABLED SD_DISABLED */ + /*------------------------------------------------------------*/ + { 0x04000, 0x05000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x07000, 0x0f000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x05000, 0x07000, { &io_matrix[AA_COMBO], &io_matrix[AN_COMBO] } }, + { 0x0f000, 0x10000, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x20000, 0x24000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x24000, 0x28000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x28000, 0x2c000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x10000, 0x11000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x11000, 0x12000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x12000, 0x13000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x43000, 0x44000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x44000, 0x45000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x45000, 0x47000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x40000, 0x42000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x42000, 0x43000, { &io_matrix[AA_COMBO], &io_matrix[AN_COMBO] } }, + { 0x47000, 0x4a000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x4a000, 0x5a000, { &io_matrix[AN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x5a000, 0x5c000, { &io_matrix[NN_COMBO], &io_matrix[NN_COMBO] } }, + { 0x5e000, 0x60000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x60000, 0x70000, { &io_matrix[AN_COMBO], &io_matrix[AN_COMBO] } }, + { 0x70000, 0x72000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, + { 0x72000, 0x80000, { &io_matrix[AA_COMBO], &io_matrix[AA_COMBO] } }, +}; + +#endif /* #if !defined(_IPA_ACCESS_CONTROL_H_) */ diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_gcc_hwio.h b/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_gcc_hwio.h new file mode 100644 index 000000000000..ff93acd15c1d --- /dev/null +++ b/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_gcc_hwio.h @@ -0,0 +1,16806 @@ +/* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#if !defined(_IPA_GCC_HWIO_H_) +#define _IPA_GCC_HWIO_H_ + +/* ***************************************************************************** + * + * HWIO register definitions + * + * ***************************************************************************** + */ +#define GCC_CLK_CTL_REG_REG_BASE (CLK_CTL_BASE + 0x00000000) +#define GCC_CLK_CTL_REG_REG_BASE_PHYS (CLK_CTL_BASE_PHYS + 0x00000000) +#define GCC_CLK_CTL_REG_REG_BASE_OFFS 0x00000000 +#define HWIO_GCC_GPLL0_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000000) +#define HWIO_GCC_GPLL0_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000000) +#define HWIO_GCC_GPLL0_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000000) +#define HWIO_GCC_GPLL0_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000004) +#define HWIO_GCC_GPLL0_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000004) +#define HWIO_GCC_GPLL0_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000004) +#define HWIO_GCC_GPLL0_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000008) +#define HWIO_GCC_GPLL0_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000008) +#define HWIO_GCC_GPLL0_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000008) +#define HWIO_GCC_GPLL0_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000000c) +#define HWIO_GCC_GPLL0_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000000c) +#define HWIO_GCC_GPLL0_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000000c) +#define HWIO_GCC_GPLL0_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000010) +#define HWIO_GCC_GPLL0_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000010) +#define HWIO_GCC_GPLL0_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000010) +#define HWIO_GCC_GPLL0_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000014) +#define HWIO_GCC_GPLL0_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000014) +#define HWIO_GCC_GPLL0_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000014) +#define HWIO_GCC_GPLL0_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000018) +#define HWIO_GCC_GPLL0_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000018) +#define HWIO_GCC_GPLL0_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000018) +#define HWIO_GCC_GPLL0_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000001c) +#define HWIO_GCC_GPLL0_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000001c) +#define HWIO_GCC_GPLL0_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000001c) +#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000020) +#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000020) +#define HWIO_GCC_GPLL0_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000020) +#define HWIO_GCC_GPLL0_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000024) +#define HWIO_GCC_GPLL0_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000024) +#define HWIO_GCC_GPLL0_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000024) +#define HWIO_GCC_GPLL0_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000028) +#define HWIO_GCC_GPLL0_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000028) +#define HWIO_GCC_GPLL0_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000028) +#define HWIO_GCC_GPLL0_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000002c) +#define HWIO_GCC_GPLL0_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000002c) +#define HWIO_GCC_GPLL0_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000002c) +#define HWIO_GCC_GPLL0_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000030) +#define HWIO_GCC_GPLL0_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000030) +#define HWIO_GCC_GPLL0_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000030) +#define HWIO_GCC_GPLL0_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000034) +#define HWIO_GCC_GPLL0_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000034) +#define HWIO_GCC_GPLL0_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000034) +#define HWIO_GCC_GPLL0_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000038) +#define HWIO_GCC_GPLL0_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000038) +#define HWIO_GCC_GPLL0_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000038) +#define HWIO_GCC_GPLL0_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000003c) +#define HWIO_GCC_GPLL0_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000003c) +#define HWIO_GCC_GPLL0_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000003c) +#define HWIO_GCC_GPLL0_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000040) +#define HWIO_GCC_GPLL0_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000040) +#define HWIO_GCC_GPLL0_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000040) +#define HWIO_GCC_GPLL0_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000044) +#define HWIO_GCC_GPLL0_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000044) +#define HWIO_GCC_GPLL0_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000044) +#define HWIO_GCC_GPLL0_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000048) +#define HWIO_GCC_GPLL0_SSC_DELTA_ALPHA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00000048) +#define HWIO_GCC_GPLL0_SSC_DELTA_ALPHA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00000048) +#define HWIO_GCC_GPLL0_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000004c) +#define HWIO_GCC_GPLL0_SSC_UPDATE_RATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000004c) +#define HWIO_GCC_GPLL0_SSC_UPDATE_RATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000004c) +#define HWIO_GCC_GPLL0_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000050) +#define HWIO_GCC_GPLL0_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000050) +#define HWIO_GCC_GPLL0_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000050) +#define HWIO_GCC_GPLL1_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001000) +#define HWIO_GCC_GPLL1_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001000) +#define HWIO_GCC_GPLL1_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001000) +#define HWIO_GCC_GPLL1_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001004) +#define HWIO_GCC_GPLL1_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001004) +#define HWIO_GCC_GPLL1_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001004) +#define HWIO_GCC_GPLL1_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001008) +#define HWIO_GCC_GPLL1_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001008) +#define HWIO_GCC_GPLL1_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001008) +#define HWIO_GCC_GPLL1_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000100c) +#define HWIO_GCC_GPLL1_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000100c) +#define HWIO_GCC_GPLL1_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000100c) +#define HWIO_GCC_GPLL1_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001010) +#define HWIO_GCC_GPLL1_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001010) +#define HWIO_GCC_GPLL1_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001010) +#define HWIO_GCC_GPLL1_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001014) +#define HWIO_GCC_GPLL1_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001014) +#define HWIO_GCC_GPLL1_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001014) +#define HWIO_GCC_GPLL1_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001018) +#define HWIO_GCC_GPLL1_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001018) +#define HWIO_GCC_GPLL1_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001018) +#define HWIO_GCC_GPLL1_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000101c) +#define HWIO_GCC_GPLL1_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000101c) +#define HWIO_GCC_GPLL1_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000101c) +#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001020) +#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001020) +#define HWIO_GCC_GPLL1_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001020) +#define HWIO_GCC_GPLL1_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001024) +#define HWIO_GCC_GPLL1_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001024) +#define HWIO_GCC_GPLL1_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001024) +#define HWIO_GCC_GPLL1_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001028) +#define HWIO_GCC_GPLL1_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001028) +#define HWIO_GCC_GPLL1_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001028) +#define HWIO_GCC_GPLL1_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000102c) +#define HWIO_GCC_GPLL1_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000102c) +#define HWIO_GCC_GPLL1_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000102c) +#define HWIO_GCC_GPLL1_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001030) +#define HWIO_GCC_GPLL1_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001030) +#define HWIO_GCC_GPLL1_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001030) +#define HWIO_GCC_GPLL1_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001034) +#define HWIO_GCC_GPLL1_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001034) +#define HWIO_GCC_GPLL1_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001034) +#define HWIO_GCC_GPLL1_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001038) +#define HWIO_GCC_GPLL1_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001038) +#define HWIO_GCC_GPLL1_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001038) +#define HWIO_GCC_GPLL1_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000103c) +#define HWIO_GCC_GPLL1_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000103c) +#define HWIO_GCC_GPLL1_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000103c) +#define HWIO_GCC_GPLL1_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001040) +#define HWIO_GCC_GPLL1_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001040) +#define HWIO_GCC_GPLL1_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001040) +#define HWIO_GCC_GPLL1_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001044) +#define HWIO_GCC_GPLL1_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001044) +#define HWIO_GCC_GPLL1_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001044) +#define HWIO_GCC_GPLL1_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001048) +#define HWIO_GCC_GPLL1_SSC_DELTA_ALPHA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00001048) +#define HWIO_GCC_GPLL1_SSC_DELTA_ALPHA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00001048) +#define HWIO_GCC_GPLL1_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000104c) +#define HWIO_GCC_GPLL1_SSC_UPDATE_RATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000104c) +#define HWIO_GCC_GPLL1_SSC_UPDATE_RATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000104c) +#define HWIO_GCC_GPLL1_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00001050) +#define HWIO_GCC_GPLL1_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001050) +#define HWIO_GCC_GPLL1_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001050) +#define HWIO_GCC_GPLL2_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00002000) +#define HWIO_GCC_GPLL2_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002000) +#define HWIO_GCC_GPLL2_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002000) +#define HWIO_GCC_GPLL2_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00002004) +#define HWIO_GCC_GPLL2_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002004) +#define HWIO_GCC_GPLL2_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002004) +#define HWIO_GCC_GPLL2_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002008) +#define HWIO_GCC_GPLL2_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002008) +#define HWIO_GCC_GPLL2_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002008) +#define HWIO_GCC_GPLL2_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000200c) +#define HWIO_GCC_GPLL2_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000200c) +#define HWIO_GCC_GPLL2_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000200c) +#define HWIO_GCC_GPLL2_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002010) +#define HWIO_GCC_GPLL2_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002010) +#define HWIO_GCC_GPLL2_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002010) +#define HWIO_GCC_GPLL2_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002014) +#define HWIO_GCC_GPLL2_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002014) +#define HWIO_GCC_GPLL2_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002014) +#define HWIO_GCC_GPLL2_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002018) +#define HWIO_GCC_GPLL2_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002018) +#define HWIO_GCC_GPLL2_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002018) +#define HWIO_GCC_GPLL2_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000201c) +#define HWIO_GCC_GPLL2_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000201c) +#define HWIO_GCC_GPLL2_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000201c) +#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002020) +#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002020) +#define HWIO_GCC_GPLL2_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002020) +#define HWIO_GCC_GPLL2_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002024) +#define HWIO_GCC_GPLL2_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002024) +#define HWIO_GCC_GPLL2_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002024) +#define HWIO_GCC_GPLL2_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002028) +#define HWIO_GCC_GPLL2_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002028) +#define HWIO_GCC_GPLL2_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002028) +#define HWIO_GCC_GPLL2_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000202c) +#define HWIO_GCC_GPLL2_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000202c) +#define HWIO_GCC_GPLL2_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000202c) +#define HWIO_GCC_GPLL2_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00002030) +#define HWIO_GCC_GPLL2_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002030) +#define HWIO_GCC_GPLL2_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002030) +#define HWIO_GCC_GPLL2_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002034) +#define HWIO_GCC_GPLL2_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002034) +#define HWIO_GCC_GPLL2_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002034) +#define HWIO_GCC_GPLL2_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00002038) +#define HWIO_GCC_GPLL2_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002038) +#define HWIO_GCC_GPLL2_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002038) +#define HWIO_GCC_GPLL2_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000203c) +#define HWIO_GCC_GPLL2_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000203c) +#define HWIO_GCC_GPLL2_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000203c) +#define HWIO_GCC_GPLL2_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002040) +#define HWIO_GCC_GPLL2_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002040) +#define HWIO_GCC_GPLL2_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002040) +#define HWIO_GCC_GPLL2_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00002044) +#define HWIO_GCC_GPLL2_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002044) +#define HWIO_GCC_GPLL2_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002044) +#define HWIO_GCC_GPLL2_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002048) +#define HWIO_GCC_GPLL2_SSC_DELTA_ALPHA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00002048) +#define HWIO_GCC_GPLL2_SSC_DELTA_ALPHA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00002048) +#define HWIO_GCC_GPLL2_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000204c) +#define HWIO_GCC_GPLL2_SSC_UPDATE_RATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000204c) +#define HWIO_GCC_GPLL2_SSC_UPDATE_RATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000204c) +#define HWIO_GCC_GPLL2_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00002050) +#define HWIO_GCC_GPLL2_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00002050) +#define HWIO_GCC_GPLL2_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00002050) +#define HWIO_GCC_GPLL3_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00003000) +#define HWIO_GCC_GPLL3_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003000) +#define HWIO_GCC_GPLL3_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003000) +#define HWIO_GCC_GPLL3_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00003004) +#define HWIO_GCC_GPLL3_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003004) +#define HWIO_GCC_GPLL3_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003004) +#define HWIO_GCC_GPLL3_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003008) +#define HWIO_GCC_GPLL3_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003008) +#define HWIO_GCC_GPLL3_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003008) +#define HWIO_GCC_GPLL3_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000300c) +#define HWIO_GCC_GPLL3_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000300c) +#define HWIO_GCC_GPLL3_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000300c) +#define HWIO_GCC_GPLL3_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003010) +#define HWIO_GCC_GPLL3_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003010) +#define HWIO_GCC_GPLL3_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003010) +#define HWIO_GCC_GPLL3_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003014) +#define HWIO_GCC_GPLL3_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003014) +#define HWIO_GCC_GPLL3_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003014) +#define HWIO_GCC_GPLL3_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003018) +#define HWIO_GCC_GPLL3_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003018) +#define HWIO_GCC_GPLL3_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003018) +#define HWIO_GCC_GPLL3_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000301c) +#define HWIO_GCC_GPLL3_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000301c) +#define HWIO_GCC_GPLL3_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000301c) +#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003020) +#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003020) +#define HWIO_GCC_GPLL3_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003020) +#define HWIO_GCC_GPLL3_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003024) +#define HWIO_GCC_GPLL3_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003024) +#define HWIO_GCC_GPLL3_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003024) +#define HWIO_GCC_GPLL3_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003028) +#define HWIO_GCC_GPLL3_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003028) +#define HWIO_GCC_GPLL3_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003028) +#define HWIO_GCC_GPLL3_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000302c) +#define HWIO_GCC_GPLL3_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000302c) +#define HWIO_GCC_GPLL3_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000302c) +#define HWIO_GCC_GPLL3_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00003030) +#define HWIO_GCC_GPLL3_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003030) +#define HWIO_GCC_GPLL3_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003030) +#define HWIO_GCC_GPLL3_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003034) +#define HWIO_GCC_GPLL3_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003034) +#define HWIO_GCC_GPLL3_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003034) +#define HWIO_GCC_GPLL3_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00003038) +#define HWIO_GCC_GPLL3_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003038) +#define HWIO_GCC_GPLL3_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003038) +#define HWIO_GCC_GPLL3_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000303c) +#define HWIO_GCC_GPLL3_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000303c) +#define HWIO_GCC_GPLL3_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000303c) +#define HWIO_GCC_GPLL3_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003040) +#define HWIO_GCC_GPLL3_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003040) +#define HWIO_GCC_GPLL3_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003040) +#define HWIO_GCC_GPLL3_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00003044) +#define HWIO_GCC_GPLL3_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003044) +#define HWIO_GCC_GPLL3_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003044) +#define HWIO_GCC_GPLL3_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003048) +#define HWIO_GCC_GPLL3_SSC_DELTA_ALPHA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00003048) +#define HWIO_GCC_GPLL3_SSC_DELTA_ALPHA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00003048) +#define HWIO_GCC_GPLL3_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000304c) +#define HWIO_GCC_GPLL3_SSC_UPDATE_RATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000304c) +#define HWIO_GCC_GPLL3_SSC_UPDATE_RATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000304c) +#define HWIO_GCC_GPLL3_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00003050) +#define HWIO_GCC_GPLL3_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00003050) +#define HWIO_GCC_GPLL3_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00003050) +#define HWIO_GCC_GPLL4_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076000) +#define HWIO_GCC_GPLL4_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076000) +#define HWIO_GCC_GPLL4_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076000) +#define HWIO_GCC_GPLL4_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076004) +#define HWIO_GCC_GPLL4_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076004) +#define HWIO_GCC_GPLL4_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076004) +#define HWIO_GCC_GPLL4_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076008) +#define HWIO_GCC_GPLL4_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076008) +#define HWIO_GCC_GPLL4_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076008) +#define HWIO_GCC_GPLL4_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007600c) +#define HWIO_GCC_GPLL4_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007600c) +#define HWIO_GCC_GPLL4_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007600c) +#define HWIO_GCC_GPLL4_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076010) +#define HWIO_GCC_GPLL4_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076010) +#define HWIO_GCC_GPLL4_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076010) +#define HWIO_GCC_GPLL4_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076014) +#define HWIO_GCC_GPLL4_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076014) +#define HWIO_GCC_GPLL4_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076014) +#define HWIO_GCC_GPLL4_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076018) +#define HWIO_GCC_GPLL4_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076018) +#define HWIO_GCC_GPLL4_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076018) +#define HWIO_GCC_GPLL4_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007601c) +#define HWIO_GCC_GPLL4_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007601c) +#define HWIO_GCC_GPLL4_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007601c) +#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076020) +#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076020) +#define HWIO_GCC_GPLL4_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076020) +#define HWIO_GCC_GPLL4_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076024) +#define HWIO_GCC_GPLL4_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076024) +#define HWIO_GCC_GPLL4_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076024) +#define HWIO_GCC_GPLL4_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076028) +#define HWIO_GCC_GPLL4_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076028) +#define HWIO_GCC_GPLL4_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076028) +#define HWIO_GCC_GPLL4_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007602c) +#define HWIO_GCC_GPLL4_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007602c) +#define HWIO_GCC_GPLL4_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007602c) +#define HWIO_GCC_GPLL4_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076030) +#define HWIO_GCC_GPLL4_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076030) +#define HWIO_GCC_GPLL4_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076030) +#define HWIO_GCC_GPLL4_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076034) +#define HWIO_GCC_GPLL4_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076034) +#define HWIO_GCC_GPLL4_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076034) +#define HWIO_GCC_GPLL4_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076038) +#define HWIO_GCC_GPLL4_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076038) +#define HWIO_GCC_GPLL4_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076038) +#define HWIO_GCC_GPLL4_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007603c) +#define HWIO_GCC_GPLL4_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007603c) +#define HWIO_GCC_GPLL4_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007603c) +#define HWIO_GCC_GPLL4_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076040) +#define HWIO_GCC_GPLL4_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076040) +#define HWIO_GCC_GPLL4_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076040) +#define HWIO_GCC_GPLL4_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00076044) +#define HWIO_GCC_GPLL4_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076044) +#define HWIO_GCC_GPLL4_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076044) +#define HWIO_GCC_GPLL4_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076048) +#define HWIO_GCC_GPLL4_SSC_DELTA_ALPHA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00076048) +#define HWIO_GCC_GPLL4_SSC_DELTA_ALPHA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00076048) +#define HWIO_GCC_GPLL4_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007604c) +#define HWIO_GCC_GPLL4_SSC_UPDATE_RATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0007604c) +#define HWIO_GCC_GPLL4_SSC_UPDATE_RATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0007604c) +#define HWIO_GCC_GPLL4_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00076050) +#define HWIO_GCC_GPLL4_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00076050) +#define HWIO_GCC_GPLL4_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00076050) +#define HWIO_GCC_GPLL5_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00074000) +#define HWIO_GCC_GPLL5_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074000) +#define HWIO_GCC_GPLL5_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074000) +#define HWIO_GCC_GPLL5_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00074004) +#define HWIO_GCC_GPLL5_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074004) +#define HWIO_GCC_GPLL5_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074004) +#define HWIO_GCC_GPLL5_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074008) +#define HWIO_GCC_GPLL5_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074008) +#define HWIO_GCC_GPLL5_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074008) +#define HWIO_GCC_GPLL5_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007400c) +#define HWIO_GCC_GPLL5_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007400c) +#define HWIO_GCC_GPLL5_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007400c) +#define HWIO_GCC_GPLL5_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074010) +#define HWIO_GCC_GPLL5_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074010) +#define HWIO_GCC_GPLL5_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074010) +#define HWIO_GCC_GPLL5_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074014) +#define HWIO_GCC_GPLL5_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074014) +#define HWIO_GCC_GPLL5_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074014) +#define HWIO_GCC_GPLL5_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074018) +#define HWIO_GCC_GPLL5_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074018) +#define HWIO_GCC_GPLL5_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074018) +#define HWIO_GCC_GPLL5_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007401c) +#define HWIO_GCC_GPLL5_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007401c) +#define HWIO_GCC_GPLL5_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007401c) +#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074020) +#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074020) +#define HWIO_GCC_GPLL5_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074020) +#define HWIO_GCC_GPLL5_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074024) +#define HWIO_GCC_GPLL5_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074024) +#define HWIO_GCC_GPLL5_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074024) +#define HWIO_GCC_GPLL5_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074028) +#define HWIO_GCC_GPLL5_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074028) +#define HWIO_GCC_GPLL5_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074028) +#define HWIO_GCC_GPLL5_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007402c) +#define HWIO_GCC_GPLL5_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007402c) +#define HWIO_GCC_GPLL5_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007402c) +#define HWIO_GCC_GPLL5_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00074030) +#define HWIO_GCC_GPLL5_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074030) +#define HWIO_GCC_GPLL5_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074030) +#define HWIO_GCC_GPLL5_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074034) +#define HWIO_GCC_GPLL5_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074034) +#define HWIO_GCC_GPLL5_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074034) +#define HWIO_GCC_GPLL5_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00074038) +#define HWIO_GCC_GPLL5_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074038) +#define HWIO_GCC_GPLL5_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074038) +#define HWIO_GCC_GPLL5_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007403c) +#define HWIO_GCC_GPLL5_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007403c) +#define HWIO_GCC_GPLL5_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007403c) +#define HWIO_GCC_GPLL5_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074040) +#define HWIO_GCC_GPLL5_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074040) +#define HWIO_GCC_GPLL5_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074040) +#define HWIO_GCC_GPLL5_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00074044) +#define HWIO_GCC_GPLL5_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074044) +#define HWIO_GCC_GPLL5_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074044) +#define HWIO_GCC_GPLL5_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074048) +#define HWIO_GCC_GPLL5_SSC_DELTA_ALPHA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00074048) +#define HWIO_GCC_GPLL5_SSC_DELTA_ALPHA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00074048) +#define HWIO_GCC_GPLL5_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007404c) +#define HWIO_GCC_GPLL5_SSC_UPDATE_RATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0007404c) +#define HWIO_GCC_GPLL5_SSC_UPDATE_RATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0007404c) +#define HWIO_GCC_GPLL5_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00074050) +#define HWIO_GCC_GPLL5_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00074050) +#define HWIO_GCC_GPLL5_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00074050) +#define HWIO_GCC_GPLL6_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013000) +#define HWIO_GCC_GPLL6_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013000) +#define HWIO_GCC_GPLL6_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013000) +#define HWIO_GCC_GPLL6_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013004) +#define HWIO_GCC_GPLL6_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013004) +#define HWIO_GCC_GPLL6_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013004) +#define HWIO_GCC_GPLL6_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013008) +#define HWIO_GCC_GPLL6_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013008) +#define HWIO_GCC_GPLL6_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013008) +#define HWIO_GCC_GPLL6_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001300c) +#define HWIO_GCC_GPLL6_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001300c) +#define HWIO_GCC_GPLL6_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001300c) +#define HWIO_GCC_GPLL6_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013010) +#define HWIO_GCC_GPLL6_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013010) +#define HWIO_GCC_GPLL6_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013010) +#define HWIO_GCC_GPLL6_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013014) +#define HWIO_GCC_GPLL6_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013014) +#define HWIO_GCC_GPLL6_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013014) +#define HWIO_GCC_GPLL6_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013018) +#define HWIO_GCC_GPLL6_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013018) +#define HWIO_GCC_GPLL6_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013018) +#define HWIO_GCC_GPLL6_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001301c) +#define HWIO_GCC_GPLL6_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001301c) +#define HWIO_GCC_GPLL6_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001301c) +#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013020) +#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013020) +#define HWIO_GCC_GPLL6_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013020) +#define HWIO_GCC_GPLL6_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013024) +#define HWIO_GCC_GPLL6_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013024) +#define HWIO_GCC_GPLL6_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013024) +#define HWIO_GCC_GPLL6_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013028) +#define HWIO_GCC_GPLL6_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013028) +#define HWIO_GCC_GPLL6_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013028) +#define HWIO_GCC_GPLL6_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001302c) +#define HWIO_GCC_GPLL6_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001302c) +#define HWIO_GCC_GPLL6_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001302c) +#define HWIO_GCC_GPLL6_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013030) +#define HWIO_GCC_GPLL6_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013030) +#define HWIO_GCC_GPLL6_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013030) +#define HWIO_GCC_GPLL6_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013034) +#define HWIO_GCC_GPLL6_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013034) +#define HWIO_GCC_GPLL6_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013034) +#define HWIO_GCC_GPLL6_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013038) +#define HWIO_GCC_GPLL6_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013038) +#define HWIO_GCC_GPLL6_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013038) +#define HWIO_GCC_GPLL6_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001303c) +#define HWIO_GCC_GPLL6_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001303c) +#define HWIO_GCC_GPLL6_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001303c) +#define HWIO_GCC_GPLL6_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013040) +#define HWIO_GCC_GPLL6_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013040) +#define HWIO_GCC_GPLL6_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013040) +#define HWIO_GCC_GPLL6_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00013044) +#define HWIO_GCC_GPLL6_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013044) +#define HWIO_GCC_GPLL6_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013044) +#define HWIO_GCC_GPLL6_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013048) +#define HWIO_GCC_GPLL6_SSC_DELTA_ALPHA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00013048) +#define HWIO_GCC_GPLL6_SSC_DELTA_ALPHA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00013048) +#define HWIO_GCC_GPLL6_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001304c) +#define HWIO_GCC_GPLL6_SSC_UPDATE_RATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001304c) +#define HWIO_GCC_GPLL6_SSC_UPDATE_RATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001304c) +#define HWIO_GCC_GPLL6_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00013050) +#define HWIO_GCC_GPLL6_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00013050) +#define HWIO_GCC_GPLL6_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00013050) +#define HWIO_GCC_GPLL7_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a000) +#define HWIO_GCC_GPLL7_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a000) +#define HWIO_GCC_GPLL7_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a000) +#define HWIO_GCC_GPLL7_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a004) +#define HWIO_GCC_GPLL7_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a004) +#define HWIO_GCC_GPLL7_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a004) +#define HWIO_GCC_GPLL7_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a008) +#define HWIO_GCC_GPLL7_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a008) +#define HWIO_GCC_GPLL7_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a008) +#define HWIO_GCC_GPLL7_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a00c) +#define HWIO_GCC_GPLL7_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a00c) +#define HWIO_GCC_GPLL7_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a00c) +#define HWIO_GCC_GPLL7_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a010) +#define HWIO_GCC_GPLL7_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a010) +#define HWIO_GCC_GPLL7_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a010) +#define HWIO_GCC_GPLL7_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a014) +#define HWIO_GCC_GPLL7_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a014) +#define HWIO_GCC_GPLL7_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a014) +#define HWIO_GCC_GPLL7_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a018) +#define HWIO_GCC_GPLL7_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a018) +#define HWIO_GCC_GPLL7_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a018) +#define HWIO_GCC_GPLL7_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a01c) +#define HWIO_GCC_GPLL7_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a01c) +#define HWIO_GCC_GPLL7_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a01c) +#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a020) +#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a020) +#define HWIO_GCC_GPLL7_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a020) +#define HWIO_GCC_GPLL7_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a024) +#define HWIO_GCC_GPLL7_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a024) +#define HWIO_GCC_GPLL7_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a024) +#define HWIO_GCC_GPLL7_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a028) +#define HWIO_GCC_GPLL7_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a028) +#define HWIO_GCC_GPLL7_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a028) +#define HWIO_GCC_GPLL7_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a02c) +#define HWIO_GCC_GPLL7_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a02c) +#define HWIO_GCC_GPLL7_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a02c) +#define HWIO_GCC_GPLL7_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a030) +#define HWIO_GCC_GPLL7_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a030) +#define HWIO_GCC_GPLL7_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a030) +#define HWIO_GCC_GPLL7_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a034) +#define HWIO_GCC_GPLL7_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a034) +#define HWIO_GCC_GPLL7_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a034) +#define HWIO_GCC_GPLL7_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a038) +#define HWIO_GCC_GPLL7_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a038) +#define HWIO_GCC_GPLL7_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a038) +#define HWIO_GCC_GPLL7_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a03c) +#define HWIO_GCC_GPLL7_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a03c) +#define HWIO_GCC_GPLL7_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a03c) +#define HWIO_GCC_GPLL7_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a040) +#define HWIO_GCC_GPLL7_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a040) +#define HWIO_GCC_GPLL7_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a040) +#define HWIO_GCC_GPLL7_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001a044) +#define HWIO_GCC_GPLL7_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a044) +#define HWIO_GCC_GPLL7_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a044) +#define HWIO_GCC_GPLL7_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a048) +#define HWIO_GCC_GPLL7_SSC_DELTA_ALPHA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001a048) +#define HWIO_GCC_GPLL7_SSC_DELTA_ALPHA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001a048) +#define HWIO_GCC_GPLL7_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a04c) +#define HWIO_GCC_GPLL7_SSC_UPDATE_RATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001a04c) +#define HWIO_GCC_GPLL7_SSC_UPDATE_RATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001a04c) +#define HWIO_GCC_GPLL7_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001a050) +#define HWIO_GCC_GPLL7_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001a050) +#define HWIO_GCC_GPLL7_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001a050) +#define HWIO_GCC_GPLL8_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b000) +#define HWIO_GCC_GPLL8_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b000) +#define HWIO_GCC_GPLL8_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b000) +#define HWIO_GCC_GPLL8_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b004) +#define HWIO_GCC_GPLL8_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b004) +#define HWIO_GCC_GPLL8_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b004) +#define HWIO_GCC_GPLL8_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b008) +#define HWIO_GCC_GPLL8_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b008) +#define HWIO_GCC_GPLL8_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b008) +#define HWIO_GCC_GPLL8_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b00c) +#define HWIO_GCC_GPLL8_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b00c) +#define HWIO_GCC_GPLL8_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b00c) +#define HWIO_GCC_GPLL8_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b010) +#define HWIO_GCC_GPLL8_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b010) +#define HWIO_GCC_GPLL8_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b010) +#define HWIO_GCC_GPLL8_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b014) +#define HWIO_GCC_GPLL8_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b014) +#define HWIO_GCC_GPLL8_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b014) +#define HWIO_GCC_GPLL8_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b018) +#define HWIO_GCC_GPLL8_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b018) +#define HWIO_GCC_GPLL8_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b018) +#define HWIO_GCC_GPLL8_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b01c) +#define HWIO_GCC_GPLL8_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b01c) +#define HWIO_GCC_GPLL8_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b01c) +#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b020) +#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b020) +#define HWIO_GCC_GPLL8_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b020) +#define HWIO_GCC_GPLL8_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b024) +#define HWIO_GCC_GPLL8_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b024) +#define HWIO_GCC_GPLL8_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b024) +#define HWIO_GCC_GPLL8_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b028) +#define HWIO_GCC_GPLL8_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b028) +#define HWIO_GCC_GPLL8_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b028) +#define HWIO_GCC_GPLL8_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b02c) +#define HWIO_GCC_GPLL8_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b02c) +#define HWIO_GCC_GPLL8_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b02c) +#define HWIO_GCC_GPLL8_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b030) +#define HWIO_GCC_GPLL8_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b030) +#define HWIO_GCC_GPLL8_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b030) +#define HWIO_GCC_GPLL8_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b034) +#define HWIO_GCC_GPLL8_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b034) +#define HWIO_GCC_GPLL8_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b034) +#define HWIO_GCC_GPLL8_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b038) +#define HWIO_GCC_GPLL8_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b038) +#define HWIO_GCC_GPLL8_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b038) +#define HWIO_GCC_GPLL8_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b03c) +#define HWIO_GCC_GPLL8_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b03c) +#define HWIO_GCC_GPLL8_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b03c) +#define HWIO_GCC_GPLL8_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b040) +#define HWIO_GCC_GPLL8_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b040) +#define HWIO_GCC_GPLL8_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b040) +#define HWIO_GCC_GPLL8_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001b044) +#define HWIO_GCC_GPLL8_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b044) +#define HWIO_GCC_GPLL8_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b044) +#define HWIO_GCC_GPLL8_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b048) +#define HWIO_GCC_GPLL8_SSC_DELTA_ALPHA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001b048) +#define HWIO_GCC_GPLL8_SSC_DELTA_ALPHA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001b048) +#define HWIO_GCC_GPLL8_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b04c) +#define HWIO_GCC_GPLL8_SSC_UPDATE_RATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001b04c) +#define HWIO_GCC_GPLL8_SSC_UPDATE_RATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001b04c) +#define HWIO_GCC_GPLL8_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001b050) +#define HWIO_GCC_GPLL8_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001b050) +#define HWIO_GCC_GPLL8_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001b050) +#define HWIO_GCC_GPLL9_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c000) +#define HWIO_GCC_GPLL9_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c000) +#define HWIO_GCC_GPLL9_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c000) +#define HWIO_GCC_GPLL9_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c004) +#define HWIO_GCC_GPLL9_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c004) +#define HWIO_GCC_GPLL9_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c004) +#define HWIO_GCC_GPLL9_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c008) +#define HWIO_GCC_GPLL9_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c008) +#define HWIO_GCC_GPLL9_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c008) +#define HWIO_GCC_GPLL9_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c00c) +#define HWIO_GCC_GPLL9_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c00c) +#define HWIO_GCC_GPLL9_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c00c) +#define HWIO_GCC_GPLL9_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c010) +#define HWIO_GCC_GPLL9_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c010) +#define HWIO_GCC_GPLL9_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c010) +#define HWIO_GCC_GPLL9_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c014) +#define HWIO_GCC_GPLL9_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c014) +#define HWIO_GCC_GPLL9_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c014) +#define HWIO_GCC_GPLL9_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c018) +#define HWIO_GCC_GPLL9_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c018) +#define HWIO_GCC_GPLL9_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c018) +#define HWIO_GCC_GPLL9_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c01c) +#define HWIO_GCC_GPLL9_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c01c) +#define HWIO_GCC_GPLL9_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c01c) +#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c020) +#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c020) +#define HWIO_GCC_GPLL9_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c020) +#define HWIO_GCC_GPLL9_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c024) +#define HWIO_GCC_GPLL9_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c024) +#define HWIO_GCC_GPLL9_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c024) +#define HWIO_GCC_GPLL9_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c028) +#define HWIO_GCC_GPLL9_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c028) +#define HWIO_GCC_GPLL9_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c028) +#define HWIO_GCC_GPLL9_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c02c) +#define HWIO_GCC_GPLL9_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c02c) +#define HWIO_GCC_GPLL9_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c02c) +#define HWIO_GCC_GPLL9_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c030) +#define HWIO_GCC_GPLL9_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c030) +#define HWIO_GCC_GPLL9_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c030) +#define HWIO_GCC_GPLL9_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c034) +#define HWIO_GCC_GPLL9_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c034) +#define HWIO_GCC_GPLL9_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c034) +#define HWIO_GCC_GPLL9_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c038) +#define HWIO_GCC_GPLL9_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c038) +#define HWIO_GCC_GPLL9_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c038) +#define HWIO_GCC_GPLL9_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c03c) +#define HWIO_GCC_GPLL9_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c03c) +#define HWIO_GCC_GPLL9_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c03c) +#define HWIO_GCC_GPLL9_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c040) +#define HWIO_GCC_GPLL9_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c040) +#define HWIO_GCC_GPLL9_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c040) +#define HWIO_GCC_GPLL9_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001c044) +#define HWIO_GCC_GPLL9_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c044) +#define HWIO_GCC_GPLL9_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c044) +#define HWIO_GCC_GPLL9_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c048) +#define HWIO_GCC_GPLL9_SSC_DELTA_ALPHA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001c048) +#define HWIO_GCC_GPLL9_SSC_DELTA_ALPHA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001c048) +#define HWIO_GCC_GPLL9_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c04c) +#define HWIO_GCC_GPLL9_SSC_UPDATE_RATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001c04c) +#define HWIO_GCC_GPLL9_SSC_UPDATE_RATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001c04c) +#define HWIO_GCC_GPLL9_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001c050) +#define HWIO_GCC_GPLL9_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001c050) +#define HWIO_GCC_GPLL9_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001c050) +#define HWIO_GCC_GPLL10_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001d000) +#define HWIO_GCC_GPLL10_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d000) +#define HWIO_GCC_GPLL10_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d000) +#define HWIO_GCC_GPLL10_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001d004) +#define HWIO_GCC_GPLL10_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d004) +#define HWIO_GCC_GPLL10_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d004) +#define HWIO_GCC_GPLL10_CAL_L_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d008) +#define HWIO_GCC_GPLL10_CAL_L_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d008) +#define HWIO_GCC_GPLL10_CAL_L_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d008) +#define HWIO_GCC_GPLL10_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d00c) +#define HWIO_GCC_GPLL10_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d00c) +#define HWIO_GCC_GPLL10_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d00c) +#define HWIO_GCC_GPLL10_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d010) +#define HWIO_GCC_GPLL10_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d010) +#define HWIO_GCC_GPLL10_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d010) +#define HWIO_GCC_GPLL10_USER_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d014) +#define HWIO_GCC_GPLL10_USER_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d014) +#define HWIO_GCC_GPLL10_USER_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d014) +#define HWIO_GCC_GPLL10_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d018) +#define HWIO_GCC_GPLL10_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d018) +#define HWIO_GCC_GPLL10_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d018) +#define HWIO_GCC_GPLL10_CONFIG_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d01c) +#define HWIO_GCC_GPLL10_CONFIG_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d01c) +#define HWIO_GCC_GPLL10_CONFIG_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d01c) +#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d020) +#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001d020) +#define HWIO_GCC_GPLL10_CONFIG_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001d020) +#define HWIO_GCC_GPLL10_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d024) +#define HWIO_GCC_GPLL10_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d024) +#define HWIO_GCC_GPLL10_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d024) +#define HWIO_GCC_GPLL10_TEST_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d028) +#define HWIO_GCC_GPLL10_TEST_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d028) +#define HWIO_GCC_GPLL10_TEST_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d028) +#define HWIO_GCC_GPLL10_TEST_CTL_U1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d02c) +#define HWIO_GCC_GPLL10_TEST_CTL_U1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d02c) +#define HWIO_GCC_GPLL10_TEST_CTL_U1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d02c) +#define HWIO_GCC_GPLL10_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001d030) +#define HWIO_GCC_GPLL10_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d030) +#define HWIO_GCC_GPLL10_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d030) +#define HWIO_GCC_GPLL10_FREQ_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d034) +#define HWIO_GCC_GPLL10_FREQ_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d034) +#define HWIO_GCC_GPLL10_FREQ_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d034) +#define HWIO_GCC_GPLL10_OPMODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001d038) +#define HWIO_GCC_GPLL10_OPMODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d038) +#define HWIO_GCC_GPLL10_OPMODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d038) +#define HWIO_GCC_GPLL10_STATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001d03c) +#define HWIO_GCC_GPLL10_STATE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d03c) +#define HWIO_GCC_GPLL10_STATE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d03c) +#define HWIO_GCC_GPLL10_ALPHA_VAL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d040) +#define HWIO_GCC_GPLL10_ALPHA_VAL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d040) +#define HWIO_GCC_GPLL10_ALPHA_VAL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d040) +#define HWIO_GCC_GPLL10_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001d044) +#define HWIO_GCC_GPLL10_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001d044) +#define HWIO_GCC_GPLL10_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001d044) +#define HWIO_GCC_GPLL10_SSC_DELTA_ALPHA_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d048) +#define HWIO_GCC_GPLL10_SSC_DELTA_ALPHA_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001d048) +#define HWIO_GCC_GPLL10_SSC_DELTA_ALPHA_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001d048) +#define HWIO_GCC_GPLL10_SSC_UPDATE_RATE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d04c) +#define HWIO_GCC_GPLL10_SSC_UPDATE_RATE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001d04c) +#define HWIO_GCC_GPLL10_SSC_UPDATE_RATE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001d04c) +#define HWIO_GCC_GPLL10_SSC_NUM_STEPS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001d050) +#define HWIO_GCC_GPLL10_SSC_NUM_STEPS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001d050) +#define HWIO_GCC_GPLL10_SSC_NUM_STEPS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001d050) +#define HWIO_GCC_SYSTEM_NOC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004000) +#define HWIO_GCC_SYSTEM_NOC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00004000) +#define HWIO_GCC_SYSTEM_NOC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00004000) +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004004) +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00004004) +#define HWIO_GCC_SYS_NOC_GC_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00004004) +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000401c) +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000401c) +#define HWIO_GCC_RPMH_SYS_NOC_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000401c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004024) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004024) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004024) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004028) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004028) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004028) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000402c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000402c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000402c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004030) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004030) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004030) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004034) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004034) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004034) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004038) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004038) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004038) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000403c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000403c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000403c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004040) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004040) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004040) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004044) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004044) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004044) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004048) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004048) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004048) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000404c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000404c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000404c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004050) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004050) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004050) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004054) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004054) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004054) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004058) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004058) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004058) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000405c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000405c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000405c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004060) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004060) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_GC_AXI_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004060) +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004008) +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004008) +#define HWIO_GCC_SYS_NOC_GC_AXI_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004008) +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000400c) +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000400c) +#define HWIO_GCC_SYS_NOC_GC_AXI_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000400c) +#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004134) +#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004134) +#define HWIO_GCC_SYS_NOC_GC_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004134) +#define HWIO_GCC_SYS_NOC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004138) +#define HWIO_GCC_SYS_NOC_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00004138) +#define HWIO_GCC_SYS_NOC_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00004138) +#define HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000413c) +#define HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000413c) +#define HWIO_GCC_SYS_NOC_SOUTH_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000413c) +#define HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004140) +#define HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004140) +#define HWIO_GCC_SYS_NOC_NORTH_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004140) +#define HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004144) +#define HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00004144) +#define HWIO_GCC_SYS_NOC_WEST_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00004144) +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00004148) +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004148) +#define HWIO_GCC_SYS_NOC_QDSS_STM_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004148) +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004819c) +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004819c) +#define HWIO_GCC_SYS_NOC_CPUSS_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004819c) +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000414c) +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000414c) +#define HWIO_GCC_SYS_NOC_AHB_CFG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000414c) +#define HWIO_GCC_SYS_NOC_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004150) +#define HWIO_GCC_SYS_NOC_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00004150) +#define HWIO_GCC_SYS_NOC_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00004150) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004170) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004170) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004170) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004174) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004174) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004174) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004178) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004178) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004178) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000417c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000417c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000417c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004180) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004180) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004180) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004184) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004184) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004184) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004188) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004188) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004188) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000418c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000418c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000418c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004190) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004190) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004190) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004194) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004194) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004194) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004198) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004198) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004198) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000419c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000419c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000419c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000041a0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000041a0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000041a0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000041a4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000041a4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000041a4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000041a8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000041a8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000041a8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000041ac) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000041ac) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000041ac) +#define HWIO_GCC_SYS_NOC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004154) +#define HWIO_GCC_SYS_NOC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00004154) +#define HWIO_GCC_SYS_NOC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00004154) +#define HWIO_GCC_SYS_NOC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004158) +#define HWIO_GCC_SYS_NOC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00004158) +#define HWIO_GCC_SYS_NOC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00004158) +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004280) +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00004280) +#define HWIO_GCC_SYS_NOC_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00004280) +#define HWIO_GCC_SYS_NOC_MONAQ_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004284) +#define HWIO_GCC_SYS_NOC_MONAQ_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00004284) +#define HWIO_GCC_SYS_NOC_MONAQ_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00004284) +#define HWIO_GCC_SYS_NOC_WEST_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00004288) +#define HWIO_GCC_SYS_NOC_WEST_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004288) +#define HWIO_GCC_SYS_NOC_WEST_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004288) +#define HWIO_GCC_SYS_NOC_SOUTH_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000428c) +#define HWIO_GCC_SYS_NOC_SOUTH_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000428c) +#define HWIO_GCC_SYS_NOC_SOUTH_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000428c) +#define HWIO_GCC_SYS_NOC_NORTH_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004290) +#define HWIO_GCC_SYS_NOC_NORTH_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004290) +#define HWIO_GCC_SYS_NOC_NORTH_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004290) +#define HWIO_GCC_SYS_NOC_MONAQ_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004294) +#define HWIO_GCC_SYS_NOC_MONAQ_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004294) +#define HWIO_GCC_SYS_NOC_MONAQ_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004294) +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00004298) +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004298) +#define HWIO_GCC_SNOC_QOSGEN_EXTREF_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004298) +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000429c) +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000429c) +#define HWIO_GCC_SYS_NOC_SF_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000429c) +#define HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000042a0) +#define HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042a0) +#define HWIO_GCC_SYS_NOC_SF_WEST_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042a0) +#define HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000042a4) +#define HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042a4) +#define HWIO_GCC_SYS_NOC_SF_NORTH_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042a4) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000042a8) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042a8) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042a8) +#define HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000042ac) +#define HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042ac) +#define HWIO_GCC_SYS_NOC_MONAQ_SF_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042ac) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042cc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042cc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042cc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042d0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042d0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042d0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042d4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042d4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042d4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042d8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042d8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042d8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042dc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042dc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042dc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042e0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042e0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042e0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042e4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042e4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042e4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042e8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042e8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042e8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042ec) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042ec) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042ec) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042f0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042f0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042f0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042f4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042f4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042f4) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042f8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042f8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042f8) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000042fc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042fc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042fc) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004300) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004300) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004300) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004304) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004304) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004304) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004308) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004308) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_SF_AXI_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004308) +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000042b0) +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042b0) +#define HWIO_GCC_SYS_NOC_SF_AXI_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042b0) +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000042b4) +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000042b4) +#define HWIO_GCC_SYS_NOC_SF_AXI_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000042b4) +#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000043dc) +#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000043dc) +#define HWIO_GCC_SYS_NOC_SF_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000043dc) +#define HWIO_GCC_SYS_NOC_MONAQ_SF_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000043e0) +#define HWIO_GCC_SYS_NOC_MONAQ_SF_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000043e0) +#define HWIO_GCC_SYS_NOC_MONAQ_SF_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000043e0) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004400) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004400) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004400) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004404) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004404) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004404) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004408) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004408) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004408) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000440c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000440c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000440c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004410) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004410) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004410) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004414) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004414) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004414) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004418) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004418) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004418) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000441c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000441c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000441c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004420) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004420) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004420) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004424) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004424) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004424) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004428) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004428) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004428) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000442c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000442c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000442c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004430) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004430) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004430) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004434) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004434) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004434) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004438) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004438) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004438) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000443c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000443c) +#define HWIO_GCC_RPMH_SYS_NOC_SYS_NOC_MONAQ_AXI_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000443c) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000043e4) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000043e4) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000043e4) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000043e8) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000043e8) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000043e8) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00004510) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00004510) +#define HWIO_GCC_SYS_NOC_MONAQ_AXI_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00004510) +#define HWIO_GCC_CONFIG_NOC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005000) +#define HWIO_GCC_CONFIG_NOC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00005000) +#define HWIO_GCC_CONFIG_NOC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00005000) +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005004) +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005004) +#define HWIO_GCC_CNOC_PERIPH_SOUTH_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005004) +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005008) +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005008) +#define HWIO_GCC_CNOC_PERIPH_NORTH_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005008) +#define HWIO_GCC_CNOC_PERIPH_EAST_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000500c) +#define HWIO_GCC_CNOC_PERIPH_EAST_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000500c) +#define HWIO_GCC_CNOC_PERIPH_EAST_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000500c) +#define HWIO_GCC_CFG_NOC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005010) +#define HWIO_GCC_CFG_NOC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00005010) +#define HWIO_GCC_CFG_NOC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00005010) +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005014) +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00005014) +#define HWIO_GCC_CFG_NOC_WEST_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00005014) +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005018) +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005018) +#define HWIO_GCC_CFG_NOC_NORTH_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005018) +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000501c) +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000501c) +#define HWIO_GCC_CFG_NOC_EAST_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000501c) +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005020) +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005020) +#define HWIO_GCC_CFG_NOC_SOUTH_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005020) +#define HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005024) +#define HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005024) +#define HWIO_GCC_CFG_NOC_MONAQ_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005024) +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005028) +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005028) +#define HWIO_GCC_CFG_NOC_MMNOC_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005028) +#define HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000502c) +#define HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000502c) +#define HWIO_GCC_CFG_NOC_COMPUTE_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000502c) +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0000f078) +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f078) +#define HWIO_GCC_CFG_NOC_USB3_PRIM_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f078) +#define HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00010078) +#define HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010078) +#define HWIO_GCC_CFG_NOC_USB3_SEC_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010078) +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005030) +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00005030) +#define HWIO_GCC_NOC_WEST_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00005030) +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005034) +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00005034) +#define HWIO_GCC_NOC_NORTH_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00005034) +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005038) +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00005038) +#define HWIO_GCC_NOC_SOUTH_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00005038) +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000503c) +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000503c) +#define HWIO_GCC_NOC_EAST_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000503c) +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005040) +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005040) +#define HWIO_GCC_NOC_CENTER_DCD_XO_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005040) +#define HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005044) +#define HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00005044) +#define HWIO_GCC_NOC_MONAQ_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00005044) +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005048) +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005048) +#define HWIO_GCC_CFG_NOC_AH2PHY_XO_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005048) +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000504c) +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000504c) +#define HWIO_GCC_NOC_LPASS_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000504c) +#define HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005050) +#define HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005050) +#define HWIO_GCC_NOC_COMPUTE_DCD_XO_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005050) +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00005054) +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005054) +#define HWIO_GCC_NOC_MMNOC_CNOC_DCD_XO_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005054) +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000506c) +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000506c) +#define HWIO_GCC_RPMH_CNOC_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000506c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00005074) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005074) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005074) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00005078) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005078) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005078) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000507c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000507c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000507c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00005080) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005080) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005080) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00005084) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005084) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005084) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00005088) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005088) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005088) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000508c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000508c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000508c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00005090) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005090) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005090) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00005094) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005094) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005094) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00005098) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00005098) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00005098) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000509c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000509c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000509c) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000050a0) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000050a0) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000050a0) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000050a4) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000050a4) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000050a4) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000050a8) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000050a8) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000050a8) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000050ac) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000050ac) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000050ac) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000050b0) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000050b0) +#define HWIO_GCC_RPMH_CNOC_CONFIG_NOC_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000050b0) +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005058) +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00005058) +#define HWIO_GCC_CONFIG_NOC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00005058) +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000505c) +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000505c) +#define HWIO_GCC_CONFIG_NOC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000505c) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051a0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051a0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051a0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051a4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051a4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051a4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051a8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051a8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051a8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051ac) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051ac) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051ac) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051b0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051b0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051b0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051b4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051b4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051b4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051b8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051b8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051b8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051bc) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051bc) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051bc) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051c0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051c0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051c0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051c4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051c4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051c4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051c8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051c8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051c8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051cc) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051cc) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051cc) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051d0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051d0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051d0) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051d4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051d4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051d4) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051d8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051d8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051d8) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000051dc) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000051dc) +#define HWIO_GCC_RPMH_CNOC_CNOC_PERIPH_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000051dc) +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005184) +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00005184) +#define HWIO_GCC_CNOC_PERIPH_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00005184) +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00005188) +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00005188) +#define HWIO_GCC_CNOC_PERIPH_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00005188) +#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000052b0) +#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000052b0) +#define HWIO_GCC_CONFIG_NOC_CENTER_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000052b0) +#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000052b4) +#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000052b4) +#define HWIO_GCC_CONFIG_NOC_WEST_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000052b4) +#define HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000052b8) +#define HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000052b8) +#define HWIO_GCC_CONFIG_NOC_EAST_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000052b8) +#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000052bc) +#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000052bc) +#define HWIO_GCC_CONFIG_NOC_NORTH_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000052bc) +#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000052c0) +#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000052c0) +#define HWIO_GCC_CONFIG_NOC_SOUTH_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000052c0) +#define HWIO_GCC_CONFIG_NOC_MONAQ_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000052c4) +#define HWIO_GCC_CONFIG_NOC_MONAQ_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000052c4) +#define HWIO_GCC_CONFIG_NOC_MONAQ_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000052c4) +#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000052c8) +#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000052c8) +#define HWIO_GCC_CONFIG_NOC_MMNOC_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000052c8) +#define HWIO_GCC_CONFIG_NOC_COMPUTE_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000052cc) +#define HWIO_GCC_CONFIG_NOC_COMPUTE_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000052cc) +#define HWIO_GCC_CONFIG_NOC_COMPUTE_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000052cc) +#define HWIO_GCC_TIC_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000e000) +#define HWIO_GCC_TIC_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000e000) +#define HWIO_GCC_TIC_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000e000) +#define HWIO_GCC_IMEM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008000) +#define HWIO_GCC_IMEM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00008000) +#define HWIO_GCC_IMEM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00008000) +#define HWIO_GCC_IMEM_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00008004) +#define HWIO_GCC_IMEM_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00008004) +#define HWIO_GCC_IMEM_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00008004) +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00008008) +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00008008) +#define HWIO_GCC_IMEM_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00008008) +#define HWIO_GCC_MMU_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083000) +#define HWIO_GCC_MMU_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083000) +#define HWIO_GCC_MMU_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083000) +#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00083004) +#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00083004) +#define HWIO_GCC_SYS_NOC_SF_TCU_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00083004) +#define HWIO_GCC_MMU_TCU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00083008) +#define HWIO_GCC_MMU_TCU_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00083008) +#define HWIO_GCC_MMU_TCU_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00083008) +#define HWIO_GCC_MMU_TCU_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008300c) +#define HWIO_GCC_MMU_TCU_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008300c) +#define HWIO_GCC_MMU_TCU_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008300c) +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00083024) +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00083024) +#define HWIO_GCC_RPMH_SHUB_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00083024) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008302c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008302c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008302c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083030) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083030) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083030) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083034) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083034) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083034) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083038) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083038) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083038) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008303c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008303c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008303c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083040) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083040) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083040) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083044) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083044) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083044) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083048) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083048) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083048) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008304c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008304c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008304c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083050) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083050) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083050) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083054) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083054) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083054) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083058) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083058) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083058) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008305c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008305c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008305c) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083060) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083060) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083060) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083064) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083064) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083064) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00083068) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00083068) +#define HWIO_GCC_RPMH_SHUB_MMU_TCU_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00083068) +#define HWIO_GCC_MMU_TCU_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00083010) +#define HWIO_GCC_MMU_TCU_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00083010) +#define HWIO_GCC_MMU_TCU_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00083010) +#define HWIO_GCC_MMU_TCU_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00083014) +#define HWIO_GCC_MMU_TCU_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00083014) +#define HWIO_GCC_MMU_TCU_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00083014) +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008313c) +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0008313c) +#define HWIO_GCC_MMU_TCU_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0008313c) +#define HWIO_GCC_ANOC_TBU_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00090000) +#define HWIO_GCC_ANOC_TBU_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00090000) +#define HWIO_GCC_ANOC_TBU_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00090000) +#define HWIO_GCC_ANOC_TBU_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00090004) +#define HWIO_GCC_ANOC_TBU_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00090004) +#define HWIO_GCC_ANOC_TBU_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00090004) +#define HWIO_GCC_ANOC_TBU_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00090008) +#define HWIO_GCC_ANOC_TBU_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00090008) +#define HWIO_GCC_ANOC_TBU_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00090008) +#define HWIO_GCC_ANOC_TBU_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009000c) +#define HWIO_GCC_ANOC_TBU_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0009000c) +#define HWIO_GCC_ANOC_TBU_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0009000c) +#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00090010) +#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00090010) +#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00090010) +#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00090014) +#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00090014) +#define HWIO_GCC_AGGRE_NOC_AUDIO_TBU_SREGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00090014) +#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00090018) +#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00090018) +#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00090018) +#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009001c) +#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009001c) +#define HWIO_GCC_AGGRE_NOC_PCIE_TBU_SREGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009001c) +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00090020) +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00090020) +#define HWIO_GCC_AGGRE_NOC_TBU1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00090020) +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00090024) +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00090024) +#define HWIO_GCC_AGGRE_NOC_TBU1_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00090024) +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00090028) +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00090028) +#define HWIO_GCC_AGGRE_NOC_TBU2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00090028) +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009002c) +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0009002c) +#define HWIO_GCC_AGGRE_NOC_TBU2_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0009002c) +#define HWIO_GCC_MMNOC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00009000) +#define HWIO_GCC_MMNOC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009000) +#define HWIO_GCC_MMNOC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009000) +#define HWIO_GCC_MMNOC_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00009004) +#define HWIO_GCC_MMNOC_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009004) +#define HWIO_GCC_MMNOC_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009004) +#define HWIO_GCC_MMNOC_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009008) +#define HWIO_GCC_MMNOC_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009008) +#define HWIO_GCC_MMNOC_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009008) +#define HWIO_GCC_MMNOC_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000900c) +#define HWIO_GCC_MMNOC_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000900c) +#define HWIO_GCC_MMNOC_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000900c) +#define HWIO_GCC_MMNOC_TBU_SF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009010) +#define HWIO_GCC_MMNOC_TBU_SF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009010) +#define HWIO_GCC_MMNOC_TBU_SF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009010) +#define HWIO_GCC_MMNOC_TBU_SF_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009014) +#define HWIO_GCC_MMNOC_TBU_SF_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009014) +#define HWIO_GCC_MMNOC_TBU_SF_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009014) +#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009018) +#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009018) +#define HWIO_GCC_MMNOC_TBU_HF0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009018) +#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000901c) +#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000901c) +#define HWIO_GCC_MMNOC_TBU_HF0_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000901c) +#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009020) +#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009020) +#define HWIO_GCC_MMNOC_TBU_HF1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009020) +#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009024) +#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009024) +#define HWIO_GCC_MMNOC_TBU_HF1_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009024) +#define HWIO_GCC_MMNOC_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00009028) +#define HWIO_GCC_MMNOC_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009028) +#define HWIO_GCC_MMNOC_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009028) +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000902c) +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000902c) +#define HWIO_GCC_MMNOC_AHB_CFG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000902c) +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009030) +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00009030) +#define HWIO_GCC_NOC_MMNOC_DCD_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00009030) +#define HWIO_GCC_MMNOC_HF_QX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009034) +#define HWIO_GCC_MMNOC_HF_QX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009034) +#define HWIO_GCC_MMNOC_HF_QX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009034) +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000904c) +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000904c) +#define HWIO_GCC_RPMH_MMNOC_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000904c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009054) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009054) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009054) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009058) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009058) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009058) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000905c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000905c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000905c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009060) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009060) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009060) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009064) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009064) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009064) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009068) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009068) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009068) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000906c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000906c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000906c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009070) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009070) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009070) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009074) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009074) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009074) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009078) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009078) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009078) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000907c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000907c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000907c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009080) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009080) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009080) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009084) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009084) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009084) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009088) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009088) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009088) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000908c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000908c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000908c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009090) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009090) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_HF_QX_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009090) +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009038) +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00009038) +#define HWIO_GCC_MMNOC_HF_QX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00009038) +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000903c) +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000903c) +#define HWIO_GCC_MMNOC_HF_QX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000903c) +#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00009164) +#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009164) +#define HWIO_GCC_MMNOC_HF_QX_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009164) +#define HWIO_GCC_MMNOC_SF_QX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009168) +#define HWIO_GCC_MMNOC_SF_QX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00009168) +#define HWIO_GCC_MMNOC_SF_QX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00009168) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009188) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009188) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009188) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000918c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000918c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000918c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009190) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009190) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009190) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009194) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009194) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009194) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009198) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009198) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009198) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000919c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000919c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000919c) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000091a0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000091a0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000091a0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000091a4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000091a4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000091a4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000091a8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000091a8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000091a8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000091ac) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000091ac) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000091ac) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000091b0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000091b0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000091b0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000091b4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000091b4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000091b4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000091b8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000091b8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000091b8) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000091bc) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000091bc) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000091bc) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000091c0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000091c0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000091c0) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000091c4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000091c4) +#define HWIO_GCC_RPMH_MMNOC_MMNOC_SF_QX_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000091c4) +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000916c) +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000916c) +#define HWIO_GCC_MMNOC_SF_QX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000916c) +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009170) +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00009170) +#define HWIO_GCC_MMNOC_SF_QX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00009170) +#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00009298) +#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009298) +#define HWIO_GCC_MMNOC_SF_QX_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009298) +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000929c) +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000929c) +#define HWIO_GCC_MMNOC_QOSGEN_EXTREF_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000929c) +#define HWIO_GCC_MMSS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b000) +#define HWIO_GCC_MMSS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b000) +#define HWIO_GCC_MMSS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b000) +#define HWIO_GCC_VIDEO_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b004) +#define HWIO_GCC_VIDEO_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b004) +#define HWIO_GCC_VIDEO_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b004) +#define HWIO_GCC_CAMERA_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b008) +#define HWIO_GCC_CAMERA_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b008) +#define HWIO_GCC_CAMERA_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b008) +#define HWIO_GCC_DISP_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b00c) +#define HWIO_GCC_DISP_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b00c) +#define HWIO_GCC_DISP_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b00c) +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b010) +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b010) +#define HWIO_GCC_QMIP_VIDEO_CVP_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b010) +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0000b014) +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b014) +#define HWIO_GCC_QMIP_VIDEO_VCODEC_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b014) +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b018) +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b018) +#define HWIO_GCC_QMIP_CAMERA_NRT_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b018) +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b01c) +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000b01c) +#define HWIO_GCC_QMIP_CAMERA_RT_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000b01c) +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b020) +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b020) +#define HWIO_GCC_QMIP_DISP_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b020) +#define HWIO_GCC_VIDEO_AXI0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b024) +#define HWIO_GCC_VIDEO_AXI0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b024) +#define HWIO_GCC_VIDEO_AXI0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b024) +#define HWIO_GCC_VIDEO_AXI1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b028) +#define HWIO_GCC_VIDEO_AXI1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b028) +#define HWIO_GCC_VIDEO_AXI1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b028) +#define HWIO_GCC_VIDEO_AXIC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b02c) +#define HWIO_GCC_VIDEO_AXIC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b02c) +#define HWIO_GCC_VIDEO_AXIC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b02c) +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b030) +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b030) +#define HWIO_GCC_CAMERA_HF_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b030) +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b034) +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b034) +#define HWIO_GCC_CAMERA_SF_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b034) +#define HWIO_GCC_DISP_HF_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b038) +#define HWIO_GCC_DISP_HF_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b038) +#define HWIO_GCC_DISP_HF_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b038) +#define HWIO_GCC_DISP_SF_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b03c) +#define HWIO_GCC_DISP_SF_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b03c) +#define HWIO_GCC_DISP_SF_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b03c) +#define HWIO_GCC_VIDEO_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b040) +#define HWIO_GCC_VIDEO_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b040) +#define HWIO_GCC_VIDEO_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b040) +#define HWIO_GCC_CAMERA_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b044) +#define HWIO_GCC_CAMERA_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b044) +#define HWIO_GCC_CAMERA_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b044) +#define HWIO_GCC_DISP_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b048) +#define HWIO_GCC_DISP_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b048) +#define HWIO_GCC_DISP_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b048) +#define HWIO_GCC_MMSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000b04c) +#define HWIO_GCC_MMSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b04c) +#define HWIO_GCC_MMSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b04c) +#define HWIO_GCC_MMSS_QM_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b050) +#define HWIO_GCC_MMSS_QM_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b050) +#define HWIO_GCC_MMSS_QM_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b050) +#define HWIO_GCC_MMSS_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b054) +#define HWIO_GCC_MMSS_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b054) +#define HWIO_GCC_MMSS_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b054) +#define HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b058) +#define HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000b058) +#define HWIO_GCC_MMSS_QM_CORE_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000b058) +#define HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b05c) +#define HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000b05c) +#define HWIO_GCC_MMSS_QM_CORE_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000b05c) +#define HWIO_GCC_MMSS_QM_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000b070) +#define HWIO_GCC_MMSS_QM_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000b070) +#define HWIO_GCC_MMSS_QM_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000b070) +#define HWIO_GCC_PIMEM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000a000) +#define HWIO_GCC_PIMEM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000a000) +#define HWIO_GCC_PIMEM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000a000) +#define HWIO_GCC_PIMEM_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000a004) +#define HWIO_GCC_PIMEM_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000a004) +#define HWIO_GCC_PIMEM_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000a004) +#define HWIO_GCC_PIMEM_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000a008) +#define HWIO_GCC_PIMEM_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000a008) +#define HWIO_GCC_PIMEM_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000a008) +#define HWIO_GCC_QDSS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c000) +#define HWIO_GCC_QDSS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c000) +#define HWIO_GCC_QDSS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c000) +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c004) +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c004) +#define HWIO_GCC_QDSS_DAP_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c004) +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c008) +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c008) +#define HWIO_GCC_QDSS_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c008) +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c00c) +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c00c) +#define HWIO_GCC_QDSS_CENTER_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c00c) +#define HWIO_GCC_SOUTH_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c010) +#define HWIO_GCC_SOUTH_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c010) +#define HWIO_GCC_SOUTH_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c010) +#define HWIO_GCC_EAST_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c014) +#define HWIO_GCC_EAST_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c014) +#define HWIO_GCC_EAST_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c014) +#define HWIO_GCC_NORTH_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c018) +#define HWIO_GCC_NORTH_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c018) +#define HWIO_GCC_NORTH_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c018) +#define HWIO_GCC_QDSS_ETR_USB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c01c) +#define HWIO_GCC_QDSS_ETR_USB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c01c) +#define HWIO_GCC_QDSS_ETR_USB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c01c) +#define HWIO_GCC_QDSS_STM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c020) +#define HWIO_GCC_QDSS_STM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c020) +#define HWIO_GCC_QDSS_STM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c020) +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c024) +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000c024) +#define HWIO_GCC_QDSS_TRACECLKIN_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000c024) +#define HWIO_GCC_QDSS_TSCTR_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c028) +#define HWIO_GCC_QDSS_TSCTR_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c028) +#define HWIO_GCC_QDSS_TSCTR_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c028) +#define HWIO_GCC_QDSS_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c02c) +#define HWIO_GCC_QDSS_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c02c) +#define HWIO_GCC_QDSS_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c02c) +#define HWIO_GCC_QDSS_DAP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c030) +#define HWIO_GCC_QDSS_DAP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c030) +#define HWIO_GCC_QDSS_DAP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c030) +#define HWIO_GCC_APB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c034) +#define HWIO_GCC_APB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c034) +#define HWIO_GCC_APB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c034) +#define HWIO_GCC_QDSS_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000c038) +#define HWIO_GCC_QDSS_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c038) +#define HWIO_GCC_QDSS_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c038) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c058) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c058) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c058) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c05c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c05c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c05c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c060) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c060) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c060) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c064) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c064) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c064) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c068) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c068) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c068) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c06c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c06c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c06c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c070) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c070) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c070) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c074) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c074) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c074) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c078) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c078) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c078) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c07c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c07c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c07c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c080) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c080) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c080) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c084) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c084) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c084) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c088) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c088) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c088) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c08c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c08c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c08c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c090) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c090) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c090) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c094) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c094) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_A_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c094) +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c03c) +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c03c) +#define HWIO_GCC_QDSS_ATB_A_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c03c) +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c040) +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c040) +#define HWIO_GCC_QDSS_ATB_A_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c040) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c184) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c184) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c184) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c188) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c188) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c188) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c18c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c18c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c18c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c190) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c190) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c190) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c194) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c194) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c194) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c198) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c198) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c198) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c19c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c19c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c19c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c1a0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c1a0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c1a0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c1a4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c1a4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c1a4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c1a8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c1a8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c1a8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c1ac) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c1ac) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c1ac) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c1b0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c1b0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c1b0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c1b4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c1b4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c1b4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c1b8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c1b8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c1b8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c1bc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c1bc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c1bc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c1c0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c1c0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_B_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c1c0) +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c168) +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c168) +#define HWIO_GCC_QDSS_ATB_B_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c168) +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c16c) +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c16c) +#define HWIO_GCC_QDSS_ATB_B_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c16c) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2b0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2b0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2b0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2b4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2b4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2b4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2b8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2b8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2b8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2bc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2bc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2bc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2c0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2c0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2c0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2c4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2c4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2c4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2c8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2c8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2c8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2cc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2cc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2cc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2d0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2d0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2d0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2d4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2d4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2d4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2d8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2d8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2d8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2dc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2dc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2dc) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2e0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2e0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2e0) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2e4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2e4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2e4) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2e8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2e8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2e8) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c2ec) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c2ec) +#define HWIO_GCC_RPMH_SHUB_QDSS_ATB_C_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c2ec) +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c294) +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c294) +#define HWIO_GCC_QDSS_ATB_C_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c294) +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c298) +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c298) +#define HWIO_GCC_QDSS_ATB_C_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c298) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c3dc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c3dc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c3dc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c3e0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c3e0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c3e0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c3e4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c3e4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c3e4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c3e8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c3e8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c3e8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c3ec) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c3ec) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c3ec) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c3f0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c3f0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c3f0) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c3f4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c3f4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c3f4) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c3f8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c3f8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c3f8) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c3fc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c3fc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c3fc) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c400) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c400) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c400) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c404) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c404) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c404) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c408) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c408) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c408) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c40c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c40c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c40c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c410) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c410) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c410) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c414) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c414) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c414) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c418) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c418) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_STM_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c418) +#define HWIO_GCC_QDSS_STM_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c3c0) +#define HWIO_GCC_QDSS_STM_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c3c0) +#define HWIO_GCC_QDSS_STM_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c3c0) +#define HWIO_GCC_QDSS_STM_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c3c4) +#define HWIO_GCC_QDSS_STM_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c3c4) +#define HWIO_GCC_QDSS_STM_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c3c4) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c508) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c508) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c508) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c50c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c50c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c50c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c510) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c510) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c510) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c514) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c514) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c514) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c518) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c518) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c518) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c51c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c51c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c51c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c520) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c520) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c520) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c524) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c524) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c524) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c528) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c528) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c528) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c52c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c52c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c52c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c530) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c530) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c530) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c534) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c534) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c534) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c538) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c538) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c538) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c53c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c53c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c53c) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c540) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c540) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c540) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c544) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c544) +#define HWIO_GCC_RPMH_SHUB_QDSS_TRACECLKIN_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c544) +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c4ec) +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c4ec) +#define HWIO_GCC_QDSS_TRACECLKIN_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c4ec) +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c4f0) +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c4f0) +#define HWIO_GCC_QDSS_TRACECLKIN_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c4f0) +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c618) +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c618) +#define HWIO_GCC_QDSS_APB_TSCTR_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c618) +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c61c) +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c61c) +#define HWIO_GCC_QDSS_APB_TSCTR_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c61c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c64c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c64c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c64c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c650) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c650) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c650) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c654) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c654) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c654) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c658) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c658) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c658) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c65c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c65c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c65c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c660) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c660) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c660) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c664) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c664) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c664) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c668) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c668) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c668) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c66c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c66c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c66c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c670) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c670) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c670) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c674) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c674) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c674) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c678) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c678) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c678) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c67c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c67c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c67c) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c680) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c680) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c680) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c684) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c684) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c684) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000c688) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000c688) +#define HWIO_GCC_RPMH_SYS_NOC_QDSS_TRIG_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000c688) +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c630) +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c630) +#define HWIO_GCC_QDSS_TRIG_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c630) +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000c634) +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000c634) +#define HWIO_GCC_QDSS_TRIG_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000c634) +#define HWIO_GCC_USB30_PRIM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f000) +#define HWIO_GCC_USB30_PRIM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000f000) +#define HWIO_GCC_USB30_PRIM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000f000) +#define HWIO_GCC_USB30_PRIM_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f004) +#define HWIO_GCC_USB30_PRIM_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000f004) +#define HWIO_GCC_USB30_PRIM_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000f004) +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f008) +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000f008) +#define HWIO_GCC_USB30_PRIM_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000f008) +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f00c) +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000f00c) +#define HWIO_GCC_USB30_PRIM_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000f00c) +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f010) +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f010) +#define HWIO_GCC_USB30_PRIM_MASTER_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f010) +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f014) +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0000f014) +#define HWIO_GCC_USB30_PRIM_SLEEP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0000f014) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0000f018) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f018) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f018) +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0000f01c) +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f01c) +#define HWIO_GCC_USB30_PRIM_MASTER_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f01c) +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0000f020) +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f020) +#define HWIO_GCC_USB30_PRIM_MASTER_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f020) +#define HWIO_GCC_USB30_PRIM_MASTER_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f024) +#define HWIO_GCC_USB30_PRIM_MASTER_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000f024) +#define HWIO_GCC_USB30_PRIM_MASTER_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000f024) +#define HWIO_GCC_USB30_PRIM_MASTER_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f028) +#define HWIO_GCC_USB30_PRIM_MASTER_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000f028) +#define HWIO_GCC_USB30_PRIM_MASTER_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000f028) +#define HWIO_GCC_USB30_PRIM_MASTER_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f02c) +#define HWIO_GCC_USB30_PRIM_MASTER_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000f02c) +#define HWIO_GCC_USB30_PRIM_MASTER_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000f02c) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000f034) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f034) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f034) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000f038) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f038) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f038) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0000f04c) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f04c) +#define HWIO_GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f04c) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f050) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f050) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f050) +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0000f054) +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f054) +#define HWIO_GCC_USB3_PRIM_PHY_COM_AUX_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f054) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f058) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f058) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f058) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0000f060) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f060) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f060) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0000f064) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f064) +#define HWIO_GCC_USB3_PRIM_PHY_AUX_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f064) +#define HWIO_GCC_USB30_SEC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00010000) +#define HWIO_GCC_USB30_SEC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00010000) +#define HWIO_GCC_USB30_SEC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00010000) +#define HWIO_GCC_USB30_SEC_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00010004) +#define HWIO_GCC_USB30_SEC_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00010004) +#define HWIO_GCC_USB30_SEC_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00010004) +#define HWIO_GCC_USB30_SEC_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00010008) +#define HWIO_GCC_USB30_SEC_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00010008) +#define HWIO_GCC_USB30_SEC_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00010008) +#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001000c) +#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001000c) +#define HWIO_GCC_USB30_SEC_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001000c) +#define HWIO_GCC_USB30_SEC_MASTER_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00010010) +#define HWIO_GCC_USB30_SEC_MASTER_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00010010) +#define HWIO_GCC_USB30_SEC_MASTER_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00010010) +#define HWIO_GCC_USB30_SEC_SLEEP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00010014) +#define HWIO_GCC_USB30_SEC_SLEEP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00010014) +#define HWIO_GCC_USB30_SEC_SLEEP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00010014) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00010018) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010018) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010018) +#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0001001c) +#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001001c) +#define HWIO_GCC_USB30_SEC_MASTER_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001001c) +#define HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00010020) +#define HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010020) +#define HWIO_GCC_USB30_SEC_MASTER_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010020) +#define HWIO_GCC_USB30_SEC_MASTER_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00010024) +#define HWIO_GCC_USB30_SEC_MASTER_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00010024) +#define HWIO_GCC_USB30_SEC_MASTER_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00010024) +#define HWIO_GCC_USB30_SEC_MASTER_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00010028) +#define HWIO_GCC_USB30_SEC_MASTER_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00010028) +#define HWIO_GCC_USB30_SEC_MASTER_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00010028) +#define HWIO_GCC_USB30_SEC_MASTER_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001002c) +#define HWIO_GCC_USB30_SEC_MASTER_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001002c) +#define HWIO_GCC_USB30_SEC_MASTER_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001002c) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00010034) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010034) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010034) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00010038) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010038) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010038) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001004c) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001004c) +#define HWIO_GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001004c) +#define HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00010050) +#define HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00010050) +#define HWIO_GCC_USB3_SEC_PHY_AUX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00010050) +#define HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00010054) +#define HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010054) +#define HWIO_GCC_USB3_SEC_PHY_COM_AUX_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010054) +#define HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00010058) +#define HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010058) +#define HWIO_GCC_USB3_SEC_PHY_PIPE_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010058) +#define HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00010060) +#define HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010060) +#define HWIO_GCC_USB3_SEC_PHY_AUX_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010060) +#define HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00010064) +#define HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00010064) +#define HWIO_GCC_USB3_SEC_PHY_AUX_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00010064) +#define HWIO_GCC_USB3_PHY_PRIM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00050000) +#define HWIO_GCC_USB3_PHY_PRIM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00050000) +#define HWIO_GCC_USB3_PHY_PRIM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00050000) +#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00050004) +#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00050004) +#define HWIO_GCC_USB3PHY_PHY_PRIM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00050004) +#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00050008) +#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00050008) +#define HWIO_GCC_USB3_DP_PHY_PRIM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00050008) +#define HWIO_GCC_USB3_PHY_SEC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0005000c) +#define HWIO_GCC_USB3_PHY_SEC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0005000c) +#define HWIO_GCC_USB3_PHY_SEC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0005000c) +#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00050010) +#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00050010) +#define HWIO_GCC_USB3PHY_PHY_SEC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00050010) +#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00050014) +#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00050014) +#define HWIO_GCC_USB3_DP_PHY_SEC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00050014) +#define HWIO_GCC_QUSB2PHY_PRIM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00012000) +#define HWIO_GCC_QUSB2PHY_PRIM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00012000) +#define HWIO_GCC_QUSB2PHY_PRIM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00012000) +#define HWIO_GCC_QUSB2PHY_SEC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00012004) +#define HWIO_GCC_QUSB2PHY_SEC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00012004) +#define HWIO_GCC_QUSB2PHY_SEC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00012004) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006a000) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006a000) +#define HWIO_GCC_USB_PHY_CFG_AHB2PHY_BCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006a000) +#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006a004) +#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006a004) +#define HWIO_GCC_AHB2PHY_SOUTH_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006a004) +#define HWIO_GCC_SDCC2_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00014000) +#define HWIO_GCC_SDCC2_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00014000) +#define HWIO_GCC_SDCC2_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00014000) +#define HWIO_GCC_SDCC2_APPS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00014004) +#define HWIO_GCC_SDCC2_APPS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00014004) +#define HWIO_GCC_SDCC2_APPS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00014004) +#define HWIO_GCC_SDCC2_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00014008) +#define HWIO_GCC_SDCC2_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00014008) +#define HWIO_GCC_SDCC2_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00014008) +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001400c) +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001400c) +#define HWIO_GCC_SDCC2_APPS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001400c) +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00014010) +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00014010) +#define HWIO_GCC_SDCC2_APPS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00014010) +#define HWIO_GCC_SDCC2_APPS_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00014014) +#define HWIO_GCC_SDCC2_APPS_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00014014) +#define HWIO_GCC_SDCC2_APPS_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00014014) +#define HWIO_GCC_SDCC2_APPS_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00014018) +#define HWIO_GCC_SDCC2_APPS_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00014018) +#define HWIO_GCC_SDCC2_APPS_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00014018) +#define HWIO_GCC_SDCC2_APPS_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001401c) +#define HWIO_GCC_SDCC2_APPS_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001401c) +#define HWIO_GCC_SDCC2_APPS_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001401c) +#define HWIO_GCC_SDCC4_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00016000) +#define HWIO_GCC_SDCC4_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00016000) +#define HWIO_GCC_SDCC4_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00016000) +#define HWIO_GCC_SDCC4_APPS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00016004) +#define HWIO_GCC_SDCC4_APPS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00016004) +#define HWIO_GCC_SDCC4_APPS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00016004) +#define HWIO_GCC_SDCC4_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00016008) +#define HWIO_GCC_SDCC4_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00016008) +#define HWIO_GCC_SDCC4_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00016008) +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001600c) +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001600c) +#define HWIO_GCC_SDCC4_APPS_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001600c) +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00016010) +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00016010) +#define HWIO_GCC_SDCC4_APPS_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00016010) +#define HWIO_GCC_SDCC4_APPS_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00016014) +#define HWIO_GCC_SDCC4_APPS_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00016014) +#define HWIO_GCC_SDCC4_APPS_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00016014) +#define HWIO_GCC_SDCC4_APPS_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00016018) +#define HWIO_GCC_SDCC4_APPS_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00016018) +#define HWIO_GCC_SDCC4_APPS_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00016018) +#define HWIO_GCC_SDCC4_APPS_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0001601c) +#define HWIO_GCC_SDCC4_APPS_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001601c) +#define HWIO_GCC_SDCC4_APPS_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001601c) +#define HWIO_GCC_QUPV3_WRAPPER_0_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017000) +#define HWIO_GCC_QUPV3_WRAPPER_0_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017000) +#define HWIO_GCC_QUPV3_WRAPPER_0_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017000) +#define HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017004) +#define HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017004) +#define HWIO_GCC_QUPV3_WRAP_0_M_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017004) +#define HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017008) +#define HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017008) +#define HWIO_GCC_QUPV3_WRAP_0_S_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017008) +#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001700c) +#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001700c) +#define HWIO_GCC_QUPV3_WRAP0_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001700c) +#define HWIO_GCC_QUPV3_WRAP0_CORE_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017010) +#define HWIO_GCC_QUPV3_WRAP0_CORE_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017010) +#define HWIO_GCC_QUPV3_WRAP0_CORE_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017010) +#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017014) +#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017014) +#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017014) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001702c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001702c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001702c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001703c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001703c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001703c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017044) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017044) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017044) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017048) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017048) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017048) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001704c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001704c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001704c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017050) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017050) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017050) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017054) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017054) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017054) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017058) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017058) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017058) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001705c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001705c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001705c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017060) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017060) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017060) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017064) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017064) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017064) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017068) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017068) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017068) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001706c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001706c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001706c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017070) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017070) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP0_CORE_2X_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017070) +#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017018) +#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017018) +#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017018) +#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001701c) +#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001701c) +#define HWIO_GCC_QUPV3_WRAP0_CORE_2X_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001701c) +#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017144) +#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017144) +#define HWIO_GCC_QUPV3_WRAP0_S0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017144) +#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001715c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001715c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001715c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017164) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017164) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017164) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017168) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017168) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017168) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001716c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001716c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001716c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017170) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017170) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017170) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017174) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017174) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017174) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017178) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017178) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017178) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001717c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001717c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001717c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017180) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017180) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017180) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171a4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171a4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171a4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171a8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171a8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171a8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171ac) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171ac) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171ac) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171b0) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171b0) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171b0) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171b4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171b4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171b4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171b8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171b8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171b8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171bc) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171bc) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171bc) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171c0) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171c0) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171c0) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171e4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171e4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171e4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171e8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171e8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171e8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171ec) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171ec) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171ec) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171f0) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171f0) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171f0) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171f4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171f4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171f4) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171f8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171f8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171f8) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000171fc) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000171fc) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000171fc) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017200) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017200) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017200) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017224) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017224) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017224) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017228) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017228) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017228) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001722c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001722c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001722c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017230) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017230) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017230) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017234) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017234) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017234) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017238) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017238) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017238) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001723c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001723c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001723c) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017240) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017240) +#define HWIO_GCC_QUPV3_WRAP0_SE0_QUPV3_WRAP0_S0_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017240) +#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017148) +#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017148) +#define HWIO_GCC_QUPV3_WRAP0_S0_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017148) +#define HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001714c) +#define HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001714c) +#define HWIO_GCC_QUPV3_WRAP0_S0_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001714c) +#define HWIO_GCC_QUPV3_WRAP0_S0_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017150) +#define HWIO_GCC_QUPV3_WRAP0_S0_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017150) +#define HWIO_GCC_QUPV3_WRAP0_S0_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017150) +#define HWIO_GCC_QUPV3_WRAP0_S0_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017154) +#define HWIO_GCC_QUPV3_WRAP0_S0_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017154) +#define HWIO_GCC_QUPV3_WRAP0_S0_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017154) +#define HWIO_GCC_QUPV3_WRAP0_S0_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017158) +#define HWIO_GCC_QUPV3_WRAP0_S0_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017158) +#define HWIO_GCC_QUPV3_WRAP0_S0_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017158) +#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017274) +#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017274) +#define HWIO_GCC_QUPV3_WRAP0_S1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017274) +#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001728c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001728c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001728c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017294) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017294) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017294) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017298) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017298) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017298) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001729c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001729c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001729c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172a0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172a0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172a0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172a4) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172a4) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172a4) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172a8) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172a8) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172a8) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172ac) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172ac) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172ac) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172b0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172b0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172b0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172d4) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172d4) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172d4) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172d8) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172d8) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172d8) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172dc) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172dc) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172dc) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172e0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172e0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172e0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172e4) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172e4) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172e4) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172e8) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172e8) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172e8) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172ec) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172ec) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172ec) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000172f0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000172f0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000172f0) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017314) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017314) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017314) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017318) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017318) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017318) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001731c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001731c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001731c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017320) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017320) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017320) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017324) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017324) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017324) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017328) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017328) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017328) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001732c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001732c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001732c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017330) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017330) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017330) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017354) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017354) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017354) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017358) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017358) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017358) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001735c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001735c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001735c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017360) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017360) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017360) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017364) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017364) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017364) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017368) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017368) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017368) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001736c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001736c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001736c) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017370) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017370) +#define HWIO_GCC_QUPV3_WRAP0_SE1_QUPV3_WRAP0_S1_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017370) +#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017278) +#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017278) +#define HWIO_GCC_QUPV3_WRAP0_S1_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017278) +#define HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001727c) +#define HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001727c) +#define HWIO_GCC_QUPV3_WRAP0_S1_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001727c) +#define HWIO_GCC_QUPV3_WRAP0_S1_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017280) +#define HWIO_GCC_QUPV3_WRAP0_S1_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017280) +#define HWIO_GCC_QUPV3_WRAP0_S1_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017280) +#define HWIO_GCC_QUPV3_WRAP0_S1_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017284) +#define HWIO_GCC_QUPV3_WRAP0_S1_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017284) +#define HWIO_GCC_QUPV3_WRAP0_S1_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017284) +#define HWIO_GCC_QUPV3_WRAP0_S1_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017288) +#define HWIO_GCC_QUPV3_WRAP0_S1_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017288) +#define HWIO_GCC_QUPV3_WRAP0_S1_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017288) +#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000173a4) +#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000173a4) +#define HWIO_GCC_QUPV3_WRAP0_S2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000173a4) +#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000173bc) +#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173bc) +#define HWIO_GCC_QUPV3_WRAP0_SE2_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173bc) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000173c4) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173c4) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173c4) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000173c8) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173c8) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173c8) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000173cc) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173cc) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173cc) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000173d0) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173d0) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173d0) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000173d4) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173d4) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173d4) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000173d8) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173d8) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173d8) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000173dc) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173dc) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173dc) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000173e0) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173e0) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173e0) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017404) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017404) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017404) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017408) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017408) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017408) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001740c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001740c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001740c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017410) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017410) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017410) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017414) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017414) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017414) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017418) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017418) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017418) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001741c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001741c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001741c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017420) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017420) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017420) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017444) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017444) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017444) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017448) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017448) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017448) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001744c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001744c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001744c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017450) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017450) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017450) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017454) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017454) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017454) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017458) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017458) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017458) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001745c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001745c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001745c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017460) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017460) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017460) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017484) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017484) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017484) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017488) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017488) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017488) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001748c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001748c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001748c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017490) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017490) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017490) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017494) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017494) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017494) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017498) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017498) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017498) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001749c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001749c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001749c) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000174a0) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000174a0) +#define HWIO_GCC_QUPV3_WRAP0_SE2_QUPV3_WRAP0_S2_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000174a0) +#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000173a8) +#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173a8) +#define HWIO_GCC_QUPV3_WRAP0_S2_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173a8) +#define HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000173ac) +#define HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000173ac) +#define HWIO_GCC_QUPV3_WRAP0_S2_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000173ac) +#define HWIO_GCC_QUPV3_WRAP0_S2_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000173b0) +#define HWIO_GCC_QUPV3_WRAP0_S2_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000173b0) +#define HWIO_GCC_QUPV3_WRAP0_S2_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000173b0) +#define HWIO_GCC_QUPV3_WRAP0_S2_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000173b4) +#define HWIO_GCC_QUPV3_WRAP0_S2_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000173b4) +#define HWIO_GCC_QUPV3_WRAP0_S2_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000173b4) +#define HWIO_GCC_QUPV3_WRAP0_S2_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000173b8) +#define HWIO_GCC_QUPV3_WRAP0_S2_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000173b8) +#define HWIO_GCC_QUPV3_WRAP0_S2_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000173b8) +#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000174d4) +#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000174d4) +#define HWIO_GCC_QUPV3_WRAP0_S3_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000174d4) +#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000174ec) +#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000174ec) +#define HWIO_GCC_QUPV3_WRAP0_SE3_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000174ec) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000174f4) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000174f4) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000174f4) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000174f8) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000174f8) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000174f8) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000174fc) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000174fc) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000174fc) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017500) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017500) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017500) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017504) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017504) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017504) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017508) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017508) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017508) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001750c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001750c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001750c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017510) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017510) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017510) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017534) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017534) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017534) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017538) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017538) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017538) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001753c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001753c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001753c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017540) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017540) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017540) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017544) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017544) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017544) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017548) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017548) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017548) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001754c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001754c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001754c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017550) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017550) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017550) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017574) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017574) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017574) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017578) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017578) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017578) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001757c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001757c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001757c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017580) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017580) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017580) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017584) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017584) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017584) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017588) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017588) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017588) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001758c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001758c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001758c) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017590) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017590) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017590) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000175b4) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000175b4) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000175b4) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000175b8) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000175b8) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000175b8) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000175bc) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000175bc) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000175bc) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000175c0) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000175c0) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000175c0) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000175c4) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000175c4) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000175c4) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000175c8) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000175c8) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000175c8) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000175cc) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000175cc) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000175cc) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000175d0) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000175d0) +#define HWIO_GCC_QUPV3_WRAP0_SE3_QUPV3_WRAP0_S3_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000175d0) +#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000174d8) +#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000174d8) +#define HWIO_GCC_QUPV3_WRAP0_S3_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000174d8) +#define HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000174dc) +#define HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000174dc) +#define HWIO_GCC_QUPV3_WRAP0_S3_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000174dc) +#define HWIO_GCC_QUPV3_WRAP0_S3_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000174e0) +#define HWIO_GCC_QUPV3_WRAP0_S3_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000174e0) +#define HWIO_GCC_QUPV3_WRAP0_S3_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000174e0) +#define HWIO_GCC_QUPV3_WRAP0_S3_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000174e4) +#define HWIO_GCC_QUPV3_WRAP0_S3_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000174e4) +#define HWIO_GCC_QUPV3_WRAP0_S3_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000174e4) +#define HWIO_GCC_QUPV3_WRAP0_S3_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000174e8) +#define HWIO_GCC_QUPV3_WRAP0_S3_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000174e8) +#define HWIO_GCC_QUPV3_WRAP0_S3_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000174e8) +#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017604) +#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017604) +#define HWIO_GCC_QUPV3_WRAP0_S4_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017604) +#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001761c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001761c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001761c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017624) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017624) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017624) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017628) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017628) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017628) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001762c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001762c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001762c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017630) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017630) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017630) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017634) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017634) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017634) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017638) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017638) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017638) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001763c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001763c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001763c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017640) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017640) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017640) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017664) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017664) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017664) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017668) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017668) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017668) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001766c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001766c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001766c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017670) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017670) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017670) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017674) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017674) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017674) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017678) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017678) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017678) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001767c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001767c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001767c) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017680) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017680) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017680) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176a4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176a4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176a4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176a8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176a8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176a8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176ac) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176ac) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176ac) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176b0) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176b0) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176b0) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176b4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176b4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176b4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176b8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176b8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176b8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176bc) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176bc) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176bc) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176c0) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176c0) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176c0) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176e4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176e4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176e4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176e8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176e8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176e8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176ec) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176ec) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176ec) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176f0) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176f0) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176f0) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176f4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176f4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176f4) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176f8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176f8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176f8) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000176fc) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000176fc) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000176fc) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017700) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017700) +#define HWIO_GCC_QUPV3_WRAP0_SE4_QUPV3_WRAP0_S4_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017700) +#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017608) +#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017608) +#define HWIO_GCC_QUPV3_WRAP0_S4_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017608) +#define HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001760c) +#define HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001760c) +#define HWIO_GCC_QUPV3_WRAP0_S4_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001760c) +#define HWIO_GCC_QUPV3_WRAP0_S4_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017610) +#define HWIO_GCC_QUPV3_WRAP0_S4_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017610) +#define HWIO_GCC_QUPV3_WRAP0_S4_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017610) +#define HWIO_GCC_QUPV3_WRAP0_S4_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017614) +#define HWIO_GCC_QUPV3_WRAP0_S4_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017614) +#define HWIO_GCC_QUPV3_WRAP0_S4_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017614) +#define HWIO_GCC_QUPV3_WRAP0_S4_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017618) +#define HWIO_GCC_QUPV3_WRAP0_S4_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017618) +#define HWIO_GCC_QUPV3_WRAP0_S4_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017618) +#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017734) +#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017734) +#define HWIO_GCC_QUPV3_WRAP0_S5_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017734) +#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001774c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001774c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001774c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017754) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017754) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017754) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017758) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017758) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017758) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001775c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001775c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001775c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017760) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017760) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017760) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017764) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017764) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017764) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017768) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017768) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017768) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001776c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001776c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001776c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017770) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017770) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017770) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017794) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017794) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017794) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017798) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017798) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017798) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001779c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001779c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001779c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177a0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177a0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177a0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177a4) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177a4) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177a4) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177a8) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177a8) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177a8) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177ac) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177ac) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177ac) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177b0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177b0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177b0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177d4) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177d4) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177d4) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177d8) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177d8) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177d8) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177dc) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177dc) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177dc) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177e0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177e0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177e0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177e4) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177e4) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177e4) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177e8) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177e8) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177e8) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177ec) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177ec) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177ec) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000177f0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000177f0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000177f0) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017814) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017814) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017814) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017818) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017818) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017818) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001781c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001781c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001781c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017820) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017820) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017820) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017824) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017824) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017824) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017828) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017828) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017828) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001782c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001782c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001782c) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017830) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017830) +#define HWIO_GCC_QUPV3_WRAP0_SE5_QUPV3_WRAP0_S5_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017830) +#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017738) +#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017738) +#define HWIO_GCC_QUPV3_WRAP0_S5_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017738) +#define HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001773c) +#define HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001773c) +#define HWIO_GCC_QUPV3_WRAP0_S5_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001773c) +#define HWIO_GCC_QUPV3_WRAP0_S5_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017740) +#define HWIO_GCC_QUPV3_WRAP0_S5_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017740) +#define HWIO_GCC_QUPV3_WRAP0_S5_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017740) +#define HWIO_GCC_QUPV3_WRAP0_S5_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017744) +#define HWIO_GCC_QUPV3_WRAP0_S5_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017744) +#define HWIO_GCC_QUPV3_WRAP0_S5_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017744) +#define HWIO_GCC_QUPV3_WRAP0_S5_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017748) +#define HWIO_GCC_QUPV3_WRAP0_S5_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017748) +#define HWIO_GCC_QUPV3_WRAP0_S5_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017748) +#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017864) +#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017864) +#define HWIO_GCC_QUPV3_WRAP0_S6_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017864) +#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001787c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001787c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001787c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017884) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017884) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017884) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017888) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017888) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017888) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001788c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001788c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001788c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017890) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017890) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017890) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017894) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017894) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017894) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017898) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017898) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017898) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001789c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001789c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001789c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000178a0) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000178a0) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000178a0) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000178c4) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000178c4) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000178c4) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000178c8) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000178c8) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000178c8) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000178cc) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000178cc) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000178cc) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000178d0) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000178d0) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000178d0) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000178d4) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000178d4) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000178d4) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000178d8) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000178d8) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000178d8) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000178dc) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000178dc) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000178dc) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000178e0) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000178e0) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000178e0) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017904) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017904) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017904) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017908) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017908) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017908) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001790c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001790c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001790c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017910) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017910) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017910) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017914) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017914) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017914) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017918) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017918) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017918) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001791c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001791c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001791c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017920) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017920) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017920) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017944) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017944) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017944) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017948) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017948) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017948) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001794c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001794c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001794c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017950) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017950) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017950) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017954) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017954) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017954) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017958) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017958) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017958) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001795c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001795c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001795c) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017960) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017960) +#define HWIO_GCC_QUPV3_WRAP0_SE6_QUPV3_WRAP0_S6_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017960) +#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017868) +#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017868) +#define HWIO_GCC_QUPV3_WRAP0_S6_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017868) +#define HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001786c) +#define HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001786c) +#define HWIO_GCC_QUPV3_WRAP0_S6_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001786c) +#define HWIO_GCC_QUPV3_WRAP0_S6_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017870) +#define HWIO_GCC_QUPV3_WRAP0_S6_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017870) +#define HWIO_GCC_QUPV3_WRAP0_S6_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017870) +#define HWIO_GCC_QUPV3_WRAP0_S6_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017874) +#define HWIO_GCC_QUPV3_WRAP0_S6_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017874) +#define HWIO_GCC_QUPV3_WRAP0_S6_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017874) +#define HWIO_GCC_QUPV3_WRAP0_S6_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017878) +#define HWIO_GCC_QUPV3_WRAP0_S6_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017878) +#define HWIO_GCC_QUPV3_WRAP0_S6_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017878) +#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017994) +#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00017994) +#define HWIO_GCC_QUPV3_WRAP0_S7_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00017994) +#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000179ac) +#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179ac) +#define HWIO_GCC_QUPV3_WRAP0_SE7_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179ac) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179b4) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179b4) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179b4) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179b8) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179b8) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179b8) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179bc) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179bc) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179bc) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179c0) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179c0) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179c0) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179c4) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179c4) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179c4) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179c8) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179c8) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179c8) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179cc) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179cc) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179cc) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179d0) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179d0) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179d0) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179f4) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179f4) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179f4) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179f8) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179f8) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179f8) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000179fc) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000179fc) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000179fc) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a00) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a00) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a00) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a04) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a04) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a04) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a08) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a08) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a08) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a0c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a0c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a0c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a10) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a10) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a10) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a34) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a34) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a34) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a38) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a38) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a38) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a3c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a3c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a3c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a40) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a40) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a40) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a44) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a44) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a44) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a48) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a48) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a48) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a4c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a4c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a4c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a50) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a50) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a50) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a74) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a74) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a74) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a78) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a78) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a78) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a7c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a7c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a7c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a80) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a80) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a80) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a84) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a84) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a84) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a88) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a88) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a88) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a8c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a8c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a8c) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00017a90) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017a90) +#define HWIO_GCC_QUPV3_WRAP0_SE7_QUPV3_WRAP0_S7_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017a90) +#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00017998) +#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00017998) +#define HWIO_GCC_QUPV3_WRAP0_S7_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00017998) +#define HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001799c) +#define HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001799c) +#define HWIO_GCC_QUPV3_WRAP0_S7_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001799c) +#define HWIO_GCC_QUPV3_WRAP0_S7_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000179a0) +#define HWIO_GCC_QUPV3_WRAP0_S7_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000179a0) +#define HWIO_GCC_QUPV3_WRAP0_S7_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000179a0) +#define HWIO_GCC_QUPV3_WRAP0_S7_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000179a4) +#define HWIO_GCC_QUPV3_WRAP0_S7_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000179a4) +#define HWIO_GCC_QUPV3_WRAP0_S7_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000179a4) +#define HWIO_GCC_QUPV3_WRAP0_S7_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000179a8) +#define HWIO_GCC_QUPV3_WRAP0_S7_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000179a8) +#define HWIO_GCC_QUPV3_WRAP0_S7_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000179a8) +#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018000) +#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018000) +#define HWIO_GCC_QUPV3_WRAPPER_1_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018000) +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018004) +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018004) +#define HWIO_GCC_QUPV3_WRAP_1_M_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018004) +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018008) +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018008) +#define HWIO_GCC_QUPV3_WRAP_1_S_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018008) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001800c) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001800c) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001800c) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018010) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018010) +#define HWIO_GCC_QUPV3_WRAP1_CORE_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018010) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018014) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018014) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018014) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001803c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001803c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001803c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018044) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018044) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018044) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018048) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018048) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018048) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001804c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001804c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001804c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018050) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018050) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018050) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018054) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018054) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018054) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018058) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018058) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018058) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001805c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001805c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001805c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018060) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018060) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018060) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018064) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018064) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018064) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018068) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018068) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018068) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001806c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001806c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001806c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018070) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018070) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP1_CORE_2X_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018070) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018018) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018018) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018018) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001801c) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001801c) +#define HWIO_GCC_QUPV3_WRAP1_CORE_2X_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001801c) +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018144) +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018144) +#define HWIO_GCC_QUPV3_WRAP1_S0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018144) +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001815c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001815c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001815c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018164) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018164) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018164) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018168) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018168) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018168) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001816c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001816c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001816c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018170) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018170) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018170) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018174) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018174) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018174) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018178) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018178) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018178) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001817c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001817c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001817c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018180) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018180) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018180) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181a4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181a4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181a4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181a8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181a8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181a8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181ac) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181ac) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181ac) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181b0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181b0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181b0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181b4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181b4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181b4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181b8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181b8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181b8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181bc) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181bc) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181bc) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181c0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181c0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181c0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181e4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181e4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181e4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181e8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181e8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181e8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181ec) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181ec) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181ec) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181f0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181f0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181f0) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181f4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181f4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181f4) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181f8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181f8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181f8) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000181fc) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000181fc) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000181fc) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018200) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018200) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018200) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018224) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018224) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018224) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018228) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018228) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018228) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001822c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001822c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001822c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018230) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018230) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018230) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018234) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018234) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018234) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018238) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018238) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018238) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001823c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001823c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001823c) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018240) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018240) +#define HWIO_GCC_QUPV3_WRAP1_SE0_QUPV3_WRAP1_S0_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018240) +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018148) +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018148) +#define HWIO_GCC_QUPV3_WRAP1_S0_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018148) +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001814c) +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001814c) +#define HWIO_GCC_QUPV3_WRAP1_S0_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001814c) +#define HWIO_GCC_QUPV3_WRAP1_S0_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018150) +#define HWIO_GCC_QUPV3_WRAP1_S0_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018150) +#define HWIO_GCC_QUPV3_WRAP1_S0_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018150) +#define HWIO_GCC_QUPV3_WRAP1_S0_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018154) +#define HWIO_GCC_QUPV3_WRAP1_S0_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018154) +#define HWIO_GCC_QUPV3_WRAP1_S0_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018154) +#define HWIO_GCC_QUPV3_WRAP1_S0_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018158) +#define HWIO_GCC_QUPV3_WRAP1_S0_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018158) +#define HWIO_GCC_QUPV3_WRAP1_S0_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018158) +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018274) +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018274) +#define HWIO_GCC_QUPV3_WRAP1_S1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018274) +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001828c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001828c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001828c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018294) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018294) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018294) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018298) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018298) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018298) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001829c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001829c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001829c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182a0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182a0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182a0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182a4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182a4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182a4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182a8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182a8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182a8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182ac) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182ac) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182ac) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182b0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182b0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182b0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182d4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182d4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182d4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182d8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182d8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182d8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182dc) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182dc) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182dc) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182e0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182e0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182e0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182e4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182e4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182e4) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182e8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182e8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182e8) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182ec) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182ec) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182ec) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000182f0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000182f0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000182f0) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018314) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018314) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018314) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018318) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018318) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018318) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001831c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001831c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001831c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018320) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018320) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018320) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018324) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018324) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018324) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018328) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018328) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018328) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001832c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001832c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001832c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018330) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018330) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018330) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018354) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018354) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018354) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018358) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018358) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018358) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001835c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001835c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001835c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018360) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018360) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018360) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018364) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018364) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018364) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018368) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018368) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018368) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001836c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001836c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001836c) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018370) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018370) +#define HWIO_GCC_QUPV3_WRAP1_SE1_QUPV3_WRAP1_S1_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018370) +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018278) +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018278) +#define HWIO_GCC_QUPV3_WRAP1_S1_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018278) +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001827c) +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001827c) +#define HWIO_GCC_QUPV3_WRAP1_S1_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001827c) +#define HWIO_GCC_QUPV3_WRAP1_S1_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018280) +#define HWIO_GCC_QUPV3_WRAP1_S1_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018280) +#define HWIO_GCC_QUPV3_WRAP1_S1_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018280) +#define HWIO_GCC_QUPV3_WRAP1_S1_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018284) +#define HWIO_GCC_QUPV3_WRAP1_S1_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018284) +#define HWIO_GCC_QUPV3_WRAP1_S1_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018284) +#define HWIO_GCC_QUPV3_WRAP1_S1_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018288) +#define HWIO_GCC_QUPV3_WRAP1_S1_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018288) +#define HWIO_GCC_QUPV3_WRAP1_S1_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018288) +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000183a4) +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000183a4) +#define HWIO_GCC_QUPV3_WRAP1_S2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000183a4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000183bc) +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183bc) +#define HWIO_GCC_QUPV3_WRAP1_SE2_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183bc) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000183c4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183c4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183c4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000183c8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183c8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183c8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000183cc) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183cc) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183cc) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000183d0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183d0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183d0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000183d4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183d4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183d4) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000183d8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183d8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183d8) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000183dc) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183dc) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183dc) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000183e0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183e0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183e0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018404) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018404) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018404) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018408) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018408) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018408) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001840c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001840c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001840c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018410) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018410) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018410) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018414) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018414) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018414) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018418) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018418) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018418) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001841c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001841c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001841c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018420) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018420) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018420) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018444) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018444) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018444) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018448) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018448) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018448) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001844c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001844c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001844c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018450) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018450) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018450) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018454) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018454) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018454) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018458) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018458) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018458) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001845c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001845c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001845c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018460) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018460) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018460) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018484) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018484) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018484) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018488) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018488) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018488) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001848c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001848c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001848c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018490) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018490) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018490) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018494) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018494) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018494) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018498) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018498) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018498) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001849c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001849c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001849c) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000184a0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000184a0) +#define HWIO_GCC_QUPV3_WRAP1_SE2_QUPV3_WRAP1_S2_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000184a0) +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000183a8) +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183a8) +#define HWIO_GCC_QUPV3_WRAP1_S2_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183a8) +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000183ac) +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000183ac) +#define HWIO_GCC_QUPV3_WRAP1_S2_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000183ac) +#define HWIO_GCC_QUPV3_WRAP1_S2_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000183b0) +#define HWIO_GCC_QUPV3_WRAP1_S2_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000183b0) +#define HWIO_GCC_QUPV3_WRAP1_S2_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000183b0) +#define HWIO_GCC_QUPV3_WRAP1_S2_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000183b4) +#define HWIO_GCC_QUPV3_WRAP1_S2_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000183b4) +#define HWIO_GCC_QUPV3_WRAP1_S2_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000183b4) +#define HWIO_GCC_QUPV3_WRAP1_S2_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000183b8) +#define HWIO_GCC_QUPV3_WRAP1_S2_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000183b8) +#define HWIO_GCC_QUPV3_WRAP1_S2_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000183b8) +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000184d4) +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000184d4) +#define HWIO_GCC_QUPV3_WRAP1_S3_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000184d4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000184ec) +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000184ec) +#define HWIO_GCC_QUPV3_WRAP1_SE3_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000184ec) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000184f4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000184f4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000184f4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000184f8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000184f8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000184f8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000184fc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000184fc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000184fc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018500) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018500) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018500) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018504) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018504) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018504) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018508) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018508) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018508) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001850c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001850c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001850c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018510) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018510) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018510) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018534) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018534) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018534) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018538) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018538) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018538) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001853c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001853c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001853c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018540) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018540) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018540) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018544) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018544) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018544) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018548) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018548) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018548) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001854c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001854c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001854c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018550) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018550) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018550) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018574) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018574) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018574) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018578) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018578) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018578) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001857c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001857c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001857c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018580) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018580) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018580) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018584) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018584) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018584) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018588) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018588) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018588) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001858c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001858c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001858c) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018590) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018590) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018590) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000185b4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000185b4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000185b4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000185b8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000185b8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000185b8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000185bc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000185bc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000185bc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000185c0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000185c0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000185c0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000185c4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000185c4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000185c4) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000185c8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000185c8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000185c8) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000185cc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000185cc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000185cc) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000185d0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000185d0) +#define HWIO_GCC_QUPV3_WRAP1_SE3_QUPV3_WRAP1_S3_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000185d0) +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000184d8) +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000184d8) +#define HWIO_GCC_QUPV3_WRAP1_S3_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000184d8) +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000184dc) +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000184dc) +#define HWIO_GCC_QUPV3_WRAP1_S3_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000184dc) +#define HWIO_GCC_QUPV3_WRAP1_S3_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000184e0) +#define HWIO_GCC_QUPV3_WRAP1_S3_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000184e0) +#define HWIO_GCC_QUPV3_WRAP1_S3_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000184e0) +#define HWIO_GCC_QUPV3_WRAP1_S3_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000184e4) +#define HWIO_GCC_QUPV3_WRAP1_S3_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000184e4) +#define HWIO_GCC_QUPV3_WRAP1_S3_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000184e4) +#define HWIO_GCC_QUPV3_WRAP1_S3_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000184e8) +#define HWIO_GCC_QUPV3_WRAP1_S3_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000184e8) +#define HWIO_GCC_QUPV3_WRAP1_S3_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000184e8) +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018604) +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018604) +#define HWIO_GCC_QUPV3_WRAP1_S4_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018604) +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001861c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001861c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001861c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018624) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018624) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018624) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018628) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018628) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018628) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001862c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001862c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001862c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018630) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018630) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018630) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018634) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018634) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018634) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018638) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018638) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018638) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001863c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001863c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001863c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018640) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018640) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018640) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018664) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018664) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018664) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018668) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018668) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018668) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001866c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001866c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001866c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018670) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018670) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018670) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018674) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018674) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018674) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018678) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018678) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018678) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001867c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001867c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001867c) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018680) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018680) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018680) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186a4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186a4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186a4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186a8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186a8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186a8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186ac) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186ac) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186ac) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186b0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186b0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186b0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186b4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186b4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186b4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186b8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186b8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186b8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186bc) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186bc) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186bc) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186c0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186c0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186c0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186e4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186e4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186e4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186e8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186e8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186e8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186ec) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186ec) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186ec) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186f0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186f0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186f0) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186f4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186f4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186f4) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186f8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186f8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186f8) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000186fc) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000186fc) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000186fc) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018700) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018700) +#define HWIO_GCC_QUPV3_WRAP1_SE4_QUPV3_WRAP1_S4_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018700) +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018608) +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018608) +#define HWIO_GCC_QUPV3_WRAP1_S4_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018608) +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001860c) +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001860c) +#define HWIO_GCC_QUPV3_WRAP1_S4_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001860c) +#define HWIO_GCC_QUPV3_WRAP1_S4_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018610) +#define HWIO_GCC_QUPV3_WRAP1_S4_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018610) +#define HWIO_GCC_QUPV3_WRAP1_S4_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018610) +#define HWIO_GCC_QUPV3_WRAP1_S4_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018614) +#define HWIO_GCC_QUPV3_WRAP1_S4_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018614) +#define HWIO_GCC_QUPV3_WRAP1_S4_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018614) +#define HWIO_GCC_QUPV3_WRAP1_S4_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018618) +#define HWIO_GCC_QUPV3_WRAP1_S4_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018618) +#define HWIO_GCC_QUPV3_WRAP1_S4_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018618) +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018734) +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018734) +#define HWIO_GCC_QUPV3_WRAP1_S5_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018734) +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001874c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001874c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001874c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018754) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018754) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018754) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018758) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018758) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018758) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001875c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001875c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001875c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018760) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018760) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018760) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018764) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018764) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018764) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018768) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018768) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018768) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001876c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001876c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001876c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018770) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018770) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018770) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018794) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018794) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018794) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018798) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018798) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018798) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001879c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001879c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001879c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187a0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187a0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187a0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187a4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187a4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187a4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187a8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187a8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187a8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187ac) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187ac) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187ac) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187b0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187b0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187b0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187d4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187d4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187d4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187d8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187d8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187d8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187dc) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187dc) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187dc) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187e0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187e0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187e0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187e4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187e4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187e4) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187e8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187e8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187e8) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187ec) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187ec) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187ec) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000187f0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000187f0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000187f0) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018814) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018814) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018814) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018818) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018818) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018818) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001881c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001881c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001881c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018820) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018820) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018820) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018824) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018824) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018824) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018828) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018828) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018828) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001882c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001882c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001882c) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00018830) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018830) +#define HWIO_GCC_QUPV3_WRAP1_SE5_QUPV3_WRAP1_S5_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018830) +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018738) +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00018738) +#define HWIO_GCC_QUPV3_WRAP1_S5_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00018738) +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001873c) +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001873c) +#define HWIO_GCC_QUPV3_WRAP1_S5_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001873c) +#define HWIO_GCC_QUPV3_WRAP1_S5_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018740) +#define HWIO_GCC_QUPV3_WRAP1_S5_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018740) +#define HWIO_GCC_QUPV3_WRAP1_S5_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018740) +#define HWIO_GCC_QUPV3_WRAP1_S5_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018744) +#define HWIO_GCC_QUPV3_WRAP1_S5_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018744) +#define HWIO_GCC_QUPV3_WRAP1_S5_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018744) +#define HWIO_GCC_QUPV3_WRAP1_S5_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00018748) +#define HWIO_GCC_QUPV3_WRAP1_S5_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00018748) +#define HWIO_GCC_QUPV3_WRAP1_S5_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00018748) +#define HWIO_GCC_PDM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033000) +#define HWIO_GCC_PDM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00033000) +#define HWIO_GCC_PDM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00033000) +#define HWIO_GCC_PDM_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033004) +#define HWIO_GCC_PDM_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00033004) +#define HWIO_GCC_PDM_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00033004) +#define HWIO_GCC_PDM_XO4_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033008) +#define HWIO_GCC_PDM_XO4_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00033008) +#define HWIO_GCC_PDM_XO4_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00033008) +#define HWIO_GCC_PDM2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003300c) +#define HWIO_GCC_PDM2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003300c) +#define HWIO_GCC_PDM2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003300c) +#define HWIO_GCC_PDM2_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033010) +#define HWIO_GCC_PDM2_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00033010) +#define HWIO_GCC_PDM2_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00033010) +#define HWIO_GCC_PDM2_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033014) +#define HWIO_GCC_PDM2_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00033014) +#define HWIO_GCC_PDM2_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00033014) +#define HWIO_GCC_PDM_XO4_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00033028) +#define HWIO_GCC_PDM_XO4_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00033028) +#define HWIO_GCC_PDM_XO4_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00033028) +#define HWIO_GCC_PRNG_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034000) +#define HWIO_GCC_PRNG_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00034000) +#define HWIO_GCC_PRNG_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00034000) +#define HWIO_GCC_PRNG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00034004) +#define HWIO_GCC_PRNG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00034004) +#define HWIO_GCC_PRNG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00034004) +#define HWIO_GCC_TSIF_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00036000) +#define HWIO_GCC_TSIF_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00036000) +#define HWIO_GCC_TSIF_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00036000) +#define HWIO_GCC_TSIF_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00036004) +#define HWIO_GCC_TSIF_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00036004) +#define HWIO_GCC_TSIF_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00036004) +#define HWIO_GCC_TSIF_REF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00036008) +#define HWIO_GCC_TSIF_REF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00036008) +#define HWIO_GCC_TSIF_REF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00036008) +#define HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0003600c) +#define HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003600c) +#define HWIO_GCC_TSIF_INACTIVITY_TIMERS_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003600c) +#define HWIO_GCC_TSIF_REF_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00036010) +#define HWIO_GCC_TSIF_REF_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00036010) +#define HWIO_GCC_TSIF_REF_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00036010) +#define HWIO_GCC_TSIF_REF_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00036014) +#define HWIO_GCC_TSIF_REF_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00036014) +#define HWIO_GCC_TSIF_REF_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00036014) +#define HWIO_GCC_TSIF_REF_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00036018) +#define HWIO_GCC_TSIF_REF_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00036018) +#define HWIO_GCC_TSIF_REF_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00036018) +#define HWIO_GCC_TSIF_REF_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003601c) +#define HWIO_GCC_TSIF_REF_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003601c) +#define HWIO_GCC_TSIF_REF_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003601c) +#define HWIO_GCC_TSIF_REF_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00036020) +#define HWIO_GCC_TSIF_REF_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00036020) +#define HWIO_GCC_TSIF_REF_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00036020) +#define HWIO_GCC_TCSR_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037000) +#define HWIO_GCC_TCSR_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00037000) +#define HWIO_GCC_TCSR_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00037000) +#define HWIO_GCC_TCSR_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00037004) +#define HWIO_GCC_TCSR_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00037004) +#define HWIO_GCC_TCSR_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00037004) +#define HWIO_GCC_BOOT_ROM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00038000) +#define HWIO_GCC_BOOT_ROM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00038000) +#define HWIO_GCC_BOOT_ROM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00038000) +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00038004) +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00038004) +#define HWIO_GCC_BOOT_ROM_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00038004) +#define HWIO_GCC_TLMM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003a000) +#define HWIO_GCC_TLMM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003a000) +#define HWIO_GCC_TLMM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003a000) +#define HWIO_GCC_TLMM_NORTH_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003a004) +#define HWIO_GCC_TLMM_NORTH_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003a004) +#define HWIO_GCC_TLMM_NORTH_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003a004) +#define HWIO_GCC_TLMM_SOUTH_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003a008) +#define HWIO_GCC_TLMM_SOUTH_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003a008) +#define HWIO_GCC_TLMM_SOUTH_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003a008) +#define HWIO_GCC_TLMM_EAST_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003a00c) +#define HWIO_GCC_TLMM_EAST_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003a00c) +#define HWIO_GCC_TLMM_EAST_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003a00c) +#define HWIO_GCC_TLMM_WEST_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003a010) +#define HWIO_GCC_TLMM_WEST_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003a010) +#define HWIO_GCC_TLMM_WEST_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003a010) +#define HWIO_GCC_TLMM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003a014) +#define HWIO_GCC_TLMM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003a014) +#define HWIO_GCC_TLMM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003a014) +#define HWIO_GCC_AOSS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003c000) +#define HWIO_GCC_AOSS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003c000) +#define HWIO_GCC_AOSS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003c000) +#define HWIO_GCC_AOSS_CNOC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003c004) +#define HWIO_GCC_AOSS_CNOC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003c004) +#define HWIO_GCC_AOSS_CNOC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003c004) +#define HWIO_GCC_AOSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003c008) +#define HWIO_GCC_AOSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003c008) +#define HWIO_GCC_AOSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003c008) +#define HWIO_GCC_SEC_CTRL_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003d000) +#define HWIO_GCC_SEC_CTRL_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003d000) +#define HWIO_GCC_SEC_CTRL_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003d000) +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003d004) +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003d004) +#define HWIO_GCC_SEC_CTRL_ACC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003d004) +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003d008) +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003d008) +#define HWIO_GCC_SEC_CTRL_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003d008) +#define HWIO_GCC_SEC_CTRL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003d00c) +#define HWIO_GCC_SEC_CTRL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003d00c) +#define HWIO_GCC_SEC_CTRL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003d00c) +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003d010) +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003d010) +#define HWIO_GCC_SEC_CTRL_SENSE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003d010) +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0003d014) +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003d014) +#define HWIO_GCC_SEC_CTRL_BOOT_ROM_PATCH_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003d014) +#define HWIO_GCC_ACC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003d018) +#define HWIO_GCC_ACC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003d018) +#define HWIO_GCC_ACC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003d018) +#define HWIO_GCC_ACC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003d01c) +#define HWIO_GCC_ACC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003d01c) +#define HWIO_GCC_ACC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003d01c) +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003d030) +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003d030) +#define HWIO_GCC_SEC_CTRL_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003d030) +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003d034) +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003d034) +#define HWIO_GCC_SEC_CTRL_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003d034) +#define HWIO_GCC_SPDM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00040000) +#define HWIO_GCC_SPDM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00040000) +#define HWIO_GCC_SPDM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00040000) +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00040004) +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00040004) +#define HWIO_GCC_SPDM_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00040004) +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00040008) +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00040008) +#define HWIO_GCC_SPDM_MSTR_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00040008) +#define HWIO_GCC_SPDM_FF_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004000c) +#define HWIO_GCC_SPDM_FF_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004000c) +#define HWIO_GCC_SPDM_FF_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004000c) +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00040010) +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00040010) +#define HWIO_GCC_SPDM_MEMNOC_CY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00040010) +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00040014) +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00040014) +#define HWIO_GCC_SPDM_SNOC_CY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00040014) +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00040018) +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00040018) +#define HWIO_GCC_SPDM_DEBUG_CY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00040018) +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004001c) +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004001c) +#define HWIO_GCC_SPDM_PNOC_CY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004001c) +#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00040020) +#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00040020) +#define HWIO_GCC_SPDM_MEMNOC_CY_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00040020) +#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00040024) +#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00040024) +#define HWIO_GCC_SPDM_SNOC_CY_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00040024) +#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00040028) +#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00040028) +#define HWIO_GCC_SPDM_DEBUG_CY_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00040028) +#define HWIO_GCC_CE1_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00041000) +#define HWIO_GCC_CE1_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041000) +#define HWIO_GCC_CE1_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041000) +#define HWIO_GCC_CE1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00041004) +#define HWIO_GCC_CE1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041004) +#define HWIO_GCC_CE1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041004) +#define HWIO_GCC_CE1_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00041008) +#define HWIO_GCC_CE1_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00041008) +#define HWIO_GCC_CE1_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00041008) +#define HWIO_GCC_CE1_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004100c) +#define HWIO_GCC_CE1_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004100c) +#define HWIO_GCC_CE1_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004100c) +#define HWIO_GCC_RPMH_CE_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041024) +#define HWIO_GCC_RPMH_CE_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00041024) +#define HWIO_GCC_RPMH_CE_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00041024) +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004102c) +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004102c) +#define HWIO_GCC_RPMH_CE_CE1_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004102c) +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041030) +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041030) +#define HWIO_GCC_RPMH_CE_CE1_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041030) +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041034) +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041034) +#define HWIO_GCC_RPMH_CE_CE1_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041034) +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041038) +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041038) +#define HWIO_GCC_RPMH_CE_CE1_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041038) +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004103c) +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004103c) +#define HWIO_GCC_RPMH_CE_CE1_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004103c) +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041040) +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041040) +#define HWIO_GCC_RPMH_CE_CE1_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041040) +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041044) +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041044) +#define HWIO_GCC_RPMH_CE_CE1_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041044) +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041048) +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041048) +#define HWIO_GCC_RPMH_CE_CE1_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041048) +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004104c) +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004104c) +#define HWIO_GCC_RPMH_CE_CE1_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004104c) +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041050) +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041050) +#define HWIO_GCC_RPMH_CE_CE1_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041050) +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041054) +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041054) +#define HWIO_GCC_RPMH_CE_CE1_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041054) +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041058) +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041058) +#define HWIO_GCC_RPMH_CE_CE1_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041058) +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004105c) +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004105c) +#define HWIO_GCC_RPMH_CE_CE1_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004105c) +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041060) +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041060) +#define HWIO_GCC_RPMH_CE_CE1_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041060) +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041064) +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041064) +#define HWIO_GCC_RPMH_CE_CE1_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041064) +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00041068) +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00041068) +#define HWIO_GCC_RPMH_CE_CE1_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00041068) +#define HWIO_GCC_CE1_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00041010) +#define HWIO_GCC_CE1_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00041010) +#define HWIO_GCC_CE1_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00041010) +#define HWIO_GCC_CE1_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00041014) +#define HWIO_GCC_CE1_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00041014) +#define HWIO_GCC_CE1_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00041014) +#define HWIO_GCC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043000) +#define HWIO_GCC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043000) +#define HWIO_GCC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043000) +#define HWIO_GCC_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043004) +#define HWIO_GCC_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00043004) +#define HWIO_GCC_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00043004) +#define HWIO_GCC_XO_DIV4_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043008) +#define HWIO_GCC_XO_DIV4_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00043008) +#define HWIO_GCC_XO_DIV4_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00043008) +#define HWIO_GCC_SLEEP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004300c) +#define HWIO_GCC_SLEEP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004300c) +#define HWIO_GCC_SLEEP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004300c) +#define HWIO_GCC_XO_DIV4_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043010) +#define HWIO_GCC_XO_DIV4_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00043010) +#define HWIO_GCC_XO_DIV4_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00043010) +#define HWIO_GCC_SLEEP_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00043014) +#define HWIO_GCC_SLEEP_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00043014) +#define HWIO_GCC_SLEEP_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00043014) +#define HWIO_GCC_SLEEP_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00043018) +#define HWIO_GCC_SLEEP_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00043018) +#define HWIO_GCC_SLEEP_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00043018) +#define HWIO_GCC_XO_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004302c) +#define HWIO_GCC_XO_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004302c) +#define HWIO_GCC_XO_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004302c) +#define HWIO_GCC_XO_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00043030) +#define HWIO_GCC_XO_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00043030) +#define HWIO_GCC_XO_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00043030) +#define HWIO_GCC_DDRSS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00044000) +#define HWIO_GCC_DDRSS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044000) +#define HWIO_GCC_DDRSS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044000) +#define HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000092a0) +#define HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000092a0) +#define HWIO_GCC_DDRSS_MMNOC_SF_QX_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000092a0) +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000092a4) +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000092a4) +#define HWIO_GCC_DDRSS_MMNOC_HF_QX_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000092a4) +#define HWIO_GCC_DDRSS_TCU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00083140) +#define HWIO_GCC_DDRSS_TCU_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00083140) +#define HWIO_GCC_DDRSS_TCU_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00083140) +#define HWIO_GCC_DDRSS_TURING_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045158) +#define HWIO_GCC_DDRSS_TURING_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00045158) +#define HWIO_GCC_DDRSS_TURING_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00045158) +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008a154) +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0008a154) +#define HWIO_GCC_DDRSS_MSS_Q6_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0008a154) +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00071154) +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00071154) +#define HWIO_GCC_DDRSS_GPU_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00071154) +#define HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d04c) +#define HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008d04c) +#define HWIO_GCC_DDRSS_PCIE_SF_TBU_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008d04c) +#define HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044004) +#define HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044004) +#define HWIO_GCC_DDRSS_SYS_NOC_GC_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044004) +#define HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044008) +#define HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044008) +#define HWIO_GCC_DDRSS_SYS_NOC_SF_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044008) +#define HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004400c) +#define HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004400c) +#define HWIO_GCC_DDRSS_SYS_NOC_SLAVE_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004400c) +#define HWIO_GCC_DDRSS_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00044010) +#define HWIO_GCC_DDRSS_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044010) +#define HWIO_GCC_DDRSS_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044010) +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00044014) +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044014) +#define HWIO_GCC_DDRSS_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044014) +#define HWIO_GCC_DDRSS_SLEEP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00044018) +#define HWIO_GCC_DDRSS_SLEEP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044018) +#define HWIO_GCC_DDRSS_SLEEP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044018) +#define HWIO_GCC_MEMNOC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004401c) +#define HWIO_GCC_MEMNOC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004401c) +#define HWIO_GCC_MEMNOC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004401c) +#define HWIO_GCC_DDRSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00044020) +#define HWIO_GCC_DDRSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044020) +#define HWIO_GCC_DDRSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044020) +#define HWIO_GCC_DDRSS_DRE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00044024) +#define HWIO_GCC_DDRSS_DRE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044024) +#define HWIO_GCC_DDRSS_DRE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044024) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044044) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044044) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044044) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044048) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044048) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044048) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004404c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004404c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004404c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044050) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044050) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044050) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044054) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044054) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044054) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044058) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044058) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044058) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004405c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004405c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004405c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044060) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044060) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044060) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044064) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044064) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044064) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044068) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044068) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044068) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004406c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004406c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004406c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044070) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044070) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044070) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044074) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044074) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044074) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044078) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044078) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044078) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004407c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004407c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004407c) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044080) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044080) +#define HWIO_GCC_RPMH_SHUB_MEMNOC_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044080) +#define HWIO_GCC_MEMNOC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00044028) +#define HWIO_GCC_MEMNOC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044028) +#define HWIO_GCC_MEMNOC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044028) +#define HWIO_GCC_MEMNOC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004402c) +#define HWIO_GCC_MEMNOC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004402c) +#define HWIO_GCC_MEMNOC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004402c) +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00044168) +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044168) +#define HWIO_GCC_RPMH_SHRM_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044168) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044170) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044170) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044170) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044174) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044174) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044174) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044178) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044178) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044178) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0004417c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004417c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004417c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044180) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044180) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044180) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044184) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044184) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044184) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044188) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044188) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044188) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0004418c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004418c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004418c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044190) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044190) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044190) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044194) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044194) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044194) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00044198) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044198) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044198) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0004419c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004419c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004419c) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000441a0) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000441a0) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000441a0) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000441a4) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000441a4) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000441a4) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000441a8) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000441a8) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000441a8) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000441ac) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000441ac) +#define HWIO_GCC_RPMH_SHRM_SHRM_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000441ac) +#define HWIO_GCC_SHRM_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00044154) +#define HWIO_GCC_SHRM_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044154) +#define HWIO_GCC_SHRM_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044154) +#define HWIO_GCC_SHRM_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00044158) +#define HWIO_GCC_SHRM_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044158) +#define HWIO_GCC_SHRM_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044158) +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00044280) +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044280) +#define HWIO_GCC_SHRM_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044280) +#define HWIO_GCC_DCNOC_CFG_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00044284) +#define HWIO_GCC_DCNOC_CFG_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044284) +#define HWIO_GCC_DCNOC_CFG_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044284) +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00044288) +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00044288) +#define HWIO_GCC_MEMNOC_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00044288) +#define HWIO_GCC_MEMNOC_CDIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004428c) +#define HWIO_GCC_MEMNOC_CDIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004428c) +#define HWIO_GCC_MEMNOC_CDIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004428c) +#define HWIO_GCC_SHRM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00044290) +#define HWIO_GCC_SHRM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044290) +#define HWIO_GCC_SHRM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044290) +#define HWIO_GCC_DNOC_CFG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00044294) +#define HWIO_GCC_DNOC_CFG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044294) +#define HWIO_GCC_DNOC_CFG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044294) +#define HWIO_GCC_DDR_I_HCLK_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00044298) +#define HWIO_GCC_DDR_I_HCLK_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00044298) +#define HWIO_GCC_DDR_I_HCLK_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00044298) +#define HWIO_GCC_DDRMC_CH0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004429c) +#define HWIO_GCC_DDRMC_CH0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004429c) +#define HWIO_GCC_DDRMC_CH0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004429c) +#define HWIO_GCC_DDRMC_CH1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000442a0) +#define HWIO_GCC_DDRMC_CH1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x000442a0) +#define HWIO_GCC_DDRMC_CH1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x000442a0) +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000442b8) +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442b8) +#define HWIO_GCC_RPMH_DDRMC_CH0_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442b8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442c0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442c0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442c0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442c4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442c4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442c4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442c8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442c8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442c8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442cc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442cc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442cc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442d0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442d0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442d0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442d4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442d4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442d4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442d8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442d8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442d8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442dc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442dc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442dc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442e0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442e0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442e0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442e4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442e4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442e4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442e8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442e8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442e8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442ec) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442ec) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442ec) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442f0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442f0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442f0) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442f4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442f4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442f4) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442f8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442f8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442f8) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000442fc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442fc) +#define HWIO_GCC_RPMH_DDRMC_CH0_DDRMC_CH0_ROOT_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442fc) +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000442a4) +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442a4) +#define HWIO_GCC_DDRMC_CH0_ROOT_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442a4) +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000442a8) +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000442a8) +#define HWIO_GCC_DDRMC_CH0_ROOT_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000442a8) +#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000443d0) +#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000443d0) +#define HWIO_GCC_DDRMC_CH0_ROOT_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000443d0) +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000443e8) +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000443e8) +#define HWIO_GCC_RPMH_DDRMC_CH1_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000443e8) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000443f0) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000443f0) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000443f0) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000443f4) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000443f4) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000443f4) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000443f8) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000443f8) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000443f8) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000443fc) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000443fc) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000443fc) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044400) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044400) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044400) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044404) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044404) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044404) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044408) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044408) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044408) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004440c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004440c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004440c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044410) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044410) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044410) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044414) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044414) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044414) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044418) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044418) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044418) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004441c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004441c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004441c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044420) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044420) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044420) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044424) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044424) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044424) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044428) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044428) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044428) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004442c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004442c) +#define HWIO_GCC_RPMH_DDRMC_CH1_DDRMC_CH1_ROOT_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004442c) +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000443d4) +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000443d4) +#define HWIO_GCC_DDRMC_CH1_ROOT_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000443d4) +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000443d8) +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000443d8) +#define HWIO_GCC_DDRMC_CH1_ROOT_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000443d8) +#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044500) +#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044500) +#define HWIO_GCC_DDRMC_CH1_ROOT_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044500) +#define HWIO_GCC_LPASS_Q6_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00047000) +#define HWIO_GCC_LPASS_Q6_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00047000) +#define HWIO_GCC_LPASS_Q6_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00047000) +#define HWIO_GCC_LPASS_CORE_AXIM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00047004) +#define HWIO_GCC_LPASS_CORE_AXIM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00047004) +#define HWIO_GCC_LPASS_CORE_AXIM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00047004) +#define HWIO_GCC_LPASS_HW_AF_NOC_ANOC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00047008) +#define HWIO_GCC_LPASS_HW_AF_NOC_ANOC_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00047008) +#define HWIO_GCC_LPASS_HW_AF_NOC_ANOC_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00047008) +#define HWIO_GCC_LPASS_SWAY_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004700c) +#define HWIO_GCC_LPASS_SWAY_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004700c) +#define HWIO_GCC_LPASS_SWAY_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004700c) +#define HWIO_GCC_LPASS_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00047010) +#define HWIO_GCC_LPASS_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00047010) +#define HWIO_GCC_LPASS_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00047010) +#define HWIO_GCC_LPASS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00047014) +#define HWIO_GCC_LPASS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00047014) +#define HWIO_GCC_LPASS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00047014) +#define HWIO_GCC_TURING_TBU0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045000) +#define HWIO_GCC_TURING_TBU0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00045000) +#define HWIO_GCC_TURING_TBU0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00045000) +#define HWIO_GCC_TURING_TBU0_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045004) +#define HWIO_GCC_TURING_TBU0_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00045004) +#define HWIO_GCC_TURING_TBU0_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00045004) +#define HWIO_GCC_TURING_TBU1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045008) +#define HWIO_GCC_TURING_TBU1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00045008) +#define HWIO_GCC_TURING_TBU1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00045008) +#define HWIO_GCC_TURING_TBU1_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004500c) +#define HWIO_GCC_TURING_TBU1_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004500c) +#define HWIO_GCC_TURING_TBU1_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004500c) +#define HWIO_GCC_TURING_Q6_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045010) +#define HWIO_GCC_TURING_Q6_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00045010) +#define HWIO_GCC_TURING_Q6_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00045010) +#define HWIO_GCC_TURING_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045014) +#define HWIO_GCC_TURING_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00045014) +#define HWIO_GCC_TURING_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00045014) +#define HWIO_GCC_TURING_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045018) +#define HWIO_GCC_TURING_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00045018) +#define HWIO_GCC_TURING_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00045018) +#define HWIO_GCC_TURING_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004501c) +#define HWIO_GCC_TURING_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004501c) +#define HWIO_GCC_TURING_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004501c) +#define HWIO_GCC_TURING_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045020) +#define HWIO_GCC_TURING_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00045020) +#define HWIO_GCC_TURING_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00045020) +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045038) +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045038) +#define HWIO_GCC_RPMH_CDSP_NOC_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045038) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045040) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045040) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045040) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045044) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045044) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045044) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045048) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045048) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045048) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004504c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004504c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004504c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045050) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045050) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045050) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045054) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045054) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045054) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045058) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045058) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045058) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004505c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004505c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004505c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045060) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045060) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045060) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045064) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045064) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045064) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045068) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045068) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045068) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004506c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004506c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004506c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045070) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045070) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045070) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045074) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045074) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045074) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045078) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045078) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045078) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004507c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004507c) +#define HWIO_GCC_RPMH_CDSP_NOC_TURING_AXI_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004507c) +#define HWIO_GCC_TURING_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045024) +#define HWIO_GCC_TURING_AXI_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00045024) +#define HWIO_GCC_TURING_AXI_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00045024) +#define HWIO_GCC_TURING_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045028) +#define HWIO_GCC_TURING_AXI_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00045028) +#define HWIO_GCC_TURING_AXI_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00045028) +#define HWIO_GCC_TURING_AXI_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045150) +#define HWIO_GCC_TURING_AXI_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045150) +#define HWIO_GCC_TURING_AXI_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045150) +#define HWIO_GCC_TURING_AXI_CDIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00045154) +#define HWIO_GCC_TURING_AXI_CDIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00045154) +#define HWIO_GCC_TURING_AXI_CDIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00045154) +#define HWIO_GCC_CPUSS_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048000) +#define HWIO_GCC_CPUSS_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048000) +#define HWIO_GCC_CPUSS_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048000) +#define HWIO_GCC_CPUSS_GNOC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048004) +#define HWIO_GCC_CPUSS_GNOC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048004) +#define HWIO_GCC_CPUSS_GNOC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048004) +#define HWIO_GCC_CPUSS_RBCPR_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048008) +#define HWIO_GCC_CPUSS_RBCPR_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048008) +#define HWIO_GCC_CPUSS_RBCPR_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048008) +#define HWIO_GCC_CPUSS_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004800c) +#define HWIO_GCC_CPUSS_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004800c) +#define HWIO_GCC_CPUSS_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004800c) +#define HWIO_GCC_CPUSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00048010) +#define HWIO_GCC_CPUSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048010) +#define HWIO_GCC_CPUSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048010) +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048014) +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048014) +#define HWIO_GCC_CPUSS_AHB_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048014) +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048018) +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048018) +#define HWIO_GCC_CPUSS_AHB_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048018) +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004802c) +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004802c) +#define HWIO_GCC_CPUSS_AHB_POSTDIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004802c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004804c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004804c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004804c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048050) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048050) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048050) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048054) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048054) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048054) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048058) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048058) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048058) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004805c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004805c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004805c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048060) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048060) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048060) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048064) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048064) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048064) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048068) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048068) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048068) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004806c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004806c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004806c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048070) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048070) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048070) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048074) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048074) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048074) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048078) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048078) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048078) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004807c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004807c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004807c) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048080) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048080) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048080) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048084) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048084) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048084) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00048088) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00048088) +#define HWIO_GCC_RPMH_SHUB_CPUSS_AXI_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00048088) +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048030) +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048030) +#define HWIO_GCC_CPUSS_AXI_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048030) +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048034) +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048034) +#define HWIO_GCC_CPUSS_AXI_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048034) +#define HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004815c) +#define HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0004815c) +#define HWIO_GCC_CPUSS_RBCPR_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0004815c) +#define HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048160) +#define HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00048160) +#define HWIO_GCC_CPUSS_RBCPR_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00048160) +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048174) +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00048174) +#define HWIO_GCC_CPUSS_GPLL0_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00048174) +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048178) +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00048178) +#define HWIO_GCC_CPUSS_GPLL0_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00048178) +#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004818c) +#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004818c) +#define HWIO_GCC_CPUSS_AXI_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004818c) +#define HWIO_GCC_CPUSS_DVM_BUS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048190) +#define HWIO_GCC_CPUSS_DVM_BUS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048190) +#define HWIO_GCC_CPUSS_DVM_BUS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048190) +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048194) +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00048194) +#define HWIO_GCC_APSS_QDSS_TSCTR_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00048194) +#define HWIO_GCC_APSS_QDSS_APB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048198) +#define HWIO_GCC_APSS_QDSS_APB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048198) +#define HWIO_GCC_APSS_QDSS_APB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048198) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00049000) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00049000) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_BCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00049000) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00049004) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00049004) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00049004) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00049008) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00049008) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00049008) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004900c) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004900c) +#define HWIO_GCC_NOC_BUS_TIMEOUT_EXTREF_DIV512_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004900c) +#define HWIO_GCC_APB2JTAG_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004c000) +#define HWIO_GCC_APB2JTAG_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004c000) +#define HWIO_GCC_APB2JTAG_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004c000) +#define HWIO_GCC_RBCPR_CX_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004e000) +#define HWIO_GCC_RBCPR_CX_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004e000) +#define HWIO_GCC_RBCPR_CX_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004e000) +#define HWIO_GCC_RBCPR_CX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004e004) +#define HWIO_GCC_RBCPR_CX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004e004) +#define HWIO_GCC_RBCPR_CX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004e004) +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004e008) +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004e008) +#define HWIO_GCC_RBCPR_CX_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004e008) +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004e00c) +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004e00c) +#define HWIO_GCC_RBCPR_CX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004e00c) +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004e010) +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004e010) +#define HWIO_GCC_RBCPR_CX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004e010) +#define HWIO_GCC_RBCPR_MX_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004f000) +#define HWIO_GCC_RBCPR_MX_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004f000) +#define HWIO_GCC_RBCPR_MX_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004f000) +#define HWIO_GCC_RBCPR_MX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004f004) +#define HWIO_GCC_RBCPR_MX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004f004) +#define HWIO_GCC_RBCPR_MX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004f004) +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004f008) +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004f008) +#define HWIO_GCC_RBCPR_MX_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004f008) +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004f00c) +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004f00c) +#define HWIO_GCC_RBCPR_MX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004f00c) +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004f010) +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004f010) +#define HWIO_GCC_RBCPR_MX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004f010) +#define HWIO_GCC_DEBUG_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00062004) +#define HWIO_GCC_DEBUG_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00062004) +#define HWIO_GCC_DEBUG_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00062004) +#define HWIO_GCC_DEBUG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00062008) +#define HWIO_GCC_DEBUG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00062008) +#define HWIO_GCC_DEBUG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00062008) +#define HWIO_GCC_GP1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064000) +#define HWIO_GCC_GP1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064000) +#define HWIO_GCC_GP1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064000) +#define HWIO_GCC_GP1_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064004) +#define HWIO_GCC_GP1_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00064004) +#define HWIO_GCC_GP1_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00064004) +#define HWIO_GCC_GP1_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064008) +#define HWIO_GCC_GP1_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00064008) +#define HWIO_GCC_GP1_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00064008) +#define HWIO_GCC_GP1_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006400c) +#define HWIO_GCC_GP1_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006400c) +#define HWIO_GCC_GP1_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006400c) +#define HWIO_GCC_GP1_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064010) +#define HWIO_GCC_GP1_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064010) +#define HWIO_GCC_GP1_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064010) +#define HWIO_GCC_GP1_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00064014) +#define HWIO_GCC_GP1_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00064014) +#define HWIO_GCC_GP1_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00064014) +#define HWIO_GCC_GP2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00065000) +#define HWIO_GCC_GP2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00065000) +#define HWIO_GCC_GP2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00065000) +#define HWIO_GCC_GP2_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00065004) +#define HWIO_GCC_GP2_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00065004) +#define HWIO_GCC_GP2_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00065004) +#define HWIO_GCC_GP2_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00065008) +#define HWIO_GCC_GP2_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00065008) +#define HWIO_GCC_GP2_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00065008) +#define HWIO_GCC_GP2_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006500c) +#define HWIO_GCC_GP2_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006500c) +#define HWIO_GCC_GP2_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006500c) +#define HWIO_GCC_GP2_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00065010) +#define HWIO_GCC_GP2_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00065010) +#define HWIO_GCC_GP2_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00065010) +#define HWIO_GCC_GP2_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00065014) +#define HWIO_GCC_GP2_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00065014) +#define HWIO_GCC_GP2_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00065014) +#define HWIO_GCC_GP3_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066000) +#define HWIO_GCC_GP3_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066000) +#define HWIO_GCC_GP3_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066000) +#define HWIO_GCC_GP3_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066004) +#define HWIO_GCC_GP3_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00066004) +#define HWIO_GCC_GP3_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00066004) +#define HWIO_GCC_GP3_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066008) +#define HWIO_GCC_GP3_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00066008) +#define HWIO_GCC_GP3_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00066008) +#define HWIO_GCC_GP3_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006600c) +#define HWIO_GCC_GP3_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006600c) +#define HWIO_GCC_GP3_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006600c) +#define HWIO_GCC_GP3_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066010) +#define HWIO_GCC_GP3_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066010) +#define HWIO_GCC_GP3_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066010) +#define HWIO_GCC_GP3_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00066014) +#define HWIO_GCC_GP3_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00066014) +#define HWIO_GCC_GP3_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00066014) +#define HWIO_GCC_PCIE_0_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b000) +#define HWIO_GCC_PCIE_0_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b000) +#define HWIO_GCC_PCIE_0_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b000) +#define HWIO_GCC_PCIE_0_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b004) +#define HWIO_GCC_PCIE_0_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b004) +#define HWIO_GCC_PCIE_0_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b004) +#define HWIO_GCC_PCIE_0_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b008) +#define HWIO_GCC_PCIE_0_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b008) +#define HWIO_GCC_PCIE_0_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b008) +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b00c) +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b00c) +#define HWIO_GCC_PCIE_0_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b00c) +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b010) +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006b010) +#define HWIO_GCC_PCIE_0_SLV_Q2A_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006b010) +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b014) +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b014) +#define HWIO_GCC_PCIE_0_SLV_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b014) +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b018) +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0006b018) +#define HWIO_GCC_PCIE_0_MSTR_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0006b018) +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b01c) +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b01c) +#define HWIO_GCC_PCIE_0_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b01c) +#define HWIO_GCC_PCIE_0_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b020) +#define HWIO_GCC_PCIE_0_AUX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b020) +#define HWIO_GCC_PCIE_0_AUX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b020) +#define HWIO_GCC_PCIE_0_PIPE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b024) +#define HWIO_GCC_PCIE_0_PIPE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b024) +#define HWIO_GCC_PCIE_0_PIPE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b024) +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b02c) +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b02c) +#define HWIO_GCC_PCIE_0_AUX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b02c) +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b030) +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b030) +#define HWIO_GCC_PCIE_0_AUX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b030) +#define HWIO_GCC_PCIE_0_AUX_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b034) +#define HWIO_GCC_PCIE_0_AUX_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b034) +#define HWIO_GCC_PCIE_0_AUX_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b034) +#define HWIO_GCC_PCIE_0_AUX_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b038) +#define HWIO_GCC_PCIE_0_AUX_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b038) +#define HWIO_GCC_PCIE_0_AUX_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b038) +#define HWIO_GCC_PCIE_0_AUX_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006b03c) +#define HWIO_GCC_PCIE_0_AUX_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b03c) +#define HWIO_GCC_PCIE_0_AUX_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b03c) +#define HWIO_GCC_PCIE_1_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d000) +#define HWIO_GCC_PCIE_1_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d000) +#define HWIO_GCC_PCIE_1_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d000) +#define HWIO_GCC_PCIE_1_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d004) +#define HWIO_GCC_PCIE_1_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d004) +#define HWIO_GCC_PCIE_1_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d004) +#define HWIO_GCC_PCIE_1_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d008) +#define HWIO_GCC_PCIE_1_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d008) +#define HWIO_GCC_PCIE_1_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d008) +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d00c) +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d00c) +#define HWIO_GCC_PCIE_1_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d00c) +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d010) +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008d010) +#define HWIO_GCC_PCIE_1_SLV_Q2A_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008d010) +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d014) +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d014) +#define HWIO_GCC_PCIE_1_SLV_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d014) +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d018) +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0008d018) +#define HWIO_GCC_PCIE_1_MSTR_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0008d018) +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d01c) +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d01c) +#define HWIO_GCC_PCIE_1_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d01c) +#define HWIO_GCC_PCIE_1_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d020) +#define HWIO_GCC_PCIE_1_AUX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d020) +#define HWIO_GCC_PCIE_1_AUX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d020) +#define HWIO_GCC_PCIE_1_PIPE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d024) +#define HWIO_GCC_PCIE_1_PIPE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d024) +#define HWIO_GCC_PCIE_1_PIPE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d024) +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d02c) +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d02c) +#define HWIO_GCC_PCIE_1_AUX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d02c) +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d030) +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d030) +#define HWIO_GCC_PCIE_1_AUX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d030) +#define HWIO_GCC_PCIE_1_AUX_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d034) +#define HWIO_GCC_PCIE_1_AUX_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d034) +#define HWIO_GCC_PCIE_1_AUX_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d034) +#define HWIO_GCC_PCIE_1_AUX_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d038) +#define HWIO_GCC_PCIE_1_AUX_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d038) +#define HWIO_GCC_PCIE_1_AUX_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d038) +#define HWIO_GCC_PCIE_1_AUX_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008d03c) +#define HWIO_GCC_PCIE_1_AUX_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d03c) +#define HWIO_GCC_PCIE_1_AUX_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d03c) +#define HWIO_GCC_PCIE_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006f000) +#define HWIO_GCC_PCIE_PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006f000) +#define HWIO_GCC_PCIE_PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006f000) +#define HWIO_GCC_PCIE_PHY_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006f004) +#define HWIO_GCC_PCIE_PHY_AUX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006f004) +#define HWIO_GCC_PCIE_PHY_AUX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006f004) +#define HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006f014) +#define HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006f014) +#define HWIO_GCC_PCIE_PHY_REFGEN_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006f014) +#define HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006f018) +#define HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006f018) +#define HWIO_GCC_PCIE_PHY_REFGEN_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006f018) +#define HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006f02c) +#define HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0006f02c) +#define HWIO_GCC_PCIE0_PHY_REFGEN_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0006f02c) +#define HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006f030) +#define HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0006f030) +#define HWIO_GCC_PCIE1_PHY_REFGEN_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0006f030) +#define HWIO_GCC_UFS_CARD_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00075000) +#define HWIO_GCC_UFS_CARD_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00075000) +#define HWIO_GCC_UFS_CARD_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00075000) +#define HWIO_GCC_UFS_CARD_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00075004) +#define HWIO_GCC_UFS_CARD_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00075004) +#define HWIO_GCC_UFS_CARD_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00075004) +#define HWIO_GCC_UFS_CARD_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00075008) +#define HWIO_GCC_UFS_CARD_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00075008) +#define HWIO_GCC_UFS_CARD_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00075008) +#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007500c) +#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007500c) +#define HWIO_GCC_UFS_CARD_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007500c) +#define HWIO_GCC_UFS_CARD_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00075010) +#define HWIO_GCC_UFS_CARD_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00075010) +#define HWIO_GCC_UFS_CARD_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00075010) +#define HWIO_GCC_UFS_CARD_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00075014) +#define HWIO_GCC_UFS_CARD_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00075014) +#define HWIO_GCC_UFS_CARD_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00075014) +#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00075018) +#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075018) +#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075018) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0007501c) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007501c) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007501c) +#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00075020) +#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00075020) +#define HWIO_GCC_UFS_CARD_AXI_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00075020) +#define HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00075024) +#define HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00075024) +#define HWIO_GCC_UFS_CARD_AXI_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00075024) +#define HWIO_GCC_UFS_CARD_AXI_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00075028) +#define HWIO_GCC_UFS_CARD_AXI_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00075028) +#define HWIO_GCC_UFS_CARD_AXI_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00075028) +#define HWIO_GCC_UFS_CARD_AXI_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007502c) +#define HWIO_GCC_UFS_CARD_AXI_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007502c) +#define HWIO_GCC_UFS_CARD_AXI_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007502c) +#define HWIO_GCC_UFS_CARD_AXI_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00075030) +#define HWIO_GCC_UFS_CARD_AXI_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00075030) +#define HWIO_GCC_UFS_CARD_AXI_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00075030) +#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_DIV_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007503c) +#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_DIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007503c) +#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_DIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007503c) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_DIV_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007504c) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_DIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007504c) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_DIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007504c) +#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00075058) +#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075058) +#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075058) +#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007505c) +#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007505c) +#define HWIO_GCC_UFS_CARD_ICE_CORE_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007505c) +#define HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00075060) +#define HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075060) +#define HWIO_GCC_UFS_CARD_ICE_CORE_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075060) +#define HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00075064) +#define HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075064) +#define HWIO_GCC_UFS_CARD_ICE_CORE_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075064) +#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00075078) +#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075078) +#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075078) +#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007507c) +#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007507c) +#define HWIO_GCC_UFS_CARD_UNIPRO_CORE_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007507c) +#define HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00075090) +#define HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00075090) +#define HWIO_GCC_UFS_CARD_PHY_AUX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00075090) +#define HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00075094) +#define HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075094) +#define HWIO_GCC_UFS_CARD_PHY_AUX_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075094) +#define HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00075098) +#define HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075098) +#define HWIO_GCC_UFS_CARD_PHY_AUX_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075098) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000750ac) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000750ac) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000750ac) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_DIV_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000750b4) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_DIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000750b4) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_DIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000750b4) +#define HWIO_GCC_UFS_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077000) +#define HWIO_GCC_UFS_PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00077000) +#define HWIO_GCC_UFS_PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00077000) +#define HWIO_GCC_UFS_PHY_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077004) +#define HWIO_GCC_UFS_PHY_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00077004) +#define HWIO_GCC_UFS_PHY_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00077004) +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077008) +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00077008) +#define HWIO_GCC_UFS_PHY_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00077008) +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007700c) +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007700c) +#define HWIO_GCC_UFS_PHY_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007700c) +#define HWIO_GCC_UFS_PHY_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077010) +#define HWIO_GCC_UFS_PHY_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00077010) +#define HWIO_GCC_UFS_PHY_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00077010) +#define HWIO_GCC_UFS_PHY_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077014) +#define HWIO_GCC_UFS_PHY_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00077014) +#define HWIO_GCC_UFS_PHY_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00077014) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077018) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077018) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077018) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007701c) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007701c) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007701c) +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077020) +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00077020) +#define HWIO_GCC_UFS_PHY_AXI_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00077020) +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077024) +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00077024) +#define HWIO_GCC_UFS_PHY_AXI_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00077024) +#define HWIO_GCC_UFS_PHY_AXI_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077028) +#define HWIO_GCC_UFS_PHY_AXI_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00077028) +#define HWIO_GCC_UFS_PHY_AXI_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00077028) +#define HWIO_GCC_UFS_PHY_AXI_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007702c) +#define HWIO_GCC_UFS_PHY_AXI_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007702c) +#define HWIO_GCC_UFS_PHY_AXI_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007702c) +#define HWIO_GCC_UFS_PHY_AXI_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00077030) +#define HWIO_GCC_UFS_PHY_AXI_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00077030) +#define HWIO_GCC_UFS_PHY_AXI_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00077030) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007703c) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007703c) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_DIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007703c) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007704c) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007704c) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_DIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007704c) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077058) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077058) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077058) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007705c) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0007705c) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0007705c) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00077060) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077060) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077060) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00077064) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077064) +#define HWIO_GCC_UFS_PHY_ICE_CORE_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077064) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00077078) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077078) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077078) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007707c) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007707c) +#define HWIO_GCC_UFS_PHY_UNIPRO_CORE_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007707c) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077090) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00077090) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00077090) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077094) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077094) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077094) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077098) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077098) +#define HWIO_GCC_UFS_PHY_PHY_AUX_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077098) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000770ac) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000770ac) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000770ac) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000770b4) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000770b4) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_DIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000770b4) +#define HWIO_GCC_SSC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00063000) +#define HWIO_GCC_SSC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00063000) +#define HWIO_GCC_SSC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00063000) +#define HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00063004) +#define HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00063004) +#define HWIO_GCC_SSC_AGGRE_NOC_AHBM_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00063004) +#define HWIO_GCC_AGGRE_NOC_SSC_Q6_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00063008) +#define HWIO_GCC_AGGRE_NOC_SSC_Q6_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00063008) +#define HWIO_GCC_AGGRE_NOC_SSC_Q6_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00063008) +#define HWIO_GCC_SSC_CNOC_AHBS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006300c) +#define HWIO_GCC_SSC_CNOC_AHBS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006300c) +#define HWIO_GCC_SSC_CNOC_AHBS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006300c) +#define HWIO_GCC_SSC_CNOC_MPU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00063010) +#define HWIO_GCC_SSC_CNOC_MPU_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00063010) +#define HWIO_GCC_SSC_CNOC_MPU_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00063010) +#define HWIO_GCC_SSC_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00063014) +#define HWIO_GCC_SSC_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00063014) +#define HWIO_GCC_SSC_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00063014) +#define HWIO_GCC_VS_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a000) +#define HWIO_GCC_VS_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007a000) +#define HWIO_GCC_VS_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007a000) +#define HWIO_GCC_VDDCX_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a004) +#define HWIO_GCC_VDDCX_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a004) +#define HWIO_GCC_VDDCX_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a004) +#define HWIO_GCC_VDDMX_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a008) +#define HWIO_GCC_VDDMX_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a008) +#define HWIO_GCC_VDDMX_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a008) +#define HWIO_GCC_VDDA_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a00c) +#define HWIO_GCC_VDDA_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a00c) +#define HWIO_GCC_VDDA_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a00c) +#define HWIO_GCC_VS_CTRL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a010) +#define HWIO_GCC_VS_CTRL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a010) +#define HWIO_GCC_VS_CTRL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a010) +#define HWIO_GCC_VS_CTRL_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007a014) +#define HWIO_GCC_VS_CTRL_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a014) +#define HWIO_GCC_VS_CTRL_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a014) +#define HWIO_GCC_VSENSOR_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007a018) +#define HWIO_GCC_VSENSOR_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a018) +#define HWIO_GCC_VSENSOR_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a018) +#define HWIO_GCC_VSENSOR_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007a01c) +#define HWIO_GCC_VSENSOR_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a01c) +#define HWIO_GCC_VSENSOR_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a01c) +#define HWIO_GCC_VS_CTRL_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007a030) +#define HWIO_GCC_VS_CTRL_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a030) +#define HWIO_GCC_VS_CTRL_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a030) +#define HWIO_GCC_VS_CTRL_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007a034) +#define HWIO_GCC_VS_CTRL_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a034) +#define HWIO_GCC_VS_CTRL_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a034) +#define HWIO_GCC_MSS_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a048) +#define HWIO_GCC_MSS_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a048) +#define HWIO_GCC_MSS_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a048) +#define HWIO_GCC_GPU_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a04c) +#define HWIO_GCC_GPU_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a04c) +#define HWIO_GCC_GPU_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a04c) +#define HWIO_GCC_APC_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a050) +#define HWIO_GCC_APC_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a050) +#define HWIO_GCC_APC_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a050) +#define HWIO_GCC_VDDMMCX_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007a054) +#define HWIO_GCC_VDDMMCX_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a054) +#define HWIO_GCC_VDDMMCX_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a054) +#define HWIO_GCC_WCSS_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007a058) +#define HWIO_GCC_WCSS_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a058) +#define HWIO_GCC_WCSS_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a058) +#define HWIO_GCC_VDDMMMX_VS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007a05c) +#define HWIO_GCC_VDDMMMX_VS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007a05c) +#define HWIO_GCC_VDDMMMX_VS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007a05c) +#define HWIO_GCC_AGGRE_NOC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00082000) +#define HWIO_GCC_AGGRE_NOC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00082000) +#define HWIO_GCC_AGGRE_NOC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00082000) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082004) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082004) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AHB_CFG_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082004) +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00082008) +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00082008) +#define HWIO_GCC_AGGRE_NOC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00082008) +#define HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0008200c) +#define HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008200c) +#define HWIO_GCC_AGGRE_NOC_COMPUTE_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008200c) +#define HWIO_GCC_AGGRE_CNOC_PERIPH_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00082010) +#define HWIO_GCC_AGGRE_CNOC_PERIPH_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082010) +#define HWIO_GCC_AGGRE_CNOC_PERIPH_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082010) +#define HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00082014) +#define HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082014) +#define HWIO_GCC_AGGRE_NOC_SF_WEST_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082014) +#define HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082018) +#define HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082018) +#define HWIO_GCC_AGGRE_NOC_SF_NORTH_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082018) +#define HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008201c) +#define HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008201c) +#define HWIO_GCC_AGGRE_NOC_SF_CENTER_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008201c) +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082020) +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082020) +#define HWIO_GCC_AGGRE_NOC_QOSGEN_EXTREF_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082020) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00082024) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082024) +#define HWIO_GCC_AGGRE_NOC_CENTER_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082024) +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00082028) +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082028) +#define HWIO_GCC_AGGRE_NOC_WEST_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082028) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008202c) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008202c) +#define HWIO_GCC_AGGRE_NOC_SOUTH_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008202c) +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00082030) +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082030) +#define HWIO_GCC_AGGRE_NOC_EAST_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082030) +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00082034) +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082034) +#define HWIO_GCC_AGGRE_NOC_NORTH_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082034) +#define HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00082038) +#define HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082038) +#define HWIO_GCC_AGGRE_NOC_MONAQ_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082038) +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f07c) +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f07c) +#define HWIO_GCC_AGGRE_USB3_PRIM_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f07c) +#define HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001007c) +#define HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001007c) +#define HWIO_GCC_AGGRE_USB3_SEC_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001007c) +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000770c0) +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000770c0) +#define HWIO_GCC_AGGRE_UFS_PHY_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000770c0) +#define HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000750c0) +#define HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000750c0) +#define HWIO_GCC_AGGRE_UFS_CARD_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000750c0) +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00089158) +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00089158) +#define HWIO_GCC_AGGRE_NOC_IPA_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00089158) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004515c) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004515c) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_Q6_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004515c) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00045160) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00045160) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00045160) +#define HWIO_GCC_AGGRE_NOC_NPU_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004d148) +#define HWIO_GCC_AGGRE_NOC_NPU_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d148) +#define HWIO_GCC_AGGRE_NOC_NPU_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d148) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082058) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082058) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082058) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008205c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008205c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008205c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082060) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082060) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082060) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082064) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082064) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082064) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082068) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082068) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082068) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008206c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008206c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008206c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082070) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082070) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082070) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082074) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082074) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082074) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082078) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082078) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082078) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008207c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008207c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008207c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082080) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082080) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082080) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082084) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082084) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082084) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082088) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082088) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082088) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008208c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008208c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008208c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082090) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082090) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082090) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082094) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082094) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082094) +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008203c) +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008203c) +#define HWIO_GCC_AGGRE_NOC_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008203c) +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00082040) +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00082040) +#define HWIO_GCC_AGGRE_NOC_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00082040) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082184) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082184) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082184) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082188) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082188) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082188) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008218c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008218c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008218c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082190) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082190) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082190) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082194) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082194) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082194) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082198) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082198) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082198) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008219c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008219c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008219c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000821a0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000821a0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000821a0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000821a4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000821a4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000821a4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000821a8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000821a8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000821a8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000821ac) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000821ac) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000821ac) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000821b0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000821b0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000821b0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000821b4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000821b4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000821b4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000821b8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000821b8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000821b8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000821bc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000821bc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000821bc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000821c0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000821c0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_WEST_SF_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000821c0) +#define HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00082168) +#define HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082168) +#define HWIO_GCC_AGGRE_NOC_WEST_SF_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082168) +#define HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0008216c) +#define HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008216c) +#define HWIO_GCC_AGGRE_NOC_WEST_SF_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008216c) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822b0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822b0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822b0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822b4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822b4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822b4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822b8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822b8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822b8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822bc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822bc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822bc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822c0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822c0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822c0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822c4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822c4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822c4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822c8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822c8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822c8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822cc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822cc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822cc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822d0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822d0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822d0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822d4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822d4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822d4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822d8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822d8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822d8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822dc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822dc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822dc) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822e0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822e0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822e0) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822e4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822e4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822e4) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822e8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822e8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822e8) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000822ec) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000822ec) +#define HWIO_GCC_RPMH_SYS_NOC_AGGRE_NOC_NORTH_SF_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000822ec) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082294) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082294) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082294) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082298) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082298) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082298) +#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000823c0) +#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823c0) +#define HWIO_GCC_AGGRE_NOC_WEST_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823c0) +#define HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000823c4) +#define HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823c4) +#define HWIO_GCC_AGGRE_NOC_EAST_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823c4) +#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000823c8) +#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823c8) +#define HWIO_GCC_AGGRE_NOC_NORTH_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823c8) +#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000823cc) +#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823cc) +#define HWIO_GCC_AGGRE_NOC_SOUTH_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823cc) +#define HWIO_GCC_AGGRE_NOC_MONAQ_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000823d0) +#define HWIO_GCC_AGGRE_NOC_MONAQ_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823d0) +#define HWIO_GCC_AGGRE_NOC_MONAQ_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823d0) +#define HWIO_GCC_AGGRE_NOC_WEST_SF_DCD_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000823d4) +#define HWIO_GCC_AGGRE_NOC_WEST_SF_DCD_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823d4) +#define HWIO_GCC_AGGRE_NOC_WEST_SF_DCD_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823d4) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000823d8) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823d8) +#define HWIO_GCC_AGGRE_NOC_NORTH_SF_DCD_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823d8) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000823f8) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823f8) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823f8) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000823fc) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823fc) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823fc) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082400) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082400) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082400) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082404) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082404) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082404) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082408) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082408) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082408) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008240c) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008240c) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008240c) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082410) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082410) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082410) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082414) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082414) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082414) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082418) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082418) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082418) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008241c) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008241c) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008241c) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082420) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082420) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082420) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082424) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082424) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082424) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082428) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082428) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082428) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008242c) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008242c) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008242c) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082430) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082430) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082430) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082434) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082434) +#define HWIO_GCC_RPMH_CDSP_NOC_AGGRE_NOC_CDSP_NOC_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082434) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000823dc) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823dc) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823dc) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000823e0) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000823e0) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000823e0) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082508) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082508) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082508) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CDIV_CDIVR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008250c) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CDIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008250c) +#define HWIO_GCC_AGGRE_NOC_CDSP_NOC_CDIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008250c) +#define HWIO_GCC_DCC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084000) +#define HWIO_GCC_DCC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00084000) +#define HWIO_GCC_DCC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00084000) +#define HWIO_GCC_DCC_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00084004) +#define HWIO_GCC_DCC_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00084004) +#define HWIO_GCC_DCC_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00084004) +#define HWIO_GCC_IPA_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089000) +#define HWIO_GCC_IPA_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089000) +#define HWIO_GCC_IPA_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089000) +#define HWIO_GCC_IPA_BCR_RMSK 0x1 +#define HWIO_GCC_IPA_BCR_ATTR 0x3 +#define HWIO_GCC_IPA_BCR_IN in_dword_masked(HWIO_GCC_IPA_BCR_ADDR, \ + HWIO_GCC_IPA_BCR_RMSK) +#define HWIO_GCC_IPA_BCR_INM(m) in_dword_masked(HWIO_GCC_IPA_BCR_ADDR, m) +#define HWIO_GCC_IPA_BCR_OUT(v) out_dword(HWIO_GCC_IPA_BCR_ADDR, v) +#define HWIO_GCC_IPA_BCR_OUTM(m, v) out_dword_masked_ns( \ + HWIO_GCC_IPA_BCR_ADDR, \ + m, \ + v, \ + HWIO_GCC_IPA_BCR_IN) +#define HWIO_GCC_IPA_BCR_BLK_ARES_BMSK 0x1 +#define HWIO_GCC_IPA_BCR_BLK_ARES_SHFT 0x0 +#define HWIO_GCC_IPA_BCR_BLK_ARES_DISABLE_FVAL 0x0 +#define HWIO_GCC_IPA_BCR_BLK_ARES_ENABLE_FVAL 0x1 +#define HWIO_GCC_IPA_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089004) +#define HWIO_GCC_IPA_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00089004) +#define HWIO_GCC_IPA_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00089004) +#define HWIO_GCC_IPA_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089008) +#define HWIO_GCC_IPA_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00089008) +#define HWIO_GCC_IPA_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00089008) +#define HWIO_GCC_IPA_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008900c) +#define HWIO_GCC_IPA_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008900c) +#define HWIO_GCC_IPA_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008900c) +#define HWIO_GCC_IPA_2X_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089010) +#define HWIO_GCC_IPA_2X_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00089010) +#define HWIO_GCC_IPA_2X_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00089010) +#define HWIO_GCC_IPA_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089014) +#define HWIO_GCC_IPA_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089014) +#define HWIO_GCC_IPA_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089014) +#define HWIO_GCC_IPA_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089018) +#define HWIO_GCC_IPA_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00089018) +#define HWIO_GCC_IPA_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00089018) +#define HWIO_GCC_IPA_SLEEP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008901c) +#define HWIO_GCC_IPA_SLEEP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008901c) +#define HWIO_GCC_IPA_SLEEP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008901c) +#define HWIO_GCC_IPA_APB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089020) +#define HWIO_GCC_IPA_APB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00089020) +#define HWIO_GCC_IPA_APB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00089020) +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00089038) +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00089038) +#define HWIO_GCC_RPMH_IPA_CMD_DFSR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00089038) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00089040) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089040) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089040) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00089044) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089044) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089044) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00089048) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089048) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089048) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0008904c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008904c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008904c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00089050) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089050) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089050) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00089054) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089054) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089054) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00089058) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089058) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089058) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0008905c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008905c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008905c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00089060) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089060) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089060) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00089064) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089064) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089064) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00089068) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089068) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089068) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008906c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008906c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008906c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00089070) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089070) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089070) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00089074) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089074) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089074) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00089078) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00089078) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00089078) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008907c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008907c) +#define HWIO_GCC_RPMH_IPA_IPA_2X_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008907c) +#define HWIO_GCC_IPA_2X_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00089024) +#define HWIO_GCC_IPA_2X_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00089024) +#define HWIO_GCC_IPA_2X_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00089024) +#define HWIO_GCC_IPA_2X_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00089028) +#define HWIO_GCC_IPA_2X_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00089028) +#define HWIO_GCC_IPA_2X_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00089028) +#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00089150) +#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00089150) +#define HWIO_GCC_IPA_2X_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00089150) +#define HWIO_GCC_IPA_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00089154) +#define HWIO_GCC_IPA_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00089154) +#define HWIO_GCC_IPA_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00089154) +#define HWIO_GCC_MSS_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008a000) +#define HWIO_GCC_MSS_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008a000) +#define HWIO_GCC_MSS_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008a000) +#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008a004) +#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008a004) +#define HWIO_GCC_MSS_MFAB_AXIS_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008a004) +#define HWIO_GCC_MSS_AXIS2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008a008) +#define HWIO_GCC_MSS_AXIS2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008a008) +#define HWIO_GCC_MSS_AXIS2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008a008) +#define HWIO_GCC_MSS_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a00c) +#define HWIO_GCC_MSS_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008a00c) +#define HWIO_GCC_MSS_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008a00c) +#define HWIO_GCC_MSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a010) +#define HWIO_GCC_MSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008a010) +#define HWIO_GCC_MSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008a010) +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008a014) +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a014) +#define HWIO_GCC_MSS_PLL0_MAIN_DIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a014) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a034) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a034) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a034) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a038) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a038) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a038) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a03c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a03c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a03c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a040) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a040) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a040) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a044) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a044) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a044) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a048) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a048) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a048) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a04c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a04c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a04c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a050) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a050) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a050) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a054) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a054) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a054) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a058) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a058) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a058) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a05c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a05c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a05c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a060) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a060) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a060) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a064) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a064) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a064) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a068) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a068) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a068) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a06c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a06c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a06c) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a070) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a070) +#define HWIO_GCC_RPMH_SHUB_MSS_Q6_MEMNOC_AXI_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a070) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0008a018) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a018) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a018) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0008a01c) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a01c) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a01c) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008a144) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a144) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a144) +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008a14c) +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008a14c) +#define HWIO_GCC_MSS_SNOC_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008a14c) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008a150) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a150) +#define HWIO_GCC_MSS_Q6_MEMNOC_AXI_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a150) +#define HWIO_GCC_GLM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b000) +#define HWIO_GCC_GLM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b000) +#define HWIO_GCC_GLM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b000) +#define HWIO_GCC_GLM_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b004) +#define HWIO_GCC_GLM_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008b004) +#define HWIO_GCC_GLM_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008b004) +#define HWIO_GCC_GLM_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b008) +#define HWIO_GCC_GLM_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008b008) +#define HWIO_GCC_GLM_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008b008) +#define HWIO_GCC_GLM_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b00c) +#define HWIO_GCC_GLM_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008b00c) +#define HWIO_GCC_GLM_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008b00c) +#define HWIO_GCC_GLM_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b010) +#define HWIO_GCC_GLM_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008b010) +#define HWIO_GCC_GLM_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008b010) +#define HWIO_GCC_GLM_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008b014) +#define HWIO_GCC_GLM_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008b014) +#define HWIO_GCC_GLM_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008b014) +#define HWIO_GCC_QREFS_VBG_CAL_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00088000) +#define HWIO_GCC_QREFS_VBG_CAL_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00088000) +#define HWIO_GCC_QREFS_VBG_CAL_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00088000) +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00088004) +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00088004) +#define HWIO_GCC_QREFS_VBG_CAL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00088004) +#define HWIO_GCC_WCSS_AHB_S0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00011000) +#define HWIO_GCC_WCSS_AHB_S0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00011000) +#define HWIO_GCC_WCSS_AHB_S0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00011000) +#define HWIO_GCC_WCSS_AXI_M_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00011004) +#define HWIO_GCC_WCSS_AXI_M_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00011004) +#define HWIO_GCC_WCSS_AXI_M_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00011004) +#define HWIO_GCC_WCSS_ECAHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00011008) +#define HWIO_GCC_WCSS_ECAHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00011008) +#define HWIO_GCC_WCSS_ECAHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00011008) +#define HWIO_GCC_WCSS_SHDREG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001100c) +#define HWIO_GCC_WCSS_SHDREG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001100c) +#define HWIO_GCC_WCSS_SHDREG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001100c) +#define HWIO_GCC_WCSS_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00011010) +#define HWIO_GCC_WCSS_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00011010) +#define HWIO_GCC_WCSS_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00011010) +#define HWIO_GCC_WCSS_APB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00011014) +#define HWIO_GCC_WCSS_APB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00011014) +#define HWIO_GCC_WCSS_APB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00011014) +#define HWIO_GCC_GPU_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00071000) +#define HWIO_GCC_GPU_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071000) +#define HWIO_GCC_GPU_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071000) +#define HWIO_GCC_GPU_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00071004) +#define HWIO_GCC_GPU_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00071004) +#define HWIO_GCC_GPU_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00071004) +#define HWIO_GCC_GPU_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00071008) +#define HWIO_GCC_GPU_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00071008) +#define HWIO_GCC_GPU_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00071008) +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007100c) +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007100c) +#define HWIO_GCC_GPU_MEMNOC_GFX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007100c) +#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00071010) +#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00071010) +#define HWIO_GCC_GPU_MEMNOC_GFX_SREGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00071010) +#define HWIO_GCC_GPU_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00071014) +#define HWIO_GCC_GPU_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00071014) +#define HWIO_GCC_GPU_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00071014) +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00071018) +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00071018) +#define HWIO_GCC_GPU_SNOC_DVM_GFX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00071018) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071038) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071038) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071038) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007103c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007103c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007103c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071040) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071040) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071040) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071044) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071044) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071044) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071048) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071048) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071048) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007104c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007104c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007104c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071050) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071050) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071050) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071054) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071054) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071054) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071058) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071058) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071058) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007105c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007105c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007105c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071060) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071060) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071060) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071064) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071064) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071064) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071068) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071068) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071068) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007106c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007106c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007106c) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071070) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071070) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071070) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071074) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071074) +#define HWIO_GCC_RPMH_SHUB_GPU_MEMNOC_GFX_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071074) +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007101c) +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007101c) +#define HWIO_GCC_GPU_MEMNOC_GFX_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007101c) +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00071020) +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071020) +#define HWIO_GCC_GPU_MEMNOC_GFX_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071020) +#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00071148) +#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071148) +#define HWIO_GCC_GPU_MEMNOC_GFX_DCD_CDIV_DCDR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071148) +#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007114c) +#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007114c) +#define HWIO_GCC_GPU_PLL0_MAIN_DIV_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007114c) +#define HWIO_GCC_GPU_TRIG_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00071150) +#define HWIO_GCC_GPU_TRIG_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00071150) +#define HWIO_GCC_GPU_TRIG_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00071150) +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00072000) +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00072000) +#define HWIO_GCC_SP_SNOC_ANOC_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00072000) +#define HWIO_GCC_SP_SCR_NIU_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00072004) +#define HWIO_GCC_SP_SCR_NIU_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00072004) +#define HWIO_GCC_SP_SCR_NIU_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00072004) +#define HWIO_GCC_SP_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00072008) +#define HWIO_GCC_SP_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00072008) +#define HWIO_GCC_SP_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00072008) +#define HWIO_GCC_SP_SCSR_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007200c) +#define HWIO_GCC_SP_SCSR_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007200c) +#define HWIO_GCC_SP_SCSR_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007200c) +#define HWIO_GCC_SP_SEC_CTRL_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00072010) +#define HWIO_GCC_SP_SEC_CTRL_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00072010) +#define HWIO_GCC_SP_SEC_CTRL_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00072010) +#define HWIO_GCC_SP_GPKT_XO_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00072014) +#define HWIO_GCC_SP_GPKT_XO_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00072014) +#define HWIO_GCC_SP_GPKT_XO_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00072014) +#define HWIO_GCC_SP_RSSC_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072018) +#define HWIO_GCC_SP_RSSC_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00072018) +#define HWIO_GCC_SP_RSSC_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00072018) +#define HWIO_GCC_SP_ARI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007201c) +#define HWIO_GCC_SP_ARI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007201c) +#define HWIO_GCC_SP_ARI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007201c) +#define HWIO_GCC_SP_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072020) +#define HWIO_GCC_SP_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00072020) +#define HWIO_GCC_SP_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00072020) +#define HWIO_GCC_SP_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00072024) +#define HWIO_GCC_SP_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00072024) +#define HWIO_GCC_SP_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00072024) +#define HWIO_GCC_NAV_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00015000) +#define HWIO_GCC_NAV_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00015000) +#define HWIO_GCC_NAV_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00015000) +#define HWIO_GCC_NAV_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00015004) +#define HWIO_GCC_NAV_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00015004) +#define HWIO_GCC_NAV_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00015004) +#define HWIO_GCC_AHB2PHY_SOUTH_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00007000) +#define HWIO_GCC_AHB2PHY_SOUTH_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00007000) +#define HWIO_GCC_AHB2PHY_SOUTH_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00007000) +#define HWIO_GCC_AHB2PHY_NORTH_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00007004) +#define HWIO_GCC_AHB2PHY_NORTH_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00007004) +#define HWIO_GCC_AHB2PHY_NORTH_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00007004) +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00022000) +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00022000) +#define HWIO_GCC_CM_PHY_REFGEN1_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00022000) +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00022004) +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00022004) +#define HWIO_GCC_CM_PHY_REFGEN1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00022004) +#define HWIO_GCC_CM_PHY_REFGEN2_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00024000) +#define HWIO_GCC_CM_PHY_REFGEN2_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00024000) +#define HWIO_GCC_CM_PHY_REFGEN2_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00024000) +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00024004) +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00024004) +#define HWIO_GCC_CM_PHY_REFGEN2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00024004) +#define HWIO_GCC_QSPI_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00024008) +#define HWIO_GCC_QSPI_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00024008) +#define HWIO_GCC_QSPI_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00024008) +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0004b000) +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004b000) +#define HWIO_GCC_QSPI_CNOC_PERIPH_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004b000) +#define HWIO_GCC_QSPI_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004b004) +#define HWIO_GCC_QSPI_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004b004) +#define HWIO_GCC_QSPI_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004b004) +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004b008) +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004b008) +#define HWIO_GCC_QSPI_CORE_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004b008) +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004b00c) +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004b00c) +#define HWIO_GCC_QSPI_CORE_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004b00c) +#define HWIO_GCC_NPU_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004d000) +#define HWIO_GCC_NPU_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d000) +#define HWIO_GCC_NPU_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d000) +#define HWIO_GCC_NPU_CFG_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004d004) +#define HWIO_GCC_NPU_CFG_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004d004) +#define HWIO_GCC_NPU_CFG_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004d004) +#define HWIO_GCC_NPU_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004d008) +#define HWIO_GCC_NPU_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004d008) +#define HWIO_GCC_NPU_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004d008) +#define HWIO_GCC_NPU_TRIG_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004d00c) +#define HWIO_GCC_NPU_TRIG_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004d00c) +#define HWIO_GCC_NPU_TRIG_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004d00c) +#define HWIO_GCC_NPU_AT_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004d010) +#define HWIO_GCC_NPU_AT_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004d010) +#define HWIO_GCC_NPU_AT_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004d010) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d030) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d030) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d030) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d034) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d034) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d034) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d038) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d038) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d038) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d03c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d03c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d03c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d040) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d040) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d040) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d044) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d044) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d044) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d048) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d048) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d048) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d04c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d04c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d04c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d050) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d050) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d050) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d054) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d054) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d054) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d058) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d058) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d058) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d05c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d05c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d05c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d060) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d060) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d060) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d064) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d064) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d064) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d068) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d068) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d068) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0004d06c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d06c) +#define HWIO_GCC_RPMH_CDSP_NOC_NPU_AXI_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d06c) +#define HWIO_GCC_NPU_AXI_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004d014) +#define HWIO_GCC_NPU_AXI_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004d014) +#define HWIO_GCC_NPU_AXI_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004d014) +#define HWIO_GCC_NPU_AXI_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004d018) +#define HWIO_GCC_NPU_AXI_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004d018) +#define HWIO_GCC_NPU_AXI_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004d018) +#define HWIO_GCC_NPU_AXI_DCD_CDIV_DCDR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004d140) +#define HWIO_GCC_NPU_AXI_DCD_CDIV_DCDR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0004d140) +#define HWIO_GCC_NPU_AXI_DCD_CDIV_DCDR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0004d140) +#define HWIO_GCC_PLL0_MAIN_DIV_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0004d144) +#define HWIO_GCC_PLL0_MAIN_DIV_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0004d144) +#define HWIO_GCC_PLL0_MAIN_DIV_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0004d144) +#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e000) +#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e000) +#define HWIO_GCC_QUPV3_WRAPPER_2_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e000) +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e004) +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e004) +#define HWIO_GCC_QUPV3_WRAP_2_M_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e004) +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e008) +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e008) +#define HWIO_GCC_QUPV3_WRAP_2_S_AHB_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e008) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e00c) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0001e00c) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0001e00c) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e010) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CDIVR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e010) +#define HWIO_GCC_QUPV3_WRAP2_CORE_CDIVR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e010) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e014) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e014) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CBCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e014) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e03c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e03c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e03c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e044) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e044) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e044) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e048) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e048) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e048) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e04c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e04c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e04c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e050) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e050) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e050) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e054) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e054) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF8_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e054) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e058) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e058) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF9_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e058) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e05c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e05c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF10_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e05c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e060) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e060) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF11_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e060) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e064) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e064) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF12_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e064) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e068) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e068) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF13_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e068) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e06c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e06c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF14_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e06c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e070) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e070) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_QUPV3_WRAP2_CORE_2X_PERF15_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e070) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e018) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e018) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e018) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e01c) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e01c) +#define HWIO_GCC_QUPV3_WRAP2_CORE_2X_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e01c) +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e144) +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e144) +#define HWIO_GCC_QUPV3_WRAP2_S0_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e144) +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e15c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e15c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e15c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e164) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e164) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e164) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e168) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e168) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e168) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e16c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e16c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e16c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e170) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e170) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e170) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e174) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e174) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e174) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e178) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e178) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e178) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e17c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e17c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e17c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e180) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e180) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e180) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1a4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1a4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1a4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1a8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1a8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1a8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1ac) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1ac) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1ac) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1b0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1b0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1b0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1b4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1b4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1b4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1b8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1b8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1b8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1bc) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1bc) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1bc) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1c0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1c0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1c0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1e4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1e4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1e4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1e8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1e8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1e8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1ec) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1ec) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1ec) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1f0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1f0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1f0) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1f4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1f4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1f4) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1f8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1f8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1f8) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e1fc) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e1fc) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e1fc) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e200) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e200) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e200) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e224) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e224) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e224) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e228) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e228) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e228) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e22c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e22c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e22c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e230) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e230) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e230) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e234) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e234) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e234) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e238) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e238) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e238) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e23c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e23c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e23c) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e240) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e240) +#define HWIO_GCC_QUPV3_WRAP2_SE0_QUPV3_WRAP2_S0_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e240) +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e148) +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e148) +#define HWIO_GCC_QUPV3_WRAP2_S0_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e148) +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e14c) +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e14c) +#define HWIO_GCC_QUPV3_WRAP2_S0_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e14c) +#define HWIO_GCC_QUPV3_WRAP2_S0_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e150) +#define HWIO_GCC_QUPV3_WRAP2_S0_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e150) +#define HWIO_GCC_QUPV3_WRAP2_S0_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e150) +#define HWIO_GCC_QUPV3_WRAP2_S0_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e154) +#define HWIO_GCC_QUPV3_WRAP2_S0_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e154) +#define HWIO_GCC_QUPV3_WRAP2_S0_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e154) +#define HWIO_GCC_QUPV3_WRAP2_S0_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e158) +#define HWIO_GCC_QUPV3_WRAP2_S0_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e158) +#define HWIO_GCC_QUPV3_WRAP2_S0_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e158) +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e274) +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e274) +#define HWIO_GCC_QUPV3_WRAP2_S1_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e274) +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e28c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e28c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e28c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e294) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e294) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e294) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e298) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e298) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e298) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e29c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e29c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e29c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2a0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2a0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2a0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2a4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2a4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2a4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2a8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2a8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2a8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2ac) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2ac) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2ac) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2b0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2b0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2b0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2d4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2d4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2d4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2d8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2d8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2d8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2dc) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2dc) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2dc) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2e0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2e0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2e0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2e4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2e4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2e4) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2e8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2e8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2e8) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2ec) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2ec) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2ec) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e2f0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e2f0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e2f0) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e314) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e314) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e314) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e318) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e318) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e318) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e31c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e31c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e31c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e320) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e320) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e320) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e324) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e324) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e324) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e328) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e328) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e328) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e32c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e32c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e32c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e330) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e330) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e330) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e354) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e354) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e354) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e358) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e358) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e358) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e35c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e35c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e35c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e360) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e360) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e360) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e364) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e364) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e364) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e368) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e368) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e368) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e36c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e36c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e36c) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e370) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e370) +#define HWIO_GCC_QUPV3_WRAP2_SE1_QUPV3_WRAP2_S1_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e370) +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e278) +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e278) +#define HWIO_GCC_QUPV3_WRAP2_S1_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e278) +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e27c) +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e27c) +#define HWIO_GCC_QUPV3_WRAP2_S1_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e27c) +#define HWIO_GCC_QUPV3_WRAP2_S1_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e280) +#define HWIO_GCC_QUPV3_WRAP2_S1_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e280) +#define HWIO_GCC_QUPV3_WRAP2_S1_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e280) +#define HWIO_GCC_QUPV3_WRAP2_S1_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e284) +#define HWIO_GCC_QUPV3_WRAP2_S1_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e284) +#define HWIO_GCC_QUPV3_WRAP2_S1_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e284) +#define HWIO_GCC_QUPV3_WRAP2_S1_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e288) +#define HWIO_GCC_QUPV3_WRAP2_S1_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e288) +#define HWIO_GCC_QUPV3_WRAP2_S1_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e288) +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e3a4) +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e3a4) +#define HWIO_GCC_QUPV3_WRAP2_S2_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e3a4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e3bc) +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3bc) +#define HWIO_GCC_QUPV3_WRAP2_SE2_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3bc) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e3c4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3c4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3c4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e3c8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3c8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3c8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e3cc) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3cc) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3cc) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e3d0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3d0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3d0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e3d4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3d4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3d4) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e3d8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3d8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3d8) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e3dc) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3dc) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3dc) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e3e0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3e0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3e0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e404) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e404) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e404) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e408) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e408) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e408) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e40c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e40c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e40c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e410) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e410) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e410) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e414) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e414) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e414) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e418) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e418) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e418) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e41c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e41c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e41c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e420) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e420) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e420) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e444) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e444) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e444) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e448) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e448) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e448) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e44c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e44c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e44c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e450) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e450) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e450) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e454) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e454) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e454) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e458) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e458) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e458) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e45c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e45c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e45c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e460) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e460) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e460) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e484) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e484) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e484) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e488) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e488) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e488) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e48c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e48c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e48c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e490) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e490) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e490) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e494) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e494) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e494) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e498) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e498) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e498) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e49c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e49c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e49c) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e4a0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e4a0) +#define HWIO_GCC_QUPV3_WRAP2_SE2_QUPV3_WRAP2_S2_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e4a0) +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e3a8) +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3a8) +#define HWIO_GCC_QUPV3_WRAP2_S2_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3a8) +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e3ac) +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e3ac) +#define HWIO_GCC_QUPV3_WRAP2_S2_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e3ac) +#define HWIO_GCC_QUPV3_WRAP2_S2_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e3b0) +#define HWIO_GCC_QUPV3_WRAP2_S2_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e3b0) +#define HWIO_GCC_QUPV3_WRAP2_S2_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e3b0) +#define HWIO_GCC_QUPV3_WRAP2_S2_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e3b4) +#define HWIO_GCC_QUPV3_WRAP2_S2_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e3b4) +#define HWIO_GCC_QUPV3_WRAP2_S2_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e3b4) +#define HWIO_GCC_QUPV3_WRAP2_S2_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e3b8) +#define HWIO_GCC_QUPV3_WRAP2_S2_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e3b8) +#define HWIO_GCC_QUPV3_WRAP2_S2_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e3b8) +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e4d4) +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e4d4) +#define HWIO_GCC_QUPV3_WRAP2_S3_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e4d4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e4ec) +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e4ec) +#define HWIO_GCC_QUPV3_WRAP2_SE3_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e4ec) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e4f4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e4f4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e4f4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e4f8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e4f8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e4f8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e4fc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e4fc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e4fc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e500) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e500) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e500) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e504) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e504) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e504) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e508) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e508) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e508) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e50c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e50c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e50c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e510) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e510) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e510) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e534) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e534) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e534) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e538) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e538) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e538) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e53c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e53c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e53c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e540) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e540) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e540) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e544) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e544) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e544) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e548) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e548) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e548) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e54c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e54c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e54c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e550) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e550) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e550) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e574) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e574) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e574) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e578) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e578) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e578) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e57c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e57c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e57c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e580) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e580) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e580) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e584) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e584) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e584) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e588) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e588) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e588) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e58c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e58c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e58c) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e590) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e590) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e590) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e5b4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e5b4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e5b4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e5b8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e5b8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e5b8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e5bc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e5bc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e5bc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e5c0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e5c0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e5c0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e5c4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e5c4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e5c4) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e5c8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e5c8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e5c8) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e5cc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e5cc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e5cc) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e5d0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e5d0) +#define HWIO_GCC_QUPV3_WRAP2_SE3_QUPV3_WRAP2_S3_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e5d0) +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e4d8) +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e4d8) +#define HWIO_GCC_QUPV3_WRAP2_S3_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e4d8) +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e4dc) +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e4dc) +#define HWIO_GCC_QUPV3_WRAP2_S3_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e4dc) +#define HWIO_GCC_QUPV3_WRAP2_S3_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e4e0) +#define HWIO_GCC_QUPV3_WRAP2_S3_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e4e0) +#define HWIO_GCC_QUPV3_WRAP2_S3_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e4e0) +#define HWIO_GCC_QUPV3_WRAP2_S3_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e4e4) +#define HWIO_GCC_QUPV3_WRAP2_S3_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e4e4) +#define HWIO_GCC_QUPV3_WRAP2_S3_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e4e4) +#define HWIO_GCC_QUPV3_WRAP2_S3_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e4e8) +#define HWIO_GCC_QUPV3_WRAP2_S3_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e4e8) +#define HWIO_GCC_QUPV3_WRAP2_S3_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e4e8) +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e604) +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e604) +#define HWIO_GCC_QUPV3_WRAP2_S4_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e604) +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e61c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e61c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e61c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e624) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e624) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e624) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e628) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e628) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e628) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e62c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e62c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e62c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e630) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e630) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e630) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e634) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e634) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e634) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e638) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e638) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e638) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e63c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e63c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e63c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e640) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e640) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e640) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e664) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e664) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e664) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e668) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e668) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e668) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e66c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e66c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e66c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e670) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e670) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e670) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e674) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e674) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e674) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e678) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e678) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e678) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e67c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e67c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e67c) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e680) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e680) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e680) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6a4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6a4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6a4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6a8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6a8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6a8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6ac) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6ac) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6ac) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6b0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6b0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6b0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6b4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6b4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6b4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6b8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6b8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6b8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6bc) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6bc) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6bc) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6c0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6c0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6c0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6e4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6e4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6e4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6e8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6e8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6e8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6ec) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6ec) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6ec) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6f0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6f0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6f0) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6f4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6f4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6f4) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6f8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6f8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6f8) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e6fc) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e6fc) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e6fc) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e700) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e700) +#define HWIO_GCC_QUPV3_WRAP2_SE4_QUPV3_WRAP2_S4_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e700) +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e608) +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e608) +#define HWIO_GCC_QUPV3_WRAP2_S4_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e608) +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e60c) +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e60c) +#define HWIO_GCC_QUPV3_WRAP2_S4_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e60c) +#define HWIO_GCC_QUPV3_WRAP2_S4_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e610) +#define HWIO_GCC_QUPV3_WRAP2_S4_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e610) +#define HWIO_GCC_QUPV3_WRAP2_S4_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e610) +#define HWIO_GCC_QUPV3_WRAP2_S4_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e614) +#define HWIO_GCC_QUPV3_WRAP2_S4_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e614) +#define HWIO_GCC_QUPV3_WRAP2_S4_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e614) +#define HWIO_GCC_QUPV3_WRAP2_S4_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e618) +#define HWIO_GCC_QUPV3_WRAP2_S4_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e618) +#define HWIO_GCC_QUPV3_WRAP2_S4_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e618) +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e734) +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e734) +#define HWIO_GCC_QUPV3_WRAP2_S5_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e734) +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e74c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e74c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_CMD_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e74c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e754) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e754) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e754) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e758) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e758) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e758) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e75c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e75c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e75c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e760) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e760) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e760) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e764) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e764) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e764) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e768) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e768) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e768) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e76c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e76c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e76c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e770) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e770) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e770) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e794) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e794) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e794) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e798) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e798) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e798) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e79c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e79c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e79c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7a0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7a0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7a0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7a4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7a4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7a4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7a8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7a8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7a8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7ac) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7ac) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7ac) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7b0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7b0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_M_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7b0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7d4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7d4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7d4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7d8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7d8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7d8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7dc) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7dc) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7dc) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7e0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7e0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7e0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7e4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7e4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7e4) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7e8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7e8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7e8) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7ec) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7ec) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7ec) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e7f0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e7f0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_N_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e7f0) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e814) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e814) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF0_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e814) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e818) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e818) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF1_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e818) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e81c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e81c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF2_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e81c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e820) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e820) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF3_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e820) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e824) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e824) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF4_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e824) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e828) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e828) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF5_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e828) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e82c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e82c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF6_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e82c) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001e830) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e830) +#define HWIO_GCC_QUPV3_WRAP2_SE5_QUPV3_WRAP2_S5_PERF7_D_DFSR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e830) +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e738) +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e738) +#define HWIO_GCC_QUPV3_WRAP2_S5_CMD_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e738) +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e73c) +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001e73c) +#define HWIO_GCC_QUPV3_WRAP2_S5_CFG_RCGR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001e73c) +#define HWIO_GCC_QUPV3_WRAP2_S5_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e740) +#define HWIO_GCC_QUPV3_WRAP2_S5_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e740) +#define HWIO_GCC_QUPV3_WRAP2_S5_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e740) +#define HWIO_GCC_QUPV3_WRAP2_S5_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e744) +#define HWIO_GCC_QUPV3_WRAP2_S5_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e744) +#define HWIO_GCC_QUPV3_WRAP2_S5_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e744) +#define HWIO_GCC_QUPV3_WRAP2_S5_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001e748) +#define HWIO_GCC_QUPV3_WRAP2_S5_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0001e748) +#define HWIO_GCC_QUPV3_WRAP2_S5_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0001e748) +#define HWIO_GCC_RBCPR_MMCX_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000d000) +#define HWIO_GCC_RBCPR_MMCX_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000d000) +#define HWIO_GCC_RBCPR_MMCX_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000d000) +#define HWIO_GCC_RBCPR_MMCX_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000d004) +#define HWIO_GCC_RBCPR_MMCX_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000d004) +#define HWIO_GCC_RBCPR_MMCX_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000d004) +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000d008) +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000d008) +#define HWIO_GCC_RBCPR_MMCX_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000d008) +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000d00c) +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000d00c) +#define HWIO_GCC_RBCPR_MMCX_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000d00c) +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000d010) +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000d010) +#define HWIO_GCC_RBCPR_MMCX_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000d010) +#define HWIO_GCC_EMAC_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006000) +#define HWIO_GCC_EMAC_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00006000) +#define HWIO_GCC_EMAC_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00006000) +#define HWIO_GCC_EMAC_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006004) +#define HWIO_GCC_EMAC_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006004) +#define HWIO_GCC_EMAC_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006004) +#define HWIO_GCC_EMAC_CFG_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00006008) +#define HWIO_GCC_EMAC_CFG_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006008) +#define HWIO_GCC_EMAC_CFG_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006008) +#define HWIO_GCC_EMAC_CFG2_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000600c) +#define HWIO_GCC_EMAC_CFG2_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000600c) +#define HWIO_GCC_EMAC_CFG2_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000600c) +#define HWIO_GCC_EMAC_AXI_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006010) +#define HWIO_GCC_EMAC_AXI_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006010) +#define HWIO_GCC_EMAC_AXI_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006010) +#define HWIO_GCC_EMAC_SLV_AHB_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00006014) +#define HWIO_GCC_EMAC_SLV_AHB_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006014) +#define HWIO_GCC_EMAC_SLV_AHB_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006014) +#define HWIO_GCC_EMAC_RGMII_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00006018) +#define HWIO_GCC_EMAC_RGMII_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006018) +#define HWIO_GCC_EMAC_RGMII_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006018) +#define HWIO_GCC_EMAC_RGMII_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000601c) +#define HWIO_GCC_EMAC_RGMII_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000601c) +#define HWIO_GCC_EMAC_RGMII_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000601c) +#define HWIO_GCC_EMAC_RGMII_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00006020) +#define HWIO_GCC_EMAC_RGMII_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006020) +#define HWIO_GCC_EMAC_RGMII_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006020) +#define HWIO_GCC_EMAC_RGMII_M_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006024) +#define HWIO_GCC_EMAC_RGMII_M_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006024) +#define HWIO_GCC_EMAC_RGMII_M_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006024) +#define HWIO_GCC_EMAC_RGMII_N_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006028) +#define HWIO_GCC_EMAC_RGMII_N_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006028) +#define HWIO_GCC_EMAC_RGMII_N_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006028) +#define HWIO_GCC_EMAC_RGMII_D_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0000602c) +#define HWIO_GCC_EMAC_RGMII_D_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000602c) +#define HWIO_GCC_EMAC_RGMII_D_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000602c) +#define HWIO_GCC_EMAC_PTP_CBCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006034) +#define HWIO_GCC_EMAC_PTP_CBCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006034) +#define HWIO_GCC_EMAC_PTP_CBCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006034) +#define HWIO_GCC_EMAC_PTP_CMD_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00006038) +#define HWIO_GCC_EMAC_PTP_CMD_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006038) +#define HWIO_GCC_EMAC_PTP_CMD_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006038) +#define HWIO_GCC_EMAC_PTP_CFG_RCGR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000603c) +#define HWIO_GCC_EMAC_PTP_CFG_RCGR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000603c) +#define HWIO_GCC_EMAC_PTP_CFG_RCGR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000603c) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000ff8) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000ff8) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP1_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000ff8) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000ff4) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000ff4) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP2_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000ff4) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000ff0) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000ff0) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP3_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000ff0) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fec) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fec) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP4_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fec) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fe8) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fe8) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP5_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fe8) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fe4) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fe4) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP6_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fe4) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fe0) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fe0) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP7_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fe0) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fdc) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fdc) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP8_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fdc) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fd8) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fd8) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP9_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fd8) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fd4) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fd4) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP10_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fd4) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fd0) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fd0) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP11_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fd0) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fcc) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fcc) +#define HWIO_GCC_GPLL0_OUT_MAIN_PWRGRP12_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fcc) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP13_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fc8) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP13_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fc8) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP13_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fc8) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fc4) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fc4) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP14_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fc4) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fc0) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fc0) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP15_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fc0) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fbc) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fbc) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP16_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fbc) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fb8) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fb8) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP17_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fb8) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fb4) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fb4) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP18_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fb4) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fb0) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fb0) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP19_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fb0) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fac) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fac) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP20_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fac) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fa8) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fa8) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP21_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fa8) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fa4) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fa4) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP22_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fa4) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000fa0) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000fa0) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP23_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000fa0) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000f9c) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000f9c) +#define HWIO_GCC_GPLL0_OUT_EVEN_PWRGRP24_CLKGEN_ACGC_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000f9c) +#define HWIO_GCC_TZ_IPA_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003b000) +#define HWIO_GCC_TZ_IPA_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003b000) +#define HWIO_GCC_TZ_IPA_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003b000) +#define HWIO_GCC_TZ_UFS_CARD_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003b004) +#define HWIO_GCC_TZ_UFS_CARD_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003b004) +#define HWIO_GCC_TZ_UFS_CARD_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003b004) +#define HWIO_GCC_TZ_EMAC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003b008) +#define HWIO_GCC_TZ_EMAC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003b008) +#define HWIO_GCC_TZ_EMAC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003b008) +#define HWIO_GCC_TZ_USB30_PRIM_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003b00c) +#define HWIO_GCC_TZ_USB30_PRIM_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0003b00c) +#define HWIO_GCC_TZ_USB30_PRIM_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0003b00c) +#define HWIO_GCC_TZ_UFS_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003b010) +#define HWIO_GCC_TZ_UFS_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003b010) +#define HWIO_GCC_TZ_UFS_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003b010) +#define HWIO_GCC_TZ_ANOC_TBU_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003b014) +#define HWIO_GCC_TZ_ANOC_TBU_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003b014) +#define HWIO_GCC_TZ_ANOC_TBU_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003b014) +#define HWIO_GCC_TZ_PCIE_0_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003b018) +#define HWIO_GCC_TZ_PCIE_0_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003b018) +#define HWIO_GCC_TZ_PCIE_0_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003b018) +#define HWIO_GCC_TZ_PCIE_1_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003b01c) +#define HWIO_GCC_TZ_PCIE_1_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003b01c) +#define HWIO_GCC_TZ_PCIE_1_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003b01c) +#define HWIO_GCC_TZ_USB30_SEC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003b020) +#define HWIO_GCC_TZ_USB30_SEC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003b020) +#define HWIO_GCC_TZ_USB30_SEC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003b020) +#define HWIO_GCC_TZ_MMNOC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003b024) +#define HWIO_GCC_TZ_MMNOC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003b024) +#define HWIO_GCC_TZ_MMNOC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003b024) +#define HWIO_GCC_MSS_IPA_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003e000) +#define HWIO_GCC_MSS_IPA_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003e000) +#define HWIO_GCC_MSS_IPA_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003e000) +#define HWIO_GCC_MSS_UFS_CARD_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003e004) +#define HWIO_GCC_MSS_UFS_CARD_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003e004) +#define HWIO_GCC_MSS_UFS_CARD_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003e004) +#define HWIO_GCC_MSS_EMAC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003e008) +#define HWIO_GCC_MSS_EMAC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003e008) +#define HWIO_GCC_MSS_EMAC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003e008) +#define HWIO_GCC_MSS_USB30_PRIM_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003e00c) +#define HWIO_GCC_MSS_USB30_PRIM_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0003e00c) +#define HWIO_GCC_MSS_USB30_PRIM_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0003e00c) +#define HWIO_GCC_MSS_UFS_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003e010) +#define HWIO_GCC_MSS_UFS_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003e010) +#define HWIO_GCC_MSS_UFS_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003e010) +#define HWIO_GCC_MSS_ANOC_TBU_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003e014) +#define HWIO_GCC_MSS_ANOC_TBU_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003e014) +#define HWIO_GCC_MSS_ANOC_TBU_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003e014) +#define HWIO_GCC_MSS_PCIE_0_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003e018) +#define HWIO_GCC_MSS_PCIE_0_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003e018) +#define HWIO_GCC_MSS_PCIE_0_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003e018) +#define HWIO_GCC_MSS_PCIE_1_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003e01c) +#define HWIO_GCC_MSS_PCIE_1_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003e01c) +#define HWIO_GCC_MSS_PCIE_1_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003e01c) +#define HWIO_GCC_MSS_USB30_SEC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003e020) +#define HWIO_GCC_MSS_USB30_SEC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0003e020) +#define HWIO_GCC_MSS_USB30_SEC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0003e020) +#define HWIO_GCC_MSS_MMNOC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003e024) +#define HWIO_GCC_MSS_MMNOC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003e024) +#define HWIO_GCC_MSS_MMNOC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003e024) +#define HWIO_GCC_SP_IPA_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003f000) +#define HWIO_GCC_SP_IPA_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003f000) +#define HWIO_GCC_SP_IPA_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003f000) +#define HWIO_GCC_SP_UFS_CARD_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003f004) +#define HWIO_GCC_SP_UFS_CARD_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003f004) +#define HWIO_GCC_SP_UFS_CARD_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003f004) +#define HWIO_GCC_SP_EMAC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003f008) +#define HWIO_GCC_SP_EMAC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003f008) +#define HWIO_GCC_SP_EMAC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003f008) +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003f00c) +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0003f00c) +#define HWIO_GCC_SP_USB30_PRIM_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0003f00c) +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003f010) +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003f010) +#define HWIO_GCC_SP_UFS_PHY_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003f010) +#define HWIO_GCC_SP_ANOC_TBU_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003f014) +#define HWIO_GCC_SP_ANOC_TBU_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003f014) +#define HWIO_GCC_SP_ANOC_TBU_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003f014) +#define HWIO_GCC_SP_PCIE_0_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003f018) +#define HWIO_GCC_SP_PCIE_0_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003f018) +#define HWIO_GCC_SP_PCIE_0_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003f018) +#define HWIO_GCC_SP_PCIE_1_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003f01c) +#define HWIO_GCC_SP_PCIE_1_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003f01c) +#define HWIO_GCC_SP_PCIE_1_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003f01c) +#define HWIO_GCC_SP_USB30_SEC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003f020) +#define HWIO_GCC_SP_USB30_SEC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003f020) +#define HWIO_GCC_SP_USB30_SEC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003f020) +#define HWIO_GCC_SP_MMNOC_SGDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0003f024) +#define HWIO_GCC_SP_MMNOC_SGDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0003f024) +#define HWIO_GCC_SP_MMNOC_SGDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0003f024) +#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00075038) +#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075038) +#define HWIO_GCC_GPLL0_UFS_CARD_TX_SYMBOL_0_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075038) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00075048) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075048) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_0_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075048) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000750b0) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000750b0) +#define HWIO_GCC_GPLL0_UFS_CARD_RX_SYMBOL_1_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000750b0) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00077038) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077038) +#define HWIO_GCC_GPLL0_UFS_PHY_TX_SYMBOL_0_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077038) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00077048) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077048) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_0_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077048) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000770b0) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000770b0) +#define HWIO_GCC_GPLL0_UFS_PHY_RX_SYMBOL_1_ACGCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000770b0) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000f05c) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000f05c) +#define HWIO_GCC_USB3_PRIM_PHY_PIPE_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000f05c) +#define HWIO_GCC_USB3_SEC_PHY_PIPE_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0001005c) +#define HWIO_GCC_USB3_SEC_PHY_PIPE_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001005c) +#define HWIO_GCC_USB3_SEC_PHY_PIPE_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001005c) +#define HWIO_GCC_PCIE_0_PIPE_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006b028) +#define HWIO_GCC_PCIE_0_PIPE_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006b028) +#define HWIO_GCC_PCIE_0_PIPE_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006b028) +#define HWIO_GCC_PCIE_1_PIPE_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008d028) +#define HWIO_GCC_PCIE_1_PIPE_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008d028) +#define HWIO_GCC_PCIE_1_PIPE_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008d028) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_TX_SYMBOL_0_MUX_MUXR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00075040) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_TX_SYMBOL_0_MUX_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075040) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_TX_SYMBOL_0_MUX_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075040) +#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00075044) +#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075044) +#define HWIO_GCC_UFS_CARD_TX_SYMBOL_0_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075044) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_0_MUX_MUXR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00075050) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_0_MUX_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075050) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_0_MUX_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075050) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00075054) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00075054) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_0_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00075054) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_1_MUX_MUXR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000750b8) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_1_MUX_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000750b8) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_CARD_RX_SYMBOL_1_MUX_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000750b8) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x000750bc) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000750bc) +#define HWIO_GCC_UFS_CARD_RX_SYMBOL_1_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000750bc) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00077040) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077040) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_TX_SYMBOL_0_MUX_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077040) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077044) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077044) +#define HWIO_GCC_UFS_PHY_TX_SYMBOL_0_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077044) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00077050) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077050) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_0_MUX_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077050) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00077054) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00077054) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_0_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00077054) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x000770b8) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000770b8) +#define HWIO_GCC_GPLL0_AND_PLL_TEST_SE_UFS_PHY_RX_SYMBOL_1_MUX_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000770b8) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x000770bc) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x000770bc) +#define HWIO_GCC_UFS_PHY_RX_SYMBOL_1_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x000770bc) +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008a148) +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a148) +#define HWIO_GCC_MSS_Q6SS_BOOT_GPLL0_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a148) +#define HWIO_GCC_ACC_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0003e030) +#define HWIO_GCC_ACC_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003e030) +#define HWIO_GCC_ACC_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003e030) +#define HWIO_GCC_CPUSS_AHB_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00048024) +#define HWIO_GCC_CPUSS_AHB_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00048024) +#define HWIO_GCC_CPUSS_AHB_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00048024) +#define HWIO_GCC_SSC_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00054000) +#define HWIO_GCC_SSC_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00054000) +#define HWIO_GCC_SSC_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00054000) +#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00054004) +#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00054004) +#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00054004) +#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00054008) +#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00054008) +#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00054008) +#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005400c) +#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005400c) +#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005400c) +#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00054010) +#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00054010) +#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00054010) +#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00054014) +#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00054014) +#define HWIO_GCC_SSC_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00054014) +#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00054018) +#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00054018) +#define HWIO_GCC_SSC_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00054018) +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00051000) +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00051000) +#define HWIO_GCC_RPM_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00051000) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00051004) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00051004) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00051004) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00051008) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00051008) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00051008) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005100c) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005100c) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005100c) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00051010) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00051010) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00051010) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00051014) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00051014) +#define HWIO_GCC_RPM_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00051014) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00051018) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00051018) +#define HWIO_GCC_RPM_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00051018) +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00052000) +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00052000) +#define HWIO_GCC_APCS_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00052000) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00052004) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052004) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052004) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00052008) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052008) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052008) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005200c) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005200c) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005200c) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00052010) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052010) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052010) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00052014) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052014) +#define HWIO_GCC_APCS_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052014) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00052018) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052018) +#define HWIO_GCC_APCS_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052018) +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00053000) +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00053000) +#define HWIO_GCC_APCS_TZ_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00053000) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00053004) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00053004) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00053004) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00053008) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00053008) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00053008) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005300c) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005300c) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005300c) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00053010) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00053010) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00053010) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00053014) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00053014) +#define HWIO_GCC_APCS_TZ_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00053014) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00053018) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00053018) +#define HWIO_GCC_APCS_TZ_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00053018) +#define HWIO_GCC_LPASS_DSP_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00055000) +#define HWIO_GCC_LPASS_DSP_GPLL_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00055000) +#define HWIO_GCC_LPASS_DSP_GPLL_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00055000) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00055004) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00055004) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00055004) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00055008) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00055008) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00055008) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005500c) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005500c) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005500c) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00055010) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00055010) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00055010) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00055014) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00055014) +#define HWIO_GCC_LPASS_DSP_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00055014) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00055018) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00055018) +#define HWIO_GCC_LPASS_DSP_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00055018) +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00056000) +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00056000) +#define HWIO_GCC_HYP_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00056000) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00056004) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00056004) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00056004) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00056008) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00056008) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00056008) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005600c) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005600c) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005600c) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00056010) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00056010) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00056010) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00056014) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00056014) +#define HWIO_GCC_HYP_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00056014) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00056018) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00056018) +#define HWIO_GCC_HYP_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00056018) +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00057000) +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00057000) +#define HWIO_GCC_SPARE_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00057000) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00057004) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00057004) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00057004) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00057008) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00057008) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00057008) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005700c) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005700c) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005700c) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00057010) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00057010) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00057010) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00057014) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00057014) +#define HWIO_GCC_SPARE_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00057014) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00057018) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00057018) +#define HWIO_GCC_SPARE_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00057018) +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0005a000) +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0005a000) +#define HWIO_GCC_SPARE1_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0005a000) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005a004) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005a004) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005a004) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005a008) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005a008) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005a008) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005a00c) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005a00c) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005a00c) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005a010) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005a010) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005a010) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005a014) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005a014) +#define HWIO_GCC_SPARE1_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005a014) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005a018) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005a018) +#define HWIO_GCC_SPARE1_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005a018) +#define HWIO_GCC_TURING_DSP_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0005b000) +#define HWIO_GCC_TURING_DSP_GPLL_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b000) +#define HWIO_GCC_TURING_DSP_GPLL_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b000) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005b004) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b004) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b004) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005b008) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b008) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b008) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005b00c) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b00c) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b00c) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005b010) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b010) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b010) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005b014) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b014) +#define HWIO_GCC_TURING_DSP_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b014) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0005b018) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005b018) +#define HWIO_GCC_TURING_DSP_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005b018) +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00069000) +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00069000) +#define HWIO_GCC_SPARE2_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00069000) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00069004) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00069004) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00069004) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00069008) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00069008) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00069008) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0006900c) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006900c) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006900c) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00069010) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00069010) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00069010) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00069014) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00069014) +#define HWIO_GCC_SPARE2_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00069014) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00069018) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00069018) +#define HWIO_GCC_SPARE2_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00069018) +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00035000) +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00035000) +#define HWIO_GCC_MSS_Q6_GPLL_ENA_VOTE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00035000) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00035004) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035004) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035004) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00035008) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035008) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035008) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0003500c) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0003500c) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0003500c) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00035010) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035010) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_1_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035010) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00035014) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035014) +#define HWIO_GCC_MSS_Q6_CLOCK_BRANCH_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035014) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00035018) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035018) +#define HWIO_GCC_MSS_Q6_CLOCK_SLEEP_ENA_VOTE_2_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035018) +#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006c014) +#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0006c014) +#define HWIO_GCC_PCIE_0_LINK_DOWN_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0006c014) +#define HWIO_GCC_PCIE_0_MISC_RESET_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006c018) +#define HWIO_GCC_PCIE_0_MISC_RESET_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006c018) +#define HWIO_GCC_PCIE_0_MISC_RESET_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006c018) +#define HWIO_GCC_PCIE_0_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006c01c) +#define HWIO_GCC_PCIE_0_PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006c01c) +#define HWIO_GCC_PCIE_0_PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006c01c) +#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006c020) +#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c020) +#define HWIO_GCC_PCIE_0_NOCSR_COM_PHY_BCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c020) +#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0006c028) +#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006c028) +#define HWIO_GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006c028) +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006f00c) +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0006f00c) +#define HWIO_GCC_PCIE_PHY_CFG_AHB_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0006f00c) +#define HWIO_GCC_PCIE_PHY_COM_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006f010) +#define HWIO_GCC_PCIE_PHY_COM_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006f010) +#define HWIO_GCC_PCIE_PHY_COM_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006f010) +#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008e014) +#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0008e014) +#define HWIO_GCC_PCIE_1_LINK_DOWN_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0008e014) +#define HWIO_GCC_PCIE_1_MISC_RESET_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008e018) +#define HWIO_GCC_PCIE_1_MISC_RESET_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008e018) +#define HWIO_GCC_PCIE_1_MISC_RESET_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008e018) +#define HWIO_GCC_PCIE_1_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008e01c) +#define HWIO_GCC_PCIE_1_PHY_BCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008e01c) +#define HWIO_GCC_PCIE_1_PHY_BCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008e01c) +#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008e020) +#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008e020) +#define HWIO_GCC_PCIE_1_NOCSR_COM_PHY_BCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008e020) +#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008e000) +#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008e000) +#define HWIO_GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008e000) +#define HWIO_GCC_SSC_RESET_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00063020) +#define HWIO_GCC_SSC_RESET_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00063020) +#define HWIO_GCC_SSC_RESET_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00063020) +#define HWIO_GCC_DEBUG_MUX_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00062000) +#define HWIO_GCC_DEBUG_MUX_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00062000) +#define HWIO_GCC_DEBUG_MUX_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00062000) +#define HWIO_GCC_PLL_TEST_MUX_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006200c) +#define HWIO_GCC_PLL_TEST_MUX_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006200c) +#define HWIO_GCC_PLL_TEST_MUX_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006200c) +#define HWIO_GCC_PLL_RESET_N_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00062018) +#define HWIO_GCC_PLL_RESET_N_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00062018) +#define HWIO_GCC_PLL_RESET_N_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00062018) +#define HWIO_GCC_PLL_STATUS_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006201c) +#define HWIO_GCC_PLL_STATUS_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006201c) +#define HWIO_GCC_PLL_STATUS_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006201c) +#define HWIO_GCC_PLL_BYPASSNL_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00062020) +#define HWIO_GCC_PLL_BYPASSNL_MUXR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00062020) +#define HWIO_GCC_PLL_BYPASSNL_MUXR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00062020) +#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00062030) +#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00062030) +#define HWIO_GCC_DEBUG_OR_PLL_TEST_MUX_MUXR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00062030) +#define HWIO_GCC_PLLTEST_PAD_CFG_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00062034) +#define HWIO_GCC_PLLTEST_PAD_CFG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00062034) +#define HWIO_GCC_PLLTEST_PAD_CFG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00062034) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00062038) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00062038) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00062038) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0006203c) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0006203c) +#define HWIO_GCC_CLOCK_FRQ_MEASURE_STATUS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0006203c) +#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00078040) +#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00078040) +#define HWIO_GCC_GDS_HW_CTRL_SW_OVRD_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00078040) +#define HWIO_GCC_UFS_CARD_BOOT_CLOCK_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00067000) +#define HWIO_GCC_UFS_CARD_BOOT_CLOCK_CTL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067000) +#define HWIO_GCC_UFS_CARD_BOOT_CLOCK_CTL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067000) +#define HWIO_GCC_UFS_PHY_BOOT_CLOCK_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00067020) +#define HWIO_GCC_UFS_PHY_BOOT_CLOCK_CTL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00067020) +#define HWIO_GCC_UFS_PHY_BOOT_CLOCK_CTL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00067020) +#define HWIO_GCC_USB_BOOT_CLOCK_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00068000) +#define HWIO_GCC_USB_BOOT_CLOCK_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00068000) +#define HWIO_GCC_USB_BOOT_CLOCK_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00068000) +#define HWIO_GCC_VTT_EN_TIMER_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0007300c) +#define HWIO_GCC_VTT_EN_TIMER_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007300c) +#define HWIO_GCC_VTT_EN_TIMER_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007300c) +#define HWIO_GCC_VREF_EN_TIMER_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073010) +#define HWIO_GCC_VREF_EN_TIMER_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00073010) +#define HWIO_GCC_VREF_EN_TIMER_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00073010) +#define HWIO_GCC_PVC_DATA_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00073014) +#define HWIO_GCC_PVC_DATA_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00073014) +#define HWIO_GCC_PVC_DATA_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00073014) +#define HWIO_GCC_GDS_HW_CTRL_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00078030) +#define HWIO_GCC_GDS_HW_CTRL_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00078030) +#define HWIO_GCC_GDS_HW_CTRL_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00078030) +#define HWIO_GCC_WCSS_PD_CLK_DIS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00011104) +#define HWIO_GCC_WCSS_PD_CLK_DIS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00011104) +#define HWIO_GCC_WCSS_PD_CLK_DIS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00011104) +#define HWIO_GCC_SPARE0_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006d000) +#define HWIO_GCC_SPARE0_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006d000) +#define HWIO_GCC_SPARE0_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006d000) +#define HWIO_GCC_SPARE1_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0006e000) +#define HWIO_GCC_SPARE1_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0006e000) +#define HWIO_GCC_SPARE1_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0006e000) +#define HWIO_GCC_SPARE2_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00081000) +#define HWIO_GCC_SPARE2_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00081000) +#define HWIO_GCC_SPARE2_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00081000) +#define HWIO_GCC_SPARE3_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00042000) +#define HWIO_GCC_SPARE3_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00042000) +#define HWIO_GCC_SPARE3_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00042000) +#define HWIO_GCC_SPARE4_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00039000) +#define HWIO_GCC_SPARE4_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00039000) +#define HWIO_GCC_SPARE4_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00039000) +#define HWIO_GCC_SPARE5_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00032000) +#define HWIO_GCC_SPARE5_REG_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00032000) +#define HWIO_GCC_SPARE5_REG_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00032000) +#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007f000) +#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007f000) +#define HWIO_GCC_RAW_SLEEP_CLK_CTRL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007f000) +#define HWIO_GCC_TSIF_0_RESET_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00036024) +#define HWIO_GCC_TSIF_0_RESET_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00036024) +#define HWIO_GCC_TSIF_0_RESET_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00036024) +#define HWIO_GCC_TSIF_1_RESET_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00036028) +#define HWIO_GCC_TSIF_1_RESET_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00036028) +#define HWIO_GCC_TSIF_1_RESET_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00036028) +#define HWIO_GCC_NPU_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0004d110) +#define HWIO_GCC_NPU_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0004d110) +#define HWIO_GCC_NPU_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0004d110) +#define HWIO_GCC_GPU_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00071028) +#define HWIO_GCC_GPU_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00071028) +#define HWIO_GCC_GPU_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00071028) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007b000) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0007b000) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0007b000) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b004) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b004) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b004) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b008) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b008) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b008) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b00c) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b00c) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b00c) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b010) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b010) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b010) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b014) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b014) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b014) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b018) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b018) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b018) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b01c) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b01c) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b01c) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b020) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b020) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b020) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b024) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b024) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b024) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007b028) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b028) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b028) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007b02c) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007b02c) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007b02c) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007b03c) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0007b03c) +#define HWIO_GCC_TZ_VOTE_GPU_SMMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0007b03c) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b040) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b040) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b040) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b044) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b044) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b044) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b048) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b048) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b048) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b04c) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b04c) +#define HWIO_GCC_TZ_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b04c) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b050) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b050) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b050) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b054) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b054) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_SF_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b054) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b058) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b058) +#define HWIO_GCC_TZ_VOTE_MMNOC_MMU_TBU_HF1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b058) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b05c) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b05c) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b05c) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007b060) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b060) +#define HWIO_GCC_TZ_VOTE_TURING_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b060) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007b064) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007b064) +#define HWIO_GCC_TZ_VOTE_ALL_SMMU_MMU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007b064) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007b068) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0007b068) +#define HWIO_GCC_TZ_VOTE_MMU_TCU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0007b068) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007c000) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0007c000) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0007c000) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c004) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c004) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c004) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c008) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c008) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c008) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c00c) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c00c) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c00c) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c010) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c010) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c010) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c014) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c014) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c014) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c018) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c018) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c018) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c01c) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c01c) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c01c) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c020) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c020) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c020) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c024) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c024) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c024) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0007c028) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c028) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c028) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007c02c) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0007c02c) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0007c02c) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007c03c) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0007c03c) +#define HWIO_GCC_HYP_VOTE_GPU_SMMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0007c03c) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c040) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c040) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c040) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c044) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c044) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c044) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c048) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c048) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c048) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c04c) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c04c) +#define HWIO_GCC_HYP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c04c) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c050) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c050) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c050) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c054) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c054) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_SF_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c054) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c058) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c058) +#define HWIO_GCC_HYP_VOTE_MMNOC_MMU_TBU_HF1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c058) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c05c) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c05c) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c05c) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007c060) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c060) +#define HWIO_GCC_HYP_VOTE_TURING_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c060) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0007c064) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007c064) +#define HWIO_GCC_HYP_VOTE_ALL_SMMU_MMU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007c064) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007c068) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0007c068) +#define HWIO_GCC_HYP_VOTE_MMU_TCU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0007c068) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007d000) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d000) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d000) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d004) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d004) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d004) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d008) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d008) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d008) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d00c) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d00c) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d00c) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d010) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d010) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d010) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d014) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d014) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d014) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d018) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d018) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d018) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d01c) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d01c) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d01c) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d020) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d020) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d020) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d024) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d024) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d024) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d028) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d028) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d028) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007d02c) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d02c) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d02c) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007d03c) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d03c) +#define HWIO_GCC_HLOS1_VOTE_GPU_SMMU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d03c) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d040) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d040) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d040) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d044) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d044) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d044) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d048) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d048) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d048) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d04c) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d04c) +#define HWIO_GCC_HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d04c) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d050) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d050) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d050) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d054) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d054) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d054) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d058) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d058) +#define HWIO_GCC_HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d058) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d05c) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d05c) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d05c) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d060) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d060) +#define HWIO_GCC_HLOS1_VOTE_TURING_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d060) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007d064) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d064) +#define HWIO_GCC_HLOS1_VOTE_ALL_SMMU_MMU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d064) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007d068) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007d068) +#define HWIO_GCC_HLOS1_VOTE_MMU_TCU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007d068) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007e000) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e000) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e000) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e004) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e004) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e004) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e008) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e008) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e008) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e00c) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e00c) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e00c) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e010) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e010) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e010) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e014) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e014) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e014) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e018) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e018) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e018) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e01c) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e01c) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e01c) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e020) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e020) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e020) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e024) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e024) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e024) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e028) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e028) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e028) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007e02c) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e02c) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e02c) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007e03c) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e03c) +#define HWIO_GCC_HLOS2_VOTE_GPU_SMMU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e03c) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e040) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e040) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e040) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e044) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e044) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e044) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e048) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e048) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e048) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e04c) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e04c) +#define HWIO_GCC_HLOS2_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e04c) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e050) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e050) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e050) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e054) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e054) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_SF_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e054) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e058) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e058) +#define HWIO_GCC_HLOS2_VOTE_MMNOC_MMU_TBU_HF1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e058) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e05c) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e05c) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e05c) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e060) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e060) +#define HWIO_GCC_HLOS2_VOTE_TURING_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e060) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0007e064) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e064) +#define HWIO_GCC_HLOS2_VOTE_ALL_SMMU_MMU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e064) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0007e068) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0007e068) +#define HWIO_GCC_HLOS2_VOTE_MMU_TCU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0007e068) +#define HWIO_GCC_UFS_MEM_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008c000) +#define HWIO_GCC_UFS_MEM_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c000) +#define HWIO_GCC_UFS_MEM_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c000) +#define HWIO_GCC_UFS_CARD_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008c004) +#define HWIO_GCC_UFS_CARD_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c004) +#define HWIO_GCC_UFS_CARD_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c004) +#define HWIO_GCC_USB3_PRIM_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008c008) +#define HWIO_GCC_USB3_PRIM_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c008) +#define HWIO_GCC_USB3_PRIM_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c008) +#define HWIO_GCC_USB3_SEC_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008c028) +#define HWIO_GCC_USB3_SEC_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c028) +#define HWIO_GCC_USB3_SEC_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c028) +#define HWIO_GCC_PCIE_0_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008c00c) +#define HWIO_GCC_PCIE_0_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c00c) +#define HWIO_GCC_PCIE_0_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c00c) +#define HWIO_GCC_PCIE_1_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008c02c) +#define HWIO_GCC_PCIE_1_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c02c) +#define HWIO_GCC_PCIE_1_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c02c) +#define HWIO_GCC_GPU_IREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c010) +#define HWIO_GCC_GPU_IREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c010) +#define HWIO_GCC_GPU_IREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c010) +#define HWIO_GCC_RX1_USB2_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008c014) +#define HWIO_GCC_RX1_USB2_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c014) +#define HWIO_GCC_RX1_USB2_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c014) +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008c018) +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c018) +#define HWIO_GCC_RX2_QLINK_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c018) +#define HWIO_GCC_RX3_CLKREF_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c01c) +#define HWIO_GCC_RX3_CLKREF_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c01c) +#define HWIO_GCC_RX3_CLKREF_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c01c) +#define HWIO_GCC_CXO2_TX1_CLKREF_EN1_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008c020) +#define HWIO_GCC_CXO2_TX1_CLKREF_EN1_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c020) +#define HWIO_GCC_CXO2_TX1_CLKREF_EN1_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c020) +#define HWIO_GCC_CLKREF_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008c024) +#define HWIO_GCC_CLKREF_SPARE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008c024) +#define HWIO_GCC_CLKREF_SPARE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008c024) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0000915c) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0000915c) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0000915c) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009160) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009160) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_STATUS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009160) +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00009464) +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009464) +#define HWIO_GCC_MMNOC_HALT_REQ_GDS_HW_CTRL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009464) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009468) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009468) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_STATUS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009468) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0000946c) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000946c) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_MASK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000946c) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00009470) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009470) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_IRQ_CLEAR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009470) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00009474) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00009474) +#define HWIO_GCC_MMNOC_GDS_HW_CTRL_SPARE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00009474) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00082678) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00082678) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00082678) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_STATUS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008267c) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_STATUS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008267c) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_STATUS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008267c) +#define HWIO_GCC_ANOC_HALT_REQ_GDS_HW_CTRL_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00082680) +#define HWIO_GCC_ANOC_HALT_REQ_GDS_HW_CTRL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082680) +#define HWIO_GCC_ANOC_HALT_REQ_GDS_HW_CTRL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082680) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_STATUS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082684) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_STATUS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082684) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_STATUS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082684) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_MASK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00082688) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_MASK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082688) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_MASK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082688) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008268c) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008268c) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_IRQ_CLEAR_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008268c) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_SPARE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00082690) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_SPARE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00082690) +#define HWIO_GCC_ANOC_TBU_GDS_HW_CTRL_SPARE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00082690) +#define HWIO_GCC_MSS_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008a024) +#define HWIO_GCC_MSS_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008a024) +#define HWIO_GCC_MSS_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008a024) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00086000) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00086000) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00086000) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086004) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086004) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086004) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086008) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086008) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086008) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008600c) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008600c) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008600c) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086010) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086010) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086010) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086014) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086014) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086014) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086018) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086018) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086018) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008601c) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008601c) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008601c) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086020) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086020) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086020) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086024) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086024) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086024) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00086028) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086028) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086028) +#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008602c) +#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008602c) +#define HWIO_GCC_SP_VOTE_MMU_TCU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008602c) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008603c) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0008603c) +#define HWIO_GCC_SP_VOTE_GPU_SMMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0008603c) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086040) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086040) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086040) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086044) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086044) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086044) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086048) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086048) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086048) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008604c) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008604c) +#define HWIO_GCC_SP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008604c) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086050) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086050) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086050) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086054) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086054) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_SF_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086054) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086058) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086058) +#define HWIO_GCC_SP_VOTE_MMNOC_MMU_TBU_HF1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086058) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008605c) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008605c) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008605c) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00086060) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086060) +#define HWIO_GCC_SP_VOTE_TURING_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086060) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00086064) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00086064) +#define HWIO_GCC_SP_VOTE_ALL_SMMU_MMU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00086064) +#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00086068) +#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00086068) +#define HWIO_GCC_SP_VOTE_MMU_TCU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00086068) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00087000) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00087000) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00087000) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087004) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087004) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087004) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087008) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087008) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087008) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008700c) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008700c) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008700c) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087010) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087010) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087010) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087014) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087014) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087014) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087018) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087018) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087018) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008701c) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008701c) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008701c) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087020) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087020) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087020) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087024) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087024) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087024) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00087028) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087028) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087028) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008702c) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0008702c) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0008702c) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008703c) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x0008703c) +#define HWIO_GCC_MSS_VOTE_GPU_SMMU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x0008703c) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087040) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087040) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087040) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087044) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087044) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087044) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087048) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087048) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087048) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008704c) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008704c) +#define HWIO_GCC_MSS_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008704c) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087050) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087050) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087050) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087054) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087054) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_SF_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087054) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087058) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087058) +#define HWIO_GCC_MSS_VOTE_MMNOC_MMU_TBU_HF1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087058) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0008705c) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0008705c) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0008705c) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00087060) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087060) +#define HWIO_GCC_MSS_VOTE_TURING_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087060) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00087064) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00087064) +#define HWIO_GCC_MSS_VOTE_ALL_SMMU_MMU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00087064) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00087068) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00087068) +#define HWIO_GCC_MSS_VOTE_MMU_TCU_GDS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00087068) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019000) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019000) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019000) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019004) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019004) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019004) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019008) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019008) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019008) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001900c) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001900c) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001900c) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019010) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019010) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019010) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019014) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019014) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019014) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019018) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019018) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019018) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001901c) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001901c) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001901c) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019020) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019020) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019020) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019024) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019024) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019024) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019028) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019028) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019028) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001902c) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001902c) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001902c) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001903c) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001903c) +#define HWIO_GCC_TURING_DSP_VOTE_GPU_SMMU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001903c) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019040) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019040) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019040) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019044) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019044) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019044) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019048) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019048) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_TBU2_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019048) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001904c) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001904c) +#define HWIO_GCC_TURING_DSP_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001904c) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019050) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019050) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019050) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019054) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019054) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_SF_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019054) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019058) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019058) +#define HWIO_GCC_TURING_DSP_VOTE_MMNOC_MMU_TBU_HF1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019058) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0001905c) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0001905c) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU0_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0001905c) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019060) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019060) +#define HWIO_GCC_TURING_DSP_VOTE_TURING_MMU_TBU1_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019060) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019064) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019064) +#define HWIO_GCC_TURING_DSP_VOTE_ALL_SMMU_MMU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019064) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00019068) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00019068) +#define HWIO_GCC_TURING_DSP_VOTE_MMU_TCU_GDS_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00019068) +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00051024) +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00051024) +#define HWIO_GCC_RPM_VOTE_QDSS_APB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00051024) +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00035024) +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00035024) +#define HWIO_GCC_MSS_Q6_VOTE_QDSS_APB_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00035024) +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00052024) +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00052024) +#define HWIO_GCC_APCS_VOTE_QDSS_APB_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00052024) +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00053024) +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00053024) +#define HWIO_GCC_APCS_TZ_VOTE_QDSS_APB_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00053024) +#define HWIO_GCC_SSC_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00054024) +#define HWIO_GCC_SSC_VOTE_QDSS_APB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00054024) +#define HWIO_GCC_SSC_VOTE_QDSS_APB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00054024) +#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00055024) +#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00055024) +#define HWIO_GCC_LPASS_DSP_VOTE_QDSS_APB_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00055024) +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00056024) +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS \ + + 0x00056024) +#define HWIO_GCC_HYP_VOTE_QDSS_APB_CLK_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS \ + + 0x00056024) +#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00057024) +#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00057024) +#define HWIO_GCC_TURING_DSP_VOTE_QDSS_APB_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00057024) +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0005a024) +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0005a024) +#define HWIO_GCC_SPARE1_VOTE_QDSS_APB_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0005a024) +#define HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00069024) +#define HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00069024) +#define HWIO_GCC_SPARE2_VOTE_QDSS_APB_CLK_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00069024) +#define HWIO_GCC_JBIST_MODE_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00080000) +#define HWIO_GCC_JBIST_MODE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00080000) +#define HWIO_GCC_JBIST_MODE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00080000) +#define HWIO_GCC_JBIST_CONFIG_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00080004) +#define HWIO_GCC_JBIST_CONFIG_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00080004) +#define HWIO_GCC_JBIST_CONFIG_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00080004) +#define HWIO_GCC_JBIST_USER_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00080008) +#define HWIO_GCC_JBIST_USER_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00080008) +#define HWIO_GCC_JBIST_USER_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00080008) +#define HWIO_GCC_JBIST_USER_CTL_U_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0008000c) +#define HWIO_GCC_JBIST_USER_CTL_U_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008000c) +#define HWIO_GCC_JBIST_USER_CTL_U_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008000c) +#define HWIO_GCC_JBIST_TEST_CTL_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00080010) +#define HWIO_GCC_JBIST_TEST_CTL_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00080010) +#define HWIO_GCC_JBIST_TEST_CTL_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00080010) +#define HWIO_GCC_JBIST_STATUS_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00080014) +#define HWIO_GCC_JBIST_STATUS_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00080014) +#define HWIO_GCC_JBIST_STATUS_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00080014) +#define HWIO_GCC_JBIST_MEAS_DONE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00080018) +#define HWIO_GCC_JBIST_MEAS_DONE_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00080018) +#define HWIO_GCC_JBIST_MEAS_DONE_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00080018) +#define HWIO_GCC_GLOBAL_EN_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x0008f000) +#define HWIO_GCC_GLOBAL_EN_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x0008f000) +#define HWIO_GCC_GLOBAL_EN_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x0008f000) +#define HWIO_GCC_CAM_CC_GDSCR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006100) +#define HWIO_GCC_CAM_CC_GDSCR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006100) +#define HWIO_GCC_CAM_CC_GDSCR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006100) +#define HWIO_GCC_WCSS_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00011100) +#define HWIO_GCC_WCSS_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00011100) +#define HWIO_GCC_WCSS_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00011100) +#define HWIO_GCC_GPLL0_CONFIG_CTL_FUSE_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00000100) +#define HWIO_GCC_GPLL0_CONFIG_CTL_FUSE_REG_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000100) +#define HWIO_GCC_GPLL0_CONFIG_CTL_FUSE_REG_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000100) +#define HWIO_GCC_GPLL0_CONFIG_CTL_U_FUSE_REG_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00000104) +#define HWIO_GCC_GPLL0_CONFIG_CTL_U_FUSE_REG_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000104) +#define HWIO_GCC_GPLL0_CONFIG_CTL_U_FUSE_REG_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000104) +#define HWIO_GCC_GPLL0_TEST_CTL_FUSE_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00000108) +#define HWIO_GCC_GPLL0_TEST_CTL_FUSE_REG_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00000108) +#define HWIO_GCC_GPLL0_TEST_CTL_FUSE_REG_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00000108) +#define HWIO_GCC_GPLL0_TEST_CTL_U_FUSE_REG_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0000010c) +#define HWIO_GCC_GPLL0_TEST_CTL_U_FUSE_REG_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0000010c) +#define HWIO_GCC_GPLL0_TEST_CTL_U_FUSE_REG_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0000010c) +#define HWIO_GCC_PLL0_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00000114) +#define HWIO_GCC_PLL0_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00000114) +#define HWIO_GCC_PLL0_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00000114) +#define HWIO_GCC_PLL1_CDIVR_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00001114) +#define HWIO_GCC_PLL1_CDIVR_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00001114) +#define HWIO_GCC_PLL1_CDIVR_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00001114) +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00094000) +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094000) +#define HWIO_GCC_RPMH_SYS_NOC_PERF0_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094000) +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091004) +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091004) +#define HWIO_GCC_RPMH_SYS_NOC_PERF1_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091004) +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091008) +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091008) +#define HWIO_GCC_RPMH_SYS_NOC_PERF2_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091008) +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009100c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009100c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF3_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009100c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091010) +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091010) +#define HWIO_GCC_RPMH_SYS_NOC_PERF4_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091010) +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091014) +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091014) +#define HWIO_GCC_RPMH_SYS_NOC_PERF5_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091014) +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091018) +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091018) +#define HWIO_GCC_RPMH_SYS_NOC_PERF6_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091018) +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009101c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009101c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF7_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009101c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091020) +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091020) +#define HWIO_GCC_RPMH_SYS_NOC_PERF8_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091020) +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091024) +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091024) +#define HWIO_GCC_RPMH_SYS_NOC_PERF9_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091024) +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091028) +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091028) +#define HWIO_GCC_RPMH_SYS_NOC_PERF10_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091028) +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009102c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009102c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF11_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009102c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091030) +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091030) +#define HWIO_GCC_RPMH_SYS_NOC_PERF12_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091030) +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091034) +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091034) +#define HWIO_GCC_RPMH_SYS_NOC_PERF13_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091034) +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00091038) +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00091038) +#define HWIO_GCC_RPMH_SYS_NOC_PERF14_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00091038) +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009103c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009103c) +#define HWIO_GCC_RPMH_SYS_NOC_PERF15_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009103c) +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00092004) +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092004) +#define HWIO_GCC_RPMH_CNOC_PERF0_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092004) +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00092008) +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092008) +#define HWIO_GCC_RPMH_CNOC_PERF1_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092008) +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009200c) +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009200c) +#define HWIO_GCC_RPMH_CNOC_PERF2_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009200c) +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00092010) +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092010) +#define HWIO_GCC_RPMH_CNOC_PERF3_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092010) +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00092014) +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092014) +#define HWIO_GCC_RPMH_CNOC_PERF4_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092014) +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00092018) +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092018) +#define HWIO_GCC_RPMH_CNOC_PERF5_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092018) +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009201c) +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009201c) +#define HWIO_GCC_RPMH_CNOC_PERF6_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009201c) +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00092020) +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092020) +#define HWIO_GCC_RPMH_CNOC_PERF7_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092020) +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00092024) +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092024) +#define HWIO_GCC_RPMH_CNOC_PERF8_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092024) +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00092028) +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092028) +#define HWIO_GCC_RPMH_CNOC_PERF9_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092028) +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009202c) +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009202c) +#define HWIO_GCC_RPMH_CNOC_PERF10_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009202c) +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00092030) +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092030) +#define HWIO_GCC_RPMH_CNOC_PERF11_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092030) +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00092034) +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092034) +#define HWIO_GCC_RPMH_CNOC_PERF12_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092034) +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00092038) +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092038) +#define HWIO_GCC_RPMH_CNOC_PERF13_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092038) +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009203c) +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009203c) +#define HWIO_GCC_RPMH_CNOC_PERF14_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009203c) +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00092040) +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00092040) +#define HWIO_GCC_RPMH_CNOC_PERF15_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00092040) +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093004) +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093004) +#define HWIO_GCC_RPMH_IPA_PERF0_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093004) +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093008) +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093008) +#define HWIO_GCC_RPMH_IPA_PERF1_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093008) +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009300c) +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009300c) +#define HWIO_GCC_RPMH_IPA_PERF2_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009300c) +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093010) +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093010) +#define HWIO_GCC_RPMH_IPA_PERF3_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093010) +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093014) +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093014) +#define HWIO_GCC_RPMH_IPA_PERF4_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093014) +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093018) +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093018) +#define HWIO_GCC_RPMH_IPA_PERF5_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093018) +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009301c) +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009301c) +#define HWIO_GCC_RPMH_IPA_PERF6_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009301c) +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093020) +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093020) +#define HWIO_GCC_RPMH_IPA_PERF7_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093020) +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093024) +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093024) +#define HWIO_GCC_RPMH_IPA_PERF8_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093024) +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093028) +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093028) +#define HWIO_GCC_RPMH_IPA_PERF9_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093028) +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009302c) +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009302c) +#define HWIO_GCC_RPMH_IPA_PERF10_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009302c) +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093030) +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093030) +#define HWIO_GCC_RPMH_IPA_PERF11_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093030) +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093034) +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093034) +#define HWIO_GCC_RPMH_IPA_PERF12_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093034) +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093038) +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093038) +#define HWIO_GCC_RPMH_IPA_PERF13_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093038) +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009303c) +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009303c) +#define HWIO_GCC_RPMH_IPA_PERF14_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009303c) +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00093040) +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00093040) +#define HWIO_GCC_RPMH_IPA_PERF15_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00093040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b004) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b004) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF0_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b004) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b008) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b008) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF1_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b008) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b00c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b00c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF2_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b00c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b010) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b010) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF3_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b010) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b014) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b014) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF4_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b014) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b018) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b018) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF5_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b018) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b01c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b01c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF6_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b01c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b020) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b020) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF7_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b020) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b024) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b024) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF8_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b024) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b028) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b028) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF9_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b028) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b02c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b02c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF10_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b02c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b030) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b030) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF11_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b030) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF12_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b034) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF13_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b038) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b03c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b03c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF14_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b03c) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009b040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009b040) +#define HWIO_GCC_RPMH_QUPV3_CORE_2X_PERF15_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009b040) +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094004) +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094004) +#define HWIO_GCC_RPMH_CE_PERF0_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094004) +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094008) +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094008) +#define HWIO_GCC_RPMH_CE_PERF1_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094008) +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009400c) +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009400c) +#define HWIO_GCC_RPMH_CE_PERF2_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009400c) +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094010) +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094010) +#define HWIO_GCC_RPMH_CE_PERF3_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094010) +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094014) +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094014) +#define HWIO_GCC_RPMH_CE_PERF4_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094014) +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094018) +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094018) +#define HWIO_GCC_RPMH_CE_PERF5_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094018) +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009401c) +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009401c) +#define HWIO_GCC_RPMH_CE_PERF6_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009401c) +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094020) +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094020) +#define HWIO_GCC_RPMH_CE_PERF7_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094020) +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094024) +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094024) +#define HWIO_GCC_RPMH_CE_PERF8_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094024) +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094028) +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094028) +#define HWIO_GCC_RPMH_CE_PERF9_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094028) +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009402c) +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009402c) +#define HWIO_GCC_RPMH_CE_PERF10_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009402c) +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094030) +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094030) +#define HWIO_GCC_RPMH_CE_PERF11_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094030) +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094034) +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094034) +#define HWIO_GCC_RPMH_CE_PERF12_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094034) +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094038) +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094038) +#define HWIO_GCC_RPMH_CE_PERF13_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094038) +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009403c) +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009403c) +#define HWIO_GCC_RPMH_CE_PERF14_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009403c) +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00094040) +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00094040) +#define HWIO_GCC_RPMH_CE_PERF15_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00094040) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c004) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c004) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF0_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c004) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c008) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c008) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF1_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c008) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c00c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c00c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF2_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c00c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c010) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c010) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF3_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c010) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c014) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c014) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF4_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c014) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c018) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c018) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF5_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c018) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c01c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c01c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF6_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c01c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c020) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c020) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF7_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c020) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c024) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c024) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF8_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c024) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c028) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c028) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF9_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c028) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c02c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c02c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF10_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c02c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c030) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c030) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF11_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c030) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c034) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c034) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF12_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c034) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c038) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c038) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF13_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c038) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c03c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c03c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF14_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c03c) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009c040) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009c040) +#define HWIO_GCC_RPMH_CDSP_NOC_PERF15_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009c040) +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095004) +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095004) +#define HWIO_GCC_RPMH_MMNOC_PERF0_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095004) +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095008) +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095008) +#define HWIO_GCC_RPMH_MMNOC_PERF1_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095008) +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009500c) +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009500c) +#define HWIO_GCC_RPMH_MMNOC_PERF2_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009500c) +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095010) +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095010) +#define HWIO_GCC_RPMH_MMNOC_PERF3_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095010) +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095014) +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095014) +#define HWIO_GCC_RPMH_MMNOC_PERF4_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095014) +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095018) +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095018) +#define HWIO_GCC_RPMH_MMNOC_PERF5_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095018) +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009501c) +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009501c) +#define HWIO_GCC_RPMH_MMNOC_PERF6_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009501c) +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095020) +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095020) +#define HWIO_GCC_RPMH_MMNOC_PERF7_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095020) +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095024) +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095024) +#define HWIO_GCC_RPMH_MMNOC_PERF8_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095024) +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095028) +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095028) +#define HWIO_GCC_RPMH_MMNOC_PERF9_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095028) +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009502c) +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009502c) +#define HWIO_GCC_RPMH_MMNOC_PERF10_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009502c) +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095030) +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095030) +#define HWIO_GCC_RPMH_MMNOC_PERF11_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095030) +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095034) +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095034) +#define HWIO_GCC_RPMH_MMNOC_PERF12_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095034) +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095038) +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095038) +#define HWIO_GCC_RPMH_MMNOC_PERF13_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095038) +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009503c) +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009503c) +#define HWIO_GCC_RPMH_MMNOC_PERF14_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009503c) +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00095040) +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00095040) +#define HWIO_GCC_RPMH_MMNOC_PERF15_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00095040) +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00096004) +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096004) +#define HWIO_GCC_RPMH_SHUB_PERF0_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096004) +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00096008) +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096008) +#define HWIO_GCC_RPMH_SHUB_PERF1_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096008) +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009600c) +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009600c) +#define HWIO_GCC_RPMH_SHUB_PERF2_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009600c) +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00096010) +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096010) +#define HWIO_GCC_RPMH_SHUB_PERF3_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096010) +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00096014) +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096014) +#define HWIO_GCC_RPMH_SHUB_PERF4_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096014) +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00096018) +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096018) +#define HWIO_GCC_RPMH_SHUB_PERF5_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096018) +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009601c) +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009601c) +#define HWIO_GCC_RPMH_SHUB_PERF6_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009601c) +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00096020) +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096020) +#define HWIO_GCC_RPMH_SHUB_PERF7_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096020) +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00096024) +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096024) +#define HWIO_GCC_RPMH_SHUB_PERF8_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096024) +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00096028) +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096028) +#define HWIO_GCC_RPMH_SHUB_PERF9_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096028) +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009602c) +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009602c) +#define HWIO_GCC_RPMH_SHUB_PERF10_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009602c) +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00096030) +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096030) +#define HWIO_GCC_RPMH_SHUB_PERF11_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096030) +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00096034) +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096034) +#define HWIO_GCC_RPMH_SHUB_PERF12_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096034) +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00096038) +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096038) +#define HWIO_GCC_RPMH_SHUB_PERF13_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096038) +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009603c) +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009603c) +#define HWIO_GCC_RPMH_SHUB_PERF14_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009603c) +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00096040) +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00096040) +#define HWIO_GCC_RPMH_SHUB_PERF15_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00096040) +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00097004) +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097004) +#define HWIO_GCC_RPMH_SHRM_PERF0_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097004) +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00097008) +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097008) +#define HWIO_GCC_RPMH_SHRM_PERF1_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097008) +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009700c) +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009700c) +#define HWIO_GCC_RPMH_SHRM_PERF2_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009700c) +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00097010) +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097010) +#define HWIO_GCC_RPMH_SHRM_PERF3_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097010) +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00097014) +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097014) +#define HWIO_GCC_RPMH_SHRM_PERF4_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097014) +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00097018) +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097018) +#define HWIO_GCC_RPMH_SHRM_PERF5_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097018) +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x0009701c) +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009701c) +#define HWIO_GCC_RPMH_SHRM_PERF6_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009701c) +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00097020) +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097020) +#define HWIO_GCC_RPMH_SHRM_PERF7_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097020) +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00097024) +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097024) +#define HWIO_GCC_RPMH_SHRM_PERF8_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097024) +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE + \ + 0x00097028) +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097028) +#define HWIO_GCC_RPMH_SHRM_PERF9_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097028) +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009702c) +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009702c) +#define HWIO_GCC_RPMH_SHRM_PERF10_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009702c) +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00097030) +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097030) +#define HWIO_GCC_RPMH_SHRM_PERF11_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097030) +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00097034) +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097034) +#define HWIO_GCC_RPMH_SHRM_PERF12_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097034) +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00097038) +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097038) +#define HWIO_GCC_RPMH_SHRM_PERF13_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097038) +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009703c) +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009703c) +#define HWIO_GCC_RPMH_SHRM_PERF14_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009703c) +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x00097040) +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00097040) +#define HWIO_GCC_RPMH_SHRM_PERF15_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00097040) +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a004) +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a004) +#define HWIO_GCC_RPMH_DDRMC_PERF0_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a004) +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a008) +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a008) +#define HWIO_GCC_RPMH_DDRMC_PERF1_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a008) +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a00c) +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a00c) +#define HWIO_GCC_RPMH_DDRMC_PERF2_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a00c) +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a010) +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a010) +#define HWIO_GCC_RPMH_DDRMC_PERF3_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a010) +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a014) +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a014) +#define HWIO_GCC_RPMH_DDRMC_PERF4_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a014) +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a018) +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a018) +#define HWIO_GCC_RPMH_DDRMC_PERF5_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a018) +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a01c) +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a01c) +#define HWIO_GCC_RPMH_DDRMC_PERF6_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a01c) +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a020) +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a020) +#define HWIO_GCC_RPMH_DDRMC_PERF7_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a020) +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a024) +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a024) +#define HWIO_GCC_RPMH_DDRMC_PERF8_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a024) +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a028) +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a028) +#define HWIO_GCC_RPMH_DDRMC_PERF9_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a028) +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a02c) +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a02c) +#define HWIO_GCC_RPMH_DDRMC_PERF10_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a02c) +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a030) +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a030) +#define HWIO_GCC_RPMH_DDRMC_PERF11_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a030) +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a034) +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a034) +#define HWIO_GCC_RPMH_DDRMC_PERF12_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a034) +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a038) +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a038) +#define HWIO_GCC_RPMH_DDRMC_PERF13_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a038) +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a03c) +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a03c) +#define HWIO_GCC_RPMH_DDRMC_PERF14_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a03c) +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_ADDR (GCC_CLK_CTL_REG_REG_BASE \ + + 0x0009a040) +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009a040) +#define HWIO_GCC_RPMH_DDRMC_PERF15_ENA_VOTE_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009a040) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098004) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098004) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098004) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098008) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098008) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098008) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009800c) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009800c) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009800c) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098010) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098010) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098010) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098014) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098014) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098014) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098018) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098018) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098018) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009801c) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009801c) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009801c) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098020) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098020) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098020) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098024) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098024) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098024) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098028) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098028) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098028) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009802c) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009802c) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009802c) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098030) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098030) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098030) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098034) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098034) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098034) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098038) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098038) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098038) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009803c) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009803c) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009803c) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00098040) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00098040) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_L_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00098040) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099004) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099004) +#define HWIO_GCC_RPMH_DDRMC_PERF0_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099004) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099008) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099008) +#define HWIO_GCC_RPMH_DDRMC_PERF1_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099008) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009900c) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009900c) +#define HWIO_GCC_RPMH_DDRMC_PERF2_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009900c) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099010) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099010) +#define HWIO_GCC_RPMH_DDRMC_PERF3_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099010) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099014) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099014) +#define HWIO_GCC_RPMH_DDRMC_PERF4_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099014) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099018) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099018) +#define HWIO_GCC_RPMH_DDRMC_PERF5_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099018) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009901c) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009901c) +#define HWIO_GCC_RPMH_DDRMC_PERF6_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009901c) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099020) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099020) +#define HWIO_GCC_RPMH_DDRMC_PERF7_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099020) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099024) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099024) +#define HWIO_GCC_RPMH_DDRMC_PERF8_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099024) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099028) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099028) +#define HWIO_GCC_RPMH_DDRMC_PERF9_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099028) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009902c) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009902c) +#define HWIO_GCC_RPMH_DDRMC_PERF10_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009902c) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099030) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099030) +#define HWIO_GCC_RPMH_DDRMC_PERF11_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099030) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099034) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099034) +#define HWIO_GCC_RPMH_DDRMC_PERF12_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099034) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099038) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099038) +#define HWIO_GCC_RPMH_DDRMC_PERF13_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099038) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x0009903c) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x0009903c) +#define HWIO_GCC_RPMH_DDRMC_PERF14_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x0009903c) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099040) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099040) +#define HWIO_GCC_RPMH_DDRMC_PERF15_GPLL2_3_FRAC_VAL_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099040) +#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00099080) +#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00099080) +#define HWIO_GCC_RPMH_DDRMC_FAKE_SWITCH_DEBUG_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00099080) +#define HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_ADDR ( \ + GCC_CLK_CTL_REG_REG_BASE + 0x00044530) +#define HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_PHYS ( \ + GCC_CLK_CTL_REG_REG_BASE_PHYS + 0x00044530) +#define HWIO_GCC_RPMH_DDRMC_CLOCK_SWITCH_MISC_OFFS ( \ + GCC_CLK_CTL_REG_REG_BASE_OFFS + 0x00044530) +#define HWIO_GCC_EMAC_MISC_ADDR (GCC_CLK_CTL_REG_REG_BASE + 0x00006040) +#define HWIO_GCC_EMAC_MISC_PHYS (GCC_CLK_CTL_REG_REG_BASE_PHYS + \ + 0x00006040) +#define HWIO_GCC_EMAC_MISC_OFFS (GCC_CLK_CTL_REG_REG_BASE_OFFS + \ + 0x00006040) +#endif diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_gcc_hwio_def.h b/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_gcc_hwio_def.h new file mode 100644 index 000000000000..e3fafc762c71 --- /dev/null +++ b/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_gcc_hwio_def.h @@ -0,0 +1,29 @@ +/* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#if !defined(_IPA_GCC_HWIO_DEF_H_) +#define _IPA_GCC_HWIO_DEF_H_ + +/* ***************************************************************************** + * + * HWIO register definitions + * + * ***************************************************************************** + */ +struct ipa_gcc_hwio_def_gcc_ipa_bcr_s { + u32 blk_ares : 1; + u32 reserved0 : 31; +}; +union ipa_gcc_hwio_def_gcc_ipa_bcr_u { + struct ipa_gcc_hwio_def_gcc_ipa_bcr_s def; + u32 value; +}; +#endif diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_hw_common_ex.h b/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_hw_common_ex.h new file mode 100644 index 000000000000..5012a32b2a5a --- /dev/null +++ b/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_hw_common_ex.h @@ -0,0 +1,610 @@ +/* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#if !defined(_IPA_HW_COMMON_EX_H_) +#define _IPA_HW_COMMON_EX_H_ + +/* VLVL defs are available for 854 */ +#define FEATURE_VLVL_DEFS true + +/* IPAv4 version flag for Sdx24 */ +#define FEATURE_IPA_HW_VERSION_4_0 true + +/* Important Platform Specific Values : IRQ_NUM, IRQ_CNT, BCR */ +#define IPA_HW_BAM_IRQ_NUM 440 + +/* Q6 IRQ number for IPA. Fetched from IPCatalog */ +#define IPA_HW_IRQ_NUM 441 + +/* Total number of different interrupts that can be enabled */ +#define IPA_HW_IRQ_CNT_TOTAL 23 + +/* IPAv4 BCR value */ +#define IPA_HW_BCR_REG_VAL 0x00000039 + +/* IPAv4 spare reg value */ +#define IPA_HW_SPARE_1_REG_VAL 0xC0000005 + +/* Whether to allow setting step mode on IPA when we crash or not */ +#define IPA_CFG_HW_IS_STEP_MODE_ALLOWED (false) + +/* GSI MHI related definitions */ +#define IPA_HW_GSI_MHI_CONSUMER_CHANNEL_NUM 0x0 +#define IPA_HW_GSI_MHI_PRODUCER_CHANNEL_NUM 0x1 + +#define IPA_HW_GSI_MHI_CONSUMER_EP_NUM 0x1 +#define IPA_HW_GSI_MHI_PRODUCER_EP_NUM 0x11 + +/* IPA ZIP WA related Macros */ +#define IPA_HW_DCMP_SRC_PIPE 0x8 +#define IPA_HW_DCMP_DEST_PIPE 0x4 +#define IPA_HW_ACK_MNGR_MASK 0x1D +#define IPA_HW_DCMP_SRC_GRP 0x5 + +/* IPA Clock resource name */ +#define IPA_CLK_RESOURCE_NAME "/clk/pcnoc" + +/* IPA Clock Bus Client name */ +#define IPA_CLK_BUS_CLIENT_NAME "IPA_PCNOC_BUS_CLIENT" + +/* HPS Sequences */ +#define IPA_HW_PKT_PROCESS_HPS_DMA 0x0 +#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_DECIPH_UCP 0x3 +#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_NO_DECIPH 0x4 +#define IPA_HW_PKT_PROCESS_HPS_2_PKT_PRS_DECIPH 0x5 +#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_NO_DECIPH_NO_UCP 0x6 +#define IPA_HW_PKT_PROCESS_HPS_PKT_PRS_DECIPH_NO_UCP 0x7 +#define IPA_HW_PKT_PROCESS_HPS_DMA_PARSER 0x8 +#define IPA_HW_PKT_PROCESS_HPS_DMA_DECIPH_PARSER 0x9 + +/* DPS Sequences */ +#define IPA_HW_PKT_PROCESS_DPS_DMA 0x0 +#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_DECIPH 0x1 +#define IPA_HW_PKT_PROCESS_DPS_DMA_WITH_DECOMP 0x2 + +/* Src RSRC GRP config */ +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_0 0x05050404 +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_1 0x0A0A0A0A +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_2 0x0C0C0C0C +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_3 0x3F003F00 +#define IPA_HW_SRC_RSRC_GRP_01_RSRC_TYPE_4 0x0E0E0E0E + +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_0 0x00000101 +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_1 0x00000808 +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_2 0x00000808 +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_3 0x3F003F00 +#define IPA_HW_SRC_RSRC_GRP_23_RSRC_TYPE_4 0x00000E0E + +/* Dest RSRC GRP config */ +#define IPA_HW_DST_RSRC_GRP_01_RSRC_TYPE_0 0x04040404 +#define IPA_HW_DST_RSRC_GRP_01_RSRC_TYPE_1 0x3F013F02 + +#define IPA_HW_DST_RSRC_GRP_23_RSRC_TYPE_0 0x02020303 +#define IPA_HW_DST_RSRC_GRP_23_RSRC_TYPE_1 0x02000201 + + +#define IPA_HW_RX_HPS_CLIENTS_MIN_DEPTH_0 0x00020703 +#define IPA_HW_RX_HPS_CLIENTS_MAX_DEPTH_0 0x00020703 + +#define IPA_HW_RSRP_GRP_0 0x0 +#define IPA_HW_RSRP_GRP_1 0x1 +#define IPA_HW_RSRP_GRP_2 0x2 +#define IPA_HW_RSRP_GRP_3 0x3 + +#define IPA_HW_PCIE_SRC_RSRP_GRP IPA_HW_RSRP_GRP_0 +#define IPA_HW_PCIE_DEST_RSRP_GRP IPA_HW_RSRP_GRP_0 + +#define IPA_HW_DDR_SRC_RSRP_GRP IPA_HW_RSRP_GRP_1 +#define IPA_HW_DDR_DEST_RSRP_GRP IPA_HW_RSRP_GRP_1 + +#define IPA_HW_SRC_RSRP_TYPE_MAX 0x5 +#define IPA_HW_DST_RSRP_TYPE_MAX 0x2 + +#define GSI_HW_QSB_LOG_MISC_MAX 0x4 + +/* IPA Clock Bus Client name */ +#define IPA_CLK_BUS_CLIENT_NAME "IPA_PCNOC_BUS_CLIENT" + +/* Is IPA decompression feature enabled */ +#define IPA_HW_IS_DECOMPRESSION_ENABLED (1) + +/* Whether to allow setting step mode on IPA when we crash or not */ +#define IPA_HW_IS_STEP_MODE_ALLOWED (true) + +/* + * HW specific clock vote freq values in KHz + * (BIMC/SNOC/PCNOC/IPA/Q6 CPU) + */ +enum ipa_hw_clk_freq_e { + /* BIMC */ + IPA_HW_CLK_FREQ_BIMC_PEAK = 518400, + IPA_HW_CLK_FREQ_BIMC_NOM_PLUS = 404200, + IPA_HW_CLK_FREQ_BIMC_NOM = 404200, + IPA_HW_CLK_FREQ_BIMC_SVS = 100000, + + /* PCNOC */ + IPA_HW_CLK_FREQ_PCNOC_PEAK = 133330, + IPA_HW_CLK_FREQ_PCNOC_NOM_PLUS = 100000, + IPA_HW_CLK_FREQ_PCNOC_NOM = 100000, + IPA_HW_CLK_FREQ_PCNOC_SVS = 50000, + + /*IPA_HW_CLK_SNOC*/ + IPA_HW_CLK_FREQ_SNOC_PEAK = 200000, + IPA_HW_CLK_FREQ_SNOC_NOM_PLUS = 150000, + IPA_HW_CLK_FREQ_SNOC_NOM = 150000, + IPA_HW_CLK_FREQ_SNOC_SVS = 85000, + IPA_HW_CLK_FREQ_SNOC_SVS_2 = 50000, + + /* IPA */ + IPA_HW_CLK_FREQ_IPA_PEAK = 500000, + IPA_HW_CLK_FREQ_IPA_NOM_PLUS = 440000, + IPA_HW_CLK_FREQ_IPA_NOM = 440000, + IPA_HW_CLK_FREQ_IPA_SVS = 250000, + IPA_HW_CLK_FREQ_IPA_SVS_2 = 120000, + + /* Q6 CPU */ + IPA_HW_CLK_FREQ_Q6_PEAK = 729600, + IPA_HW_CLK_FREQ_Q6_NOM_PLUS = 729600, + IPA_HW_CLK_FREQ_Q6_NOM = 729600, + IPA_HW_CLK_FREQ_Q6_SVS = 729600, +}; + +/* Pipe ID of all the IPA pipes */ +enum ipa_hw_pipe_id_e { + IPA_HW_PIPE_ID_0, + IPA_HW_PIPE_ID_1, + IPA_HW_PIPE_ID_2, + IPA_HW_PIPE_ID_3, + IPA_HW_PIPE_ID_4, + IPA_HW_PIPE_ID_5, + IPA_HW_PIPE_ID_6, + IPA_HW_PIPE_ID_7, + IPA_HW_PIPE_ID_8, + IPA_HW_PIPE_ID_9, + IPA_HW_PIPE_ID_10, + IPA_HW_PIPE_ID_11, + IPA_HW_PIPE_ID_12, + IPA_HW_PIPE_ID_13, + IPA_HW_PIPE_ID_14, + IPA_HW_PIPE_ID_15, + IPA_HW_PIPE_ID_16, + IPA_HW_PIPE_ID_17, + IPA_HW_PIPE_ID_18, + IPA_HW_PIPE_ID_19, + IPA_HW_PIPE_ID_20, + IPA_HW_PIPE_ID_21, + IPA_HW_PIPE_ID_22, + IPA_HW_PIPE_ID_MAX +}; + +/* Pipe ID's of System Bam Endpoints between Q6 & IPA */ +enum ipa_hw_q6_pipe_id_e { + /* Pipes used by IPA Q6 driver */ + IPA_HW_Q6_DL_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_3, + IPA_HW_Q6_CTL_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_4, + IPA_HW_Q6_UL_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_13, + IPA_HW_Q6_DL_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_14, + + IPA_HW_Q6_LTE_DL_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_6, + IPA_HW_Q6_LWA_DL_PRODUCER_PIPE_ID = IPA_HW_PIPE_ID_16, + /* Test Simulator Pipes */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0_ID = IPA_HW_PIPE_ID_0, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_ID = IPA_HW_PIPE_ID_12, + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1_ID = IPA_HW_PIPE_ID_1, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_ID = IPA_HW_PIPE_ID_10, + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2_ID = IPA_HW_PIPE_ID_2, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_ID = IPA_HW_PIPE_ID_11, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1_ID = IPA_HW_PIPE_ID_5, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1_ID = IPA_HW_PIPE_ID_17, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2_ID = IPA_HW_PIPE_ID_7, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2_ID = IPA_HW_PIPE_ID_18, + IPA_HW_Q6_DIAG_CONSUMER_PIPE_ID = IPA_HW_PIPE_ID_19, + IPA_HW_Q6_PIPE_ID_MAX = IPA_HW_PIPE_ID_MAX, +}; + +enum ipa_hw_q6_pipe_ch_id_e { + /* Channels used by IPA Q6 driver */ + IPA_HW_Q6_DL_CONSUMER_PIPE_CH_ID = 0, + IPA_HW_Q6_CTL_CONSUMER_PIPE_CH_ID = 1, + IPA_HW_Q6_UL_PRODUCER_PIPE_CH_ID = 3, + IPA_HW_Q6_DL_PRODUCER_PIPE_CH_ID = 4, + + IPA_HW_Q6_LTE_DL_CONSUMER_PIPE_CH_ID = 2, + IPA_HW_Q6_LWA_DL_PRODUCER_PIPE_CH_ID = 5, + /* Test Simulator Channels */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0_CH_ID = 6, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_CH_ID = 8, + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1_CH_ID = 9, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_CH_ID = 10, + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2_CH_ID = 11, + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_CH_ID = 12, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1_CH_ID = 13, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1_CH_ID = 14, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2_CH_ID = 15, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2_CH_ID = 16, +}; + +/* System Bam Endpoints between Q6 & IPA */ +enum ipa_hw_q6_pipe_e { + /* DL Pipe IPA->Q6 */ + IPA_HW_Q6_DL_PRODUCER_PIPE = 0, + /* UL Pipe IPA->Q6 */ + IPA_HW_Q6_UL_PRODUCER_PIPE = 1, + /* DL Pipe Q6->IPA */ + IPA_HW_Q6_DL_CONSUMER_PIPE = 2, + /* CTL Pipe Q6->IPA */ + IPA_HW_Q6_CTL_CONSUMER_PIPE = 3, + /* Q6 -> IPA, LTE DL Optimized path */ + IPA_HW_Q6_LTE_DL_CONSUMER_PIPE = 4, + /* LWA DL(Wifi to Q6) */ + IPA_HW_Q6_LWA_DL_PRODUCER_PIPE = 5, + /* Diag status pipe IPA->Q6 */ + /* Used only when FEATURE_IPA_TEST_PER_SIM is ON */ + /* SIM Pipe IPA->Sim */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0 = 7, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1 = 8, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2 = 9, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_0 = 10, + /* SIM B2B PROD Pipe */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_1 = 11, + /* SIM Pipe IPA->Sim */ + IPA_HW_Q6_SIM_UL_CONSUMER_PIPE_2 = 12, + /* End FEATURE_IPA_TEST_PER_SIM */ + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_1 = 13, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_1 = 14, + /* GSI UT channel SW->IPA */ + IPA_HW_Q6_GSI_UT_CONSUMER_PIPE_2 = 15, + /* GSI UT channel IPA->SW */ + IPA_HW_Q6_GSI_UT_PRODUCER_PIPE_2 = 16, + IPA_HW_Q6_PIPE_TOTAL +}; + +/* System Bam Endpoints between Q6 & IPA */ +enum ipa_hw_q6_gsi_ev_e { /* In Sdx24 0..11 */ + /* DL Pipe IPA->Q6 */ + IPA_HW_Q6_DL_PRODUCER_PIPE_GSI_EV = 0, + /* UL Pipe IPA->Q6 */ + IPA_HW_Q6_UL_PRODUCER_PIPE_GSI_EV = 1, + /* DL Pipe Q6->IPA */ + //IPA_HW_Q6_DL_CONSUMER_PIPE_GSI_EV = 2, + /* CTL Pipe Q6->IPA */ + //IPA_HW_Q6_CTL_CONSUMER_PIPE_GSI_EV = 3, + /* Q6 -> IPA, LTE DL Optimized path */ + //IPA_HW_Q6_LTE_DL_CONSUMER_PIPE_GSI_EV = 4, + /* LWA DL(Wifi to Q6) */ + //IPA_HW_Q6_LWA_DL_PRODUCER_PIPE_GSI_EV = 5, + /* Diag status pipe IPA->Q6 */ + //IPA_HW_Q6_DIAG_STATUS_PRODUCER_PIPE_GSI_EV = 6, + /* Used only when FEATURE_IPA_TEST_PER_SIM is ON */ + /* SIM Pipe IPA->Sim */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_0_GSI_EV = 2, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_1_GSI_EV = 3, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_DL_PRODUCER_PIPE_2_GSI_EV = 4, + /* SIM Pipe Sim->IPA */ + IPA_HW_Q6_SIM_1_GSI_EV = 5, + IPA_HW_Q6_SIM_2_GSI_EV = 6, + IPA_HW_Q6_SIM_3_GSI_EV = 7, + IPA_HW_Q6_SIM_4_GSI_EV = 8, + + IPA_HW_Q6_PIPE_GSI_EV_TOTAL +}; + +/* + * All the IRQ's supported by the IPA HW. Use this enum to set IRQ_EN + * register and read IRQ_STTS register + */ +enum ipa_hw_irq_e { + IPA_HW_IRQ_GSI_HWP = (1 << 25), + IPA_HW_IRQ_GSI_IPA_IF_TLV_RCVD = (1 << 24), + IPA_HW_IRQ_GSI_EE_IRQ = (1 << 23), + IPA_HW_IRQ_DCMP_ERR = (1 << 22), + IPA_HW_IRQ_HWP_ERR = (1 << 21), + IPA_HW_IRQ_RED_MARKER_ABOVE = (1 << 20), + IPA_HW_IRQ_YELLOW_MARKER_ABOVE = (1 << 19), + IPA_HW_IRQ_RED_MARKER_BELOW = (1 << 18), + IPA_HW_IRQ_YELLOW_MARKER_BELOW = (1 << 17), + IPA_HW_IRQ_BAM_IDLE_IRQ = (1 << 16), + IPA_HW_IRQ_TX_HOLB_DROP = (1 << 15), + IPA_HW_IRQ_TX_SUSPEND = (1 << 14), + IPA_HW_IRQ_PROC_ERR = (1 << 13), + IPA_HW_IRQ_STEP_MODE = (1 << 12), + IPA_HW_IRQ_TX_ERR = (1 << 11), + IPA_HW_IRQ_DEAGGR_ERR = (1 << 10), + IPA_HW_IRQ_RX_ERR = (1 << 9), + IPA_HW_IRQ_PROC_TO_HW_ACK_Q_NOT_EMPTY = (1 << 8), + IPA_HW_IRQ_HWP_RX_CMD_Q_NOT_FULL = (1 << 7), + IPA_HW_IRQ_HWP_IN_Q_NOT_EMPTY = (1 << 6), + IPA_HW_IRQ_HWP_IRQ_3 = (1 << 5), + IPA_HW_IRQ_HWP_IRQ_2 = (1 << 4), + IPA_HW_IRQ_HWP_IRQ_1 = (1 << 3), + IPA_HW_IRQ_HWP_IRQ_0 = (1 << 2), + IPA_HW_IRQ_EOT_COAL = (1 << 1), + IPA_HW_IRQ_BAD_SNOC_ACCESS = (1 << 0), + IPA_HW_IRQ_NONE = 0, + IPA_HW_IRQ_ALL = 0xFFFFFFFF +}; + +/* + * All the IRQ sources supported by the IPA HW. Use this enum to set + * IRQ_SRCS register + */ +enum ipa_hw_irq_srcs_e { + IPA_HW_IRQ_SRCS_PIPE_0 = (1 << IPA_HW_PIPE_ID_0), + IPA_HW_IRQ_SRCS_PIPE_1 = (1 << IPA_HW_PIPE_ID_1), + IPA_HW_IRQ_SRCS_PIPE_2 = (1 << IPA_HW_PIPE_ID_2), + IPA_HW_IRQ_SRCS_PIPE_3 = (1 << IPA_HW_PIPE_ID_3), + IPA_HW_IRQ_SRCS_PIPE_4 = (1 << IPA_HW_PIPE_ID_4), + IPA_HW_IRQ_SRCS_PIPE_5 = (1 << IPA_HW_PIPE_ID_5), + IPA_HW_IRQ_SRCS_PIPE_6 = (1 << IPA_HW_PIPE_ID_6), + IPA_HW_IRQ_SRCS_PIPE_7 = (1 << IPA_HW_PIPE_ID_7), + IPA_HW_IRQ_SRCS_PIPE_8 = (1 << IPA_HW_PIPE_ID_8), + IPA_HW_IRQ_SRCS_PIPE_9 = (1 << IPA_HW_PIPE_ID_9), + IPA_HW_IRQ_SRCS_PIPE_10 = (1 << IPA_HW_PIPE_ID_10), + IPA_HW_IRQ_SRCS_PIPE_11 = (1 << IPA_HW_PIPE_ID_11), + IPA_HW_IRQ_SRCS_PIPE_12 = (1 << IPA_HW_PIPE_ID_12), + IPA_HW_IRQ_SRCS_PIPE_13 = (1 << IPA_HW_PIPE_ID_13), + IPA_HW_IRQ_SRCS_PIPE_14 = (1 << IPA_HW_PIPE_ID_14), + IPA_HW_IRQ_SRCS_PIPE_15 = (1 << IPA_HW_PIPE_ID_15), + IPA_HW_IRQ_SRCS_PIPE_16 = (1 << IPA_HW_PIPE_ID_16), + IPA_HW_IRQ_SRCS_PIPE_17 = (1 << IPA_HW_PIPE_ID_17), + IPA_HW_IRQ_SRCS_PIPE_18 = (1 << IPA_HW_PIPE_ID_18), + IPA_HW_IRQ_SRCS_PIPE_19 = (1 << IPA_HW_PIPE_ID_19), + IPA_HW_IRQ_SRCS_PIPE_20 = (1 << IPA_HW_PIPE_ID_20), + IPA_HW_IRQ_SRCS_PIPE_21 = (1 << IPA_HW_PIPE_ID_21), + IPA_HW_IRQ_SRCS_PIPE_22 = (1 << IPA_HW_PIPE_ID_22), + IPA_HW_IRQ_SRCS_NONE = 0, + IPA_HW_IRQ_SRCS_ALL = 0xFFFFFFFF, +}; + +/* + * Total number of channel contexts that need to be saved for APPS + */ +#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7 15 + +/* + * Total number of channel contexts that need to be saved for UC + */ +#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC 5 + +/* + * Total number of event ring contexts that need to be saved for APPS + */ +#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7 12 + +/* + * Total number of event ring contexts that need to be saved for UC + */ +#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_UC 4 + +/* + * Total number of endpoints for which ipa_reg_save.pipes[endp_number] + * are not saved by default (only if ipa_cfg.gen.full_reg_trace = + * true) There is no extra endpoints in Stingray + */ +#define IPA_HW_REG_SAVE_NUM_ENDP_EXTRA 0 + +/* + * Total number of endpoints for which ipa_reg_save.pipes[endp_number] + * are always saved + */ +#define IPA_HW_REG_SAVE_NUM_ACTIVE_PIPES 23 + +/* + * Macro to set the active flag for all active pipe indexed register + */ +#define IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_ACTIVE() \ + do { \ + ipa_reg_save.ipa.pipes[0].active = true; \ + ipa_reg_save.ipa.pipes[1].active = true; \ + ipa_reg_save.ipa.pipes[2].active = true; \ + ipa_reg_save.ipa.pipes[3].active = true; \ + ipa_reg_save.ipa.pipes[4].active = true; \ + ipa_reg_save.ipa.pipes[5].active = true; \ + ipa_reg_save.ipa.pipes[6].active = true; \ + ipa_reg_save.ipa.pipes[7].active = true; \ + ipa_reg_save.ipa.pipes[8].active = true; \ + ipa_reg_save.ipa.pipes[9].active = true; \ + ipa_reg_save.ipa.pipes[10].active = true; \ + ipa_reg_save.ipa.pipes[11].active = true; \ + ipa_reg_save.ipa.pipes[12].active = true; \ + ipa_reg_save.ipa.pipes[13].active = true; \ + ipa_reg_save.ipa.pipes[14].active = true; \ + ipa_reg_save.ipa.pipes[15].active = true; \ + ipa_reg_save.ipa.pipes[16].active = true; \ + ipa_reg_save.ipa.pipes[17].active = true; \ + ipa_reg_save.ipa.pipes[18].active = true; \ + ipa_reg_save.ipa.pipes[19].active = true; \ + ipa_reg_save.ipa.pipes[20].active = true; \ + ipa_reg_save.ipa.pipes[21].active = true; \ + ipa_reg_save.ipa.pipes[22].active = true; \ + } while (0) + +/* + * Macro to define a particular register cfg entry for the remaining + * pipe indexed register. In Stingray case we don't have extra + * endpoints so it is intentially empty + */ +#define IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA(REG_NAME, VAR_NAME) \ + { 0, 0 } + +/* + * Macro to set the active flag for all active pipe indexed register + * In Stingray case we don't have extra endpoints so it is intentially + * empty + */ +#define IPA_HW_REG_SAVE_CFG_ENTRY_PIPE_ENDP_EXTRA_ACTIVE() \ + do { \ + } while (0) + +#define IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \ + (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_A7_EE].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \ + (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_Q6_EE].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE), \ + (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_REG_SAVE_HWP_GSI_EE].var_name } + +/* + * Macro to define a particular register cfg entry for all GSI EE + * register + */ +#define IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(reg_name, var_name) \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[0].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[1].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[2].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[3].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[4].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[5].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[6].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[7].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[8].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[9].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[10].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[11].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[12].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[13].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[14].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[0].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[2].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[3].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[4].var_name } + +#define IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(reg_name, var_name) \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[0].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[1].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[2].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[3].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[4].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[5].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[6].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[7].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[8].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[9].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[10].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[11].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[1].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[2].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[3].var_name } + +/* + * Macro to define a particular register cfg entry for all pipe + * indexed register + */ +#define IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + (u32 *)&ipa_reg_save.ipa.pipes[0].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ + (u32 *)&ipa_reg_save.ipa.pipes[1].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ + (u32 *)&ipa_reg_save.ipa.pipes[2].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ + (u32 *)&ipa_reg_save.ipa.pipes[3].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ + (u32 *)&ipa_reg_save.ipa.pipes[4].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 5), \ + (u32 *)&ipa_reg_save.ipa.pipes[5].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 6), \ + (u32 *)&ipa_reg_save.ipa.pipes[6].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 7), \ + (u32 *)&ipa_reg_save.ipa.pipes[7].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 8), \ + (u32 *)&ipa_reg_save.ipa.pipes[8].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 9), \ + (u32 *)&ipa_reg_save.ipa.pipes[9].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 10), \ + (u32 *)&ipa_reg_save.ipa.pipes[10].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 11), \ + (u32 *)&ipa_reg_save.ipa.pipes[11].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 12), \ + (u32 *)&ipa_reg_save.ipa.pipes[12].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 13), \ + (u32 *)&ipa_reg_save.ipa.pipes[13].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 14), \ + (u32 *)&ipa_reg_save.ipa.pipes[14].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 15), \ + (u32 *)&ipa_reg_save.ipa.pipes[15].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 16), \ + (u32 *)&ipa_reg_save.ipa.pipes[16].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 17), \ + (u32 *)&ipa_reg_save.ipa.pipes[17].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 18), \ + (u32 *)&ipa_reg_save.ipa.pipes[18].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 19), \ + (u32 *)&ipa_reg_save.ipa.pipes[19].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 20), \ + (u32 *)&ipa_reg_save.ipa.pipes[20].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 21), \ + (u32 *)&ipa_reg_save.ipa.pipes[21].endp.var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, 22), \ + (u32 *)&ipa_reg_save.ipa.pipes[22].endp.var_name } + + +#define IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM 8 +/* + * Total number of rx splt cmdq's see: + * ipa_rx_splt_cmdq_n_cmd[IPA_RX_SPLT_CMDQ_MAX] + */ +#define IPA_RX_SPLT_CMDQ_MAX 3 + +#endif /* #if !defined(_IPA_HW_COMMON_EX_H_) */ diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_hwio.h b/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_hwio.h new file mode 100644 index 000000000000..b253349496b8 --- /dev/null +++ b/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_hwio.h @@ -0,0 +1,10293 @@ +/* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#if !defined(_IPA_HWIO_H_) +#define _IPA_HWIO_H_ + +/* ***************************************************************************** + * + * HWIO register definitions + * + * ***************************************************************************** + */ +#define IPA_GSI_TOP_GSI_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00004000) +#define IPA_GSI_TOP_GSI_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + \ + 0x00004000) +#define IPA_GSI_TOP_GSI_REG_BASE_OFFS 0x00004000 +#define HWIO_IPA_GSI_TOP_GSI_CFG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000000) +#define HWIO_IPA_GSI_TOP_GSI_CFG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + \ + 0x00000000) +#define HWIO_IPA_GSI_TOP_GSI_CFG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + \ + 0x00000000) +#define HWIO_IPA_GSI_TOP_GSI_CFG_RMSK 0x3f +#define HWIO_IPA_GSI_TOP_GSI_CFG_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_CFG_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_CFG_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_CFG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_CFG_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_CFG_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_CFG_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_CFG_IN) +#define HWIO_IPA_GSI_TOP_GSI_CFG_BP_MTRIX_DISABLE_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_GSI_CFG_BP_MTRIX_DISABLE_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_GSI_CFG_GSI_PWR_CLPS_BMSK 0x10 +#define HWIO_IPA_GSI_TOP_GSI_CFG_GSI_PWR_CLPS_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_GSI_CFG_UC_IS_MCS_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_GSI_CFG_UC_IS_MCS_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_GSI_CFG_DOUBLE_MCS_CLK_FREQ_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_GSI_CFG_DOUBLE_MCS_CLK_FREQ_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_GSI_CFG_MCS_ENABLE_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_GSI_CFG_MCS_ENABLE_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_GSI_CFG_GSI_ENABLE_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_CFG_GSI_ENABLE_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000008) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000008) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_MCS_CODE_VER_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000008) +#define HWIO_IPA_GSI_TOP_GSI_ZEROS_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000010) +#define HWIO_IPA_GSI_TOP_GSI_ZEROS_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + \ + 0x00000010) +#define HWIO_IPA_GSI_TOP_GSI_ZEROS_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + \ + 0x00000010) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000018) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000018) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000018) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000001c) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000001c) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_BASE_ADDR_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000001c) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000020) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000020) +#define HWIO_IPA_GSI_TOP_GSI_PERIPH_PENDING_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000020) +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000030) +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS \ + + 0x00000030) +#define HWIO_IPA_GSI_TOP_GSI_MOQA_CFG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS \ + + 0x00000030) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000038) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + \ + 0x00000038) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + \ + 0x00000038) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_RMSK 0xff01 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_REE_CFG_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_REE_CFG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_REE_CFG_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_REE_CFG_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_REE_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_REE_CFG_IN) +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_MAX_BURST_SIZE_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_MAX_BURST_SIZE_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_MOVE_TO_ESC_CLR_MODE_TRSH_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_REE_CFG_MOVE_TO_ESC_CLR_MODE_TRSH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_WR_WRR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000050) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_WR_WRR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000050) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_WR_WRR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000050) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_RD_WRR_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000058) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_RD_WRR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000058) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_RD_WRR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000058) +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000060) +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS \ + + 0x00000060) +#define HWIO_IPA_GSI_TOP_GSI_CGC_CTRL_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS \ + + 0x00000060) +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000080) +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000080) +#define HWIO_IPA_GSI_TOP_GSI_MSI_CACHEATTR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000080) +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000084) +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000084) +#define HWIO_IPA_GSI_TOP_GSI_EVENT_CACHEATTR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000084) +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000088) +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000088) +#define HWIO_IPA_GSI_TOP_GSI_DATA_CACHEATTR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000088) +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000090) +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000090) +#define HWIO_IPA_GSI_TOP_GSI_TRE_CACHEATTR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000090) +#define HWIO_IPA_GSI_TOP_IC_DISABLE_CHNL_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000a0) +#define HWIO_IPA_GSI_TOP_IC_DISABLE_CHNL_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000a0) +#define HWIO_IPA_GSI_TOP_IC_DISABLE_CHNL_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000a0) +#define HWIO_IPA_GSI_TOP_IC_DISABLE_CHNL_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000a4) +#define HWIO_IPA_GSI_TOP_IC_DISABLE_CHNL_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000a4) +#define HWIO_IPA_GSI_TOP_IC_DISABLE_CHNL_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000a4) +#define HWIO_IPA_GSI_TOP_IC_GEN_EVNT_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000a8) +#define HWIO_IPA_GSI_TOP_IC_GEN_EVNT_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000a8) +#define HWIO_IPA_GSI_TOP_IC_GEN_EVNT_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000a8) +#define HWIO_IPA_GSI_TOP_IC_GEN_EVNT_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000ac) +#define HWIO_IPA_GSI_TOP_IC_GEN_EVNT_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000ac) +#define HWIO_IPA_GSI_TOP_IC_GEN_EVNT_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000ac) +#define HWIO_IPA_GSI_TOP_IC_GEN_INT_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000b0) +#define HWIO_IPA_GSI_TOP_IC_GEN_INT_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000b0) +#define HWIO_IPA_GSI_TOP_IC_GEN_INT_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000b0) +#define HWIO_IPA_GSI_TOP_IC_GEN_INT_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000b4) +#define HWIO_IPA_GSI_TOP_IC_GEN_INT_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000b4) +#define HWIO_IPA_GSI_TOP_IC_GEN_INT_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000b4) +#define HWIO_IPA_GSI_TOP_IC_STOP_INT_MOD_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000b8) +#define HWIO_IPA_GSI_TOP_IC_STOP_INT_MOD_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000b8) +#define HWIO_IPA_GSI_TOP_IC_STOP_INT_MOD_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000b8) +#define HWIO_IPA_GSI_TOP_IC_STOP_INT_MOD_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000bc) +#define HWIO_IPA_GSI_TOP_IC_STOP_INT_MOD_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000bc) +#define HWIO_IPA_GSI_TOP_IC_STOP_INT_MOD_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000bc) +#define HWIO_IPA_GSI_TOP_IC_PROCESS_DESC_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000c0) +#define HWIO_IPA_GSI_TOP_IC_PROCESS_DESC_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000c0) +#define HWIO_IPA_GSI_TOP_IC_PROCESS_DESC_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000c0) +#define HWIO_IPA_GSI_TOP_IC_PROCESS_DESC_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000c4) +#define HWIO_IPA_GSI_TOP_IC_PROCESS_DESC_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000c4) +#define HWIO_IPA_GSI_TOP_IC_PROCESS_DESC_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000c4) +#define HWIO_IPA_GSI_TOP_IC_TLV_STOP_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000c8) +#define HWIO_IPA_GSI_TOP_IC_TLV_STOP_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000c8) +#define HWIO_IPA_GSI_TOP_IC_TLV_STOP_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000c8) +#define HWIO_IPA_GSI_TOP_IC_TLV_STOP_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000cc) +#define HWIO_IPA_GSI_TOP_IC_TLV_STOP_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000cc) +#define HWIO_IPA_GSI_TOP_IC_TLV_STOP_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000cc) +#define HWIO_IPA_GSI_TOP_IC_TLV_RESET_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000d0) +#define HWIO_IPA_GSI_TOP_IC_TLV_RESET_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000d0) +#define HWIO_IPA_GSI_TOP_IC_TLV_RESET_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000d0) +#define HWIO_IPA_GSI_TOP_IC_TLV_RESET_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000d4) +#define HWIO_IPA_GSI_TOP_IC_TLV_RESET_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000d4) +#define HWIO_IPA_GSI_TOP_IC_TLV_RESET_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000d4) +#define HWIO_IPA_GSI_TOP_IC_RGSTR_TIMER_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000d8) +#define HWIO_IPA_GSI_TOP_IC_RGSTR_TIMER_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000d8) +#define HWIO_IPA_GSI_TOP_IC_RGSTR_TIMER_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000d8) +#define HWIO_IPA_GSI_TOP_IC_RGSTR_TIMER_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000dc) +#define HWIO_IPA_GSI_TOP_IC_RGSTR_TIMER_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000dc) +#define HWIO_IPA_GSI_TOP_IC_RGSTR_TIMER_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000dc) +#define HWIO_IPA_GSI_TOP_IC_READ_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000e0) +#define HWIO_IPA_GSI_TOP_IC_READ_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000e0) +#define HWIO_IPA_GSI_TOP_IC_READ_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000e0) +#define HWIO_IPA_GSI_TOP_IC_READ_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000e4) +#define HWIO_IPA_GSI_TOP_IC_READ_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000e4) +#define HWIO_IPA_GSI_TOP_IC_READ_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000e4) +#define HWIO_IPA_GSI_TOP_IC_WRITE_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000e8) +#define HWIO_IPA_GSI_TOP_IC_WRITE_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000e8) +#define HWIO_IPA_GSI_TOP_IC_WRITE_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000e8) +#define HWIO_IPA_GSI_TOP_IC_WRITE_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000ec) +#define HWIO_IPA_GSI_TOP_IC_WRITE_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000ec) +#define HWIO_IPA_GSI_TOP_IC_WRITE_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000ec) +#define HWIO_IPA_GSI_TOP_IC_UCONTROLLER_GPR_BCK_PRS_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000f0) +#define HWIO_IPA_GSI_TOP_IC_UCONTROLLER_GPR_BCK_PRS_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000f0) +#define HWIO_IPA_GSI_TOP_IC_UCONTROLLER_GPR_BCK_PRS_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000f0) +#define HWIO_IPA_GSI_TOP_IC_UCONTROLLER_GPR_BCK_PRS_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x000000f4) +#define HWIO_IPA_GSI_TOP_IC_UCONTROLLER_GPR_BCK_PRS_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x000000f4) +#define HWIO_IPA_GSI_TOP_IC_UCONTROLLER_GPR_BCK_PRS_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x000000f4) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000100) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000100) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_REE_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000100) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000104) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000104) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_EVT_ENG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000104) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000108) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000108) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_INT_ENG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000108) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x0000010c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000010c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_CSR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000010c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000110) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000110) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TLV_ENG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000110) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000114) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000114) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_TIMER_ENG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000114) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000118) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000118) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_DB_ENG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000118) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000011c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000011c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_RD_WR_ENG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000011c) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000120) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000120) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_UCONTROLLER_ENG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000120) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_SDMA_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000124) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_SDMA_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000124) +#define HWIO_IPA_GSI_TOP_IC_INT_WEIGHT_SDMA_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000124) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_CFG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x0000003c) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_CFG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS \ + + 0x0000003c) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_CFG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS \ + + 0x0000003c) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_CACHEATTR_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000094) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_CACHEATTR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000094) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_CACHEATTR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000094) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_SG_IOVEC_LSB_n_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000140 + 0x8 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_SG_IOVEC_LSB_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000140 + 0x8 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_SG_IOVEC_LSB_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000140 + 0x8 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_SG_IOVEC_MSB_n_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000144 + 0x8 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_SG_IOVEC_MSB_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000144 + 0x8 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SDMA_SG_IOVEC_MSB_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000144 + 0x8 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000300 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_RMSK 0x1f1f03 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_MAXn 2 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_ATTR 0x0 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_ADDR(n), \ + HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_INMI(n, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_ADDR( \ + n), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_INI(n)) +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_MAX_EV_ALLOC_BMSK 0x1f0000 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_MAX_EV_ALLOC_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_MAX_CH_ALLOC_BMSK 0x1f00 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_MAX_CH_ALLOC_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_EE_PRIO_BMSK 0x3 +#define HWIO_IPA_GSI_TOP_GSI_MANAGER_EE_QOS_n_EE_PRIO_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000200) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000200) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000200) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_IN \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_INM(m) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_SHRAM_PTR_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_CH_CNTXT_BASE_ADDR_SHRAM_PTR_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000204) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000204) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000204) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_IN \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_INM(m) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_SHRAM_PTR_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EV_CNTXT_BASE_ADDR_SHRAM_PTR_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000208) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000208) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000208) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_IN \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_INM(m) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_SHRAM_PTR_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_STORAGE_BASE_ADDR_SHRAM_PTR_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000020c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000020c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000020c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_IN \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_INM(m) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_SHRAM_PTR_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_RE_ESC_BUF_BASE_ADDR_SHRAM_PTR_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000240) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000240) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000240) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_IN \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_INM(m) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_SHRAM_PTR_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_EE_SCRACH_BASE_ADDR_SHRAM_PTR_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000244) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000244) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000244) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_IN \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_INM(m) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OUT(v) \ + out_dword(HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_IN) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_SHRAM_PTR_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_FUNC_STACK_BASE_ADDR_SHRAM_PTR_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000248) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000248) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000248) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000024c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000024c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH1_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000024c) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000250) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000250) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_PTR_MCS_SCRATCH2_BASE_ADDR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000250) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000400) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000400) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000400) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_OUTM(m, \ + v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_CMD_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000404) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000404) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000404) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EE_GENERIC_CMD_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000418) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000418) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000418) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DB_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x0000041c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000041c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000041c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EV_DB_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000420) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000420) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000420) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_OUTM(m, \ + v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_NEW_RE_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000424) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000424) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000424) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_DIS_COMP_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000428) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000428) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000428) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_OUTM(m, \ + v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_CH_EMPTY_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000042c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000042c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000042c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_EVENT_GEN_COMP_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000430) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000430) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_0_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000430) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000434) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000434) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_2_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000434) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000438) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000438) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_PERIPH_IF_TLV_IN_1_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000438) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000043c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000043c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000043c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_TIMER_EXPIRED_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000440) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000440) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000440) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_WRITE_ENG_COMP_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000444) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000444) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000444) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_READ_ENG_COMP_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000448) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000448) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000448) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_OUTM(m, \ + v) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_UC_GP_INT_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000044c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000044c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000044c) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_INM(m) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_OUTM(m, \ + v) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_IN) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_INT_MOD_STOPPED_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_SDMA_INT_n_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000450 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_SDMA_INT_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000450 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_IRAM_PTR_SDMA_INT_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000450 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00004000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00004000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00004000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_MAXn 6143 +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INI(n) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ADDR(n), \ + HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INMI(n, mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_OUTI(n, val) \ + out_dword( \ + HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_OUTMI(n, mask, val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_GSI_INST_RAM_n_INI(n)) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00002000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00002000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00002000 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_MAXn 1023 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ADDR(n), \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_n_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_GSI_SHRAM_n_INI(n)) +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_SHRAM_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_SHRAM_n_SHRAM_SHFT 0x0 + +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00003800 + 0x80 * (n) + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00003800 + 0x80 * (n) + \ + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00003800 + 0x80 * (n) + \ + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_RMSK 0x3f +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_MAXn 2 +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_MAXk 22 +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_INI2(n, \ + k) \ + in_dword_masked(HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR( \ + n, \ + k), \ + HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_INMI2(n, k, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n, k), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_OUTI2(n, k, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n, \ + k), \ + val) +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_VALID_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_VALID_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_PHY_CH_BMSK 0x1f +#define HWIO_IPA_GSI_TOP_GSI_MAP_EE_n_CH_k_VP_TABLE_PHY_CH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00001000) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001000) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001000) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_RMSK 0xf00ff +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_IN) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_HW_EVENTS_SEL_BMSK 0xf0000 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_HW_EVENTS_SEL_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_BMSK 0xff +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_ZEROS_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_0_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_1_FVAL 0x2 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_2_FVAL 0x3 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_3_FVAL 0x4 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MCS_4_FVAL 0x5 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_DB_ENG_FVAL 0x9 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_0_FVAL 0xb +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_1_FVAL 0xc +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_2_FVAL 0xd +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_3_FVAL 0xe +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_4_FVAL 0xf +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_5_FVAL 0x10 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_6_FVAL 0x11 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_REE_7_FVAL 0x12 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_0_FVAL 0x13 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_1_FVAL 0x14 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_2_FVAL 0x15 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_3_FVAL 0x16 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_4_FVAL 0x17 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_EVE_5_FVAL 0x18 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_0_FVAL 0x1b +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IE_1_FVAL 0x1c +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_0_FVAL 0x1f +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_1_FVAL 0x20 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_2_FVAL 0x21 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_3_FVAL 0x22 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_IC_4_FVAL 0x23 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_0_FVAL 0x27 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_1_FVAL 0x28 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_2_FVAL 0x29 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_MOQA_3_FVAL 0x2a +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_0_FVAL 0x2b +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_1_FVAL 0x2c +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_2_FVAL 0x2d +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_TMR_3_FVAL 0x2e +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_0_FVAL \ + 0x33 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_1_FVAL \ + 0x34 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_2_FVAL \ + 0x35 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_RD_WR_3_FVAL \ + 0x36 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_CSR_FVAL 0x3a +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SDMA_0_FVAL 0x3c +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_SEL_GSI_TESTBUS_SEL_SMDA_1_FVAL 0x3d +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00001008) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001008) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001008) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_GSI_TESTBUS_REG_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_TEST_BUS_REG_GSI_TESTBUS_REG_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00001010) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001010) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001010) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_RMSK 0x1fff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_SDMA_BUSY_BMSK 0x1000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_SDMA_BUSY_SHFT 0xc +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_IC_BUSY_BMSK 0x800 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_IC_BUSY_SHFT 0xb +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_UC_BUSY_BMSK 0x400 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_UC_BUSY_SHFT 0xa +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_DBG_CNT_BUSY_BMSK 0x200 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_DBG_CNT_BUSY_SHFT 0x9 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_DB_ENG_BUSY_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_DB_ENG_BUSY_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_REE_PWR_CLPS_BUSY_BMSK 0x80 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_REE_PWR_CLPS_BUSY_SHFT 0x7 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_INT_ENG_BUSY_BMSK 0x40 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_INT_ENG_BUSY_SHFT 0x6 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_EV_ENG_BUSY_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_EV_ENG_BUSY_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_RD_WR_BUSY_BMSK 0x10 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_RD_WR_BUSY_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_TIMER_BUSY_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_TIMER_BUSY_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_MCS_BUSY_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_MCS_BUSY_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_REE_BUSY_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_REE_BUSY_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_CSR_BUSY_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_BUSY_REG_CSR_BUSY_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001014) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001014) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001014) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_CHID_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EVENT_PENDING_CHID_BIT_MAP_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001018) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001018) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001018) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_CHID_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_TIMER_PENDING_CHID_BIT_MAP_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000101c) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000101c) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000101c) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_CHID_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_RD_WR_PENDING_CHID_BIT_MAP_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001200 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001200 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTER_CFGn_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001200 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001240 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001240 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001240 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_MAXn 7 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_ADDR(n), \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_COUNTER_VALUE_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_COUNTERn_COUNTER_VALUE_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001040) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001040) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001040) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_OUTM(m, \ + v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_IN) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FROM_SW_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00001044) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001044) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001044) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_RMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_OUT(v) out_dword( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR, \ + v) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_IN) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_MCS_STALL_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_STALL_MCS_STALL_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001048) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001048) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001048) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_IRAM_PTR_BMSK 0xfff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_PC_FOR_DEBUG_IRAM_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001050) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001050) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_SEL_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001050) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001058) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001058) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_CLR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001058) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001060) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001060) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001060) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_RMSK 0x1ffff01 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_IN in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR, \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_INM(m) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ADDR, \ + m) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_SAVED_BMSK \ + 0x1000000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_SAVED_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_MID_BMSK \ + 0xff0000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_MID_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_TID_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_TID_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_WRITE_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_ERR_TRNS_ID_ERR_WRITE_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001064) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001064) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_0_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001064) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001068) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001068) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_1_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001068) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000106c) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000106c) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_2_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000106c) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001070 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001070 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001070 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MAXn 3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_INI(n) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n), \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MID_BMSK \ + 0xf8000000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_MID_SHFT 0x1b +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_TID_BMSK \ + 0x7c00000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_TID_SHFT 0x16 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_WRITE_BMSK \ + 0x200000 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_WRITE_SHFT 0x15 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR_20_0_BMSK \ + 0x1fffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_QSB_LOG_LAST_MISC_IDn_ADDR_20_0_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001080 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001080 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_WRITE_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001080 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001100 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001100 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001100 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_MAXn 31 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_ADDR(n), \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_INMI(n, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_ADDR( \ + n), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_RF_REG_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SW_RF_n_READ_RF_REG_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001400 + 0x80 * (n) + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001400 + 0x80 * (n) + \ + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001400 + 0x80 * (n) + \ + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_RMSK 0x3f +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_MAXn 3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_MAXk 16 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_INI2(n, \ + k) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_INMI2(n, k, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_ADDR(n, k), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_VALID_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_VALID_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHY_CH_BMSK 0x1f +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_CH_k_VP_TABLE_PHY_CH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001600 + 0x80 * (n) + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001600 + 0x80 * (n) + \ + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001600 + 0x80 * (n) + \ + 0x4 * \ + (k)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_RMSK 0x3f +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_MAXn 3 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_MAXk 11 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_INI2(n, \ + k) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_RMSK) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_INMI2(n, k, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_ADDR(n, k), \ + mask) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_VALID_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_VALID_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHY_EV_CH_BMSK 0x1f +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_EE_n_EV_k_VP_TABLE_PHY_EV_CH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SDMA_TRANS_DB_n_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00001800 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SDMA_TRANS_DB_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00001800 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_DEBUG_SDMA_TRANS_DB_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00001800 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000500) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000500) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000500) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_MSK_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000504) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_MSK_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000504) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_MSK_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000504) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_CLR_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000508) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_CLR_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000508) +#define HWIO_IPA_GSI_TOP_GSI_UC_SRC_IRQ_CLR_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000508) +#define HWIO_IPA_GSI_TOP_GSI_ACC_ARGS_n_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x0000050c + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_ACC_ARGS_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000050c + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_ACC_ARGS_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000050c + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_ACC_ROUTINE_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000524) +#define HWIO_IPA_GSI_TOP_GSI_ACC_ROUTINE_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000524) +#define HWIO_IPA_GSI_TOP_GSI_ACC_ROUTINE_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000524) +#define HWIO_IPA_GSI_TOP_GSI_ACC_GO_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x00000528) +#define HWIO_IPA_GSI_TOP_GSI_ACC_GO_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + \ + 0x00000528) +#define HWIO_IPA_GSI_TOP_GSI_ACC_GO_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + \ + 0x00000528) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_STTS_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000052c) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_STTS_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000052c) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_STTS_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000052c) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_RET_VAL_LSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000530) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_RET_VAL_LSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000530) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_RET_VAL_LSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000530) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_RET_VAL_MSB_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000534) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_RET_VAL_MSB_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000534) +#define HWIO_IPA_GSI_TOP_GSI_ACC_2_UC_MCS_RET_VAL_MSB_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000534) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_VLD_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000538) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_VLD_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000538) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_VLD_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000538) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_PC_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x0000053c) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_PC_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000053c) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_PC_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000053c) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_ARGS_n_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000540 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_ARGS_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000540 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_IC_2_UC_MCS_ARGS_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000540 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_VLD_ADDR (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x00000558) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_VLD_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000558) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_VLD_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000558) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_ROUTINE_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000055c) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_ROUTINE_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000055c) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_ROUTINE_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000055c) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_ARGS_n_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x00000560 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_ARGS_n_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x00000560 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_GSI_UC_TLV_IN_ARGS_n_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x00000560 + 0x4 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c000 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c000 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c000 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_RMSK 0xfff7dfff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK \ + 0xff000000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_NOT_ALLOCATED_FVAL \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_ALLOCATED_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STARTED_FVAL 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STOPPED_FVAL 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_STOP_IN_PROC_FVAL \ + 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_ERROR_FVAL 0xf +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ERINDEX_BMSK 0x7c000 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_ERINDEX_SHFT 0xe +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHID_BMSK 0x1f00 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHID_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_EE_BMSK 0xf0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_EE_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_INBOUND_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_DIR_OUTBOUND_FVAL \ + 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_BMSK 0x7 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_MHI_FVAL \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_XHCI_FVAL \ + 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_GPI_FVAL \ + 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_0_CHTYPE_PROTOCOL_XDCI_FVAL \ + 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c004 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c004 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c004 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c008 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c008 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c008 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c00c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c00c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c00c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c010 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c010 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c010 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_READ_PTR_LSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_4_READ_PTR_LSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c014 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c014 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c014 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_READ_PTR_MSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_5_READ_PTR_MSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c018 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c018 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c018 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_WRITE_PTR_LSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_6_WRITE_PTR_LSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c01c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c01c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c01c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_WRITE_PTR_MSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_CNTXT_7_WRITE_PTR_MSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c054 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c054 + 0x4000 * \ + (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c054 + 0x4000 * \ + (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INI2(n, \ + k) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INMI2(n, k, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OUTI2(n, k, \ + val) \ + out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_OUTMI2(n, \ + k, \ + mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_READ_PTR_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_READ_PTR_READ_PTR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c058 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c058 + 0x4000 * \ + (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c058 + 0x4000 * \ + (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INI2(n, \ + k) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, \ + k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INMI2(n, k, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OUTI2(n, k, \ + val) \ + out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, \ + k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_OUTMI2(n, \ + k, \ + mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RE_INTR_DB_BMSK \ + 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_RE_FETCH_WRITE_PTR_RE_INTR_DB_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c05c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c05c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c05c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_RMSK 0x70f +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_OUTMI2(n, k, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_ADDR(n, \ + k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_USE_ESCAPE_BUF_ONLY_BMSK 0x400 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_USE_ESCAPE_BUF_ONLY_SHFT 0xa +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_USE_DB_ENG_BMSK 0x200 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_USE_DB_ENG_SHFT 0x9 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_BMSK 0x100 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_SHFT 0x8 +#define \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_ONE_PREFETCH_SEG_FVAL \ + 0x0 +#define \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_MAX_PREFETCH_TWO_PREFETCH_SEG_FVAL \ + 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_BMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_QOS_WRR_WEIGHT_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c060 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c060 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c060 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_INI2(n, \ + k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, \ + k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_INMI2(n, k, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR( \ + n, \ + k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_OUTI2(n, k, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, \ + k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_0_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c064 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c064 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c064 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_INI2(n, \ + k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, \ + k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_INMI2(n, k, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR( \ + n, \ + k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_OUTI2(n, k, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, \ + k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_1_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c068 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c068 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c068 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_INI2(n, \ + k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, \ + k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_INMI2(n, k, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR( \ + n, \ + k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_OUTI2(n, k, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, \ + k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_2_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c06c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c06c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c06c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_MAXk 16 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_INI2(n, \ + k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, \ + k), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_INMI2(n, k, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR( \ + n, \ + k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_OUTI2(n, k, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, \ + k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_SCRATCH_3_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001c070 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001c070 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DB_ENG_WRITE_PTR_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001c070 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d000 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d000 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d000 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_RMSK 0xfff1ffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ADDR( \ + n, \ + k), mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_BMSK 0xff000000 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_ELEMENT_SIZE_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHSTATE_BMSK 0xf00000 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHSTATE_SHFT 0x14 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHSTATE_NOT_ALLOCATED_FVAL \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHSTATE_ALLOCATED_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INTYPE_BMSK 0x10000 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INTYPE_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INTYPE_MSI_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_INTYPE_IRQ_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_EVCHID_BMSK 0xff00 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_EVCHID_SHFT 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_EE_BMSK 0xf0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_EE_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_BMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_MHI_EV_FVAL 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_XHCI_EV_FVAL 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_GPI_EV_FVAL 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_0_CHTYPE_XDCI_FVAL 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d004 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d004 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d004 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_RMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_ADDR( \ + n, \ + k), mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_1_R_LENGTH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d008 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d008 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d008 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_ADDR( \ + n, \ + k), mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_2_R_BASE_ADDR_LSBS_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d00c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d00c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d00c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_ADDR( \ + n, \ + k), mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_3_R_BASE_ADDR_MSBS_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d010 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d010 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d010 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_ADDR( \ + n, \ + k), mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_READ_PTR_LSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_4_READ_PTR_LSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d014 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d014 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d014 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_READ_PTR_MSB_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_5_READ_PTR_MSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d018 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d018 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d018 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_WRITE_PTR_LSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_6_WRITE_PTR_LSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d01c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d01c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d01c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_WRITE_PTR_MSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_7_WRITE_PTR_MSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d020 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d020 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d020 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_ADDR( \ + n, \ + k), mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_BMSK 0xff000000 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MOD_CNT_SHFT 0x18 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MODC_BMSK 0xff0000 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MODC_SHFT 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MODT_BMSK 0xffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_8_INT_MODT_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d024 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d024 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d024 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_ADDR( \ + n, \ + k), mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INI2(n, \ + k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INTVEC_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_9_INTVEC_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d028 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d028 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d028 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_10_MSI_ADDR_LSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d02c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d02c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d02c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_11_MSI_ADDR_MSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d030 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d030 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d030 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_12_RP_UPDATE_ADDR_LSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d034 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d034 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d034 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_INMI2(n, k, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n, \ + k), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_CNTXT_13_RP_UPDATE_ADDR_MSB_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d048 + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d048 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d048 + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_INMI2(n, k, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR( \ + n, \ + k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_0_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001d04c + 0x4000 * (n) + \ + 0x80 * \ + (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001d04c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001d04c + 0x4000 * \ + (n) + \ + 0x80 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_MAXk 11 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_INI2(n, k) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, k), \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_INMI2(n, k, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR( \ + n, \ + k), mask) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_OUTI2(n, k, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, k), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_OUTMI2(n, k, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_ADDR(n, k), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_INI2(n, k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_SCRATCH_1_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001e000 + 0x4000 * (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001e000 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_0_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001e000 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001e004 + 0x4000 * (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001e004 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_k_DOORBELL_1_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001e004 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001e100 + 0x4000 * (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001e100 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_0_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001e100 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_ADDR(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001e104 + 0x4000 * (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_PHYS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001e104 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_k_DOORBELL_1_OFFS(n, \ + k) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001e104 + 0x4000 * \ + (n) + \ + 0x8 * (k)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x0001f000 + 0x4000 * \ + (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f000 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f000 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_RMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ENABLED_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_STATUS_ENABLED_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x0001f008 + 0x4000 * \ + (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f008 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_CH_CMD_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f008 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x0001f010 + 0x4000 * \ + (n)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f010 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_EV_CH_CMD_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f010 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f018 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f018 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_EE_GENERIC_CMD_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f018 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f038 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f038 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_0_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f038 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f03c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f03c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_1_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f03c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f040 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f040 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_2_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f040 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f044 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f044 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_SW_VERSION_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f044 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f048 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f048 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_MCS_CODE_VER_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f048 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f04c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f04c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_GSI_HW_PARAM_3_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f04c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f080 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f080 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f080 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_RMSK 0x7f +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_GENERAL_BMSK 0x40 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_GENERAL_SHFT 0x6 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_BMSK 0x20 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INTER_EE_EV_CTRL_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_BMSK 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_INTER_EE_CH_CTRL_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_IEOB_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_IEOB_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_GLOB_EE_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_EV_CTRL_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_CH_CTRL_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f088 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f088 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f088 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_RMSK 0x7f +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INMI(n, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR( \ + n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_GENERAL_BMSK 0x40 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_GENERAL_SHFT 0x6 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_EV_CTRL_BMSK \ + 0x20 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_EV_CTRL_SHFT 0x5 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_CH_CTRL_BMSK \ + 0x10 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_INTER_EE_CH_CTRL_SHFT 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_IEOB_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_IEOB_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_GLOB_EE_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_GLOB_EE_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_EV_CTRL_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f090 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f090 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f090 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_GSI_CH_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_GSI_CH_BIT_MAP_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f094 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f094 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f094 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_EV_CH_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_EV_CH_BIT_MAP_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f098 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f098 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f098 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_RMSK 0x1ffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_INI(n) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR( \ + n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR( \ + n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_INI(n)) +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_GSI_CH_BIT_MAP_MSK_BMSK \ + 0x1ffff +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_MSK_GSI_CH_BIT_MAP_MSK_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f09c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f09c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f09c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR( \ + n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR( \ + n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_INI(n)) +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_EV_CH_BIT_MAP_MSK_BMSK \ + 0xfff +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_MSK_EV_CH_BIT_MAP_MSK_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f0a0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f0a0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f0a0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_ADDR( \ + n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_GSI_CH_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_GSI_CH_IRQ_CLR_GSI_CH_BIT_MAP_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f0a4 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f0a4 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f0a4 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_ADDR( \ + n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_EV_CH_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_EV_CH_IRQ_CLR_EV_CH_BIT_MAP_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f0b0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f0b0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f0b0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_INMI(n, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_ADDR( \ + n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_EV_CH_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_EV_CH_BIT_MAP_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f0b8 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f0b8 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f0b8 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_RMSK 0xfff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_INI(n) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR( \ + n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR( \ + n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_INI(n)) +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_EV_CH_BIT_MAP_MSK_BMSK \ + 0xfff +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_MSK_EV_CH_BIT_MAP_MSK_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f0c0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f0c0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f0c0 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_ADDR( \ + n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_EV_CH_BIT_MAP_BMSK \ + 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SRC_IEOB_IRQ_CLR_EV_CH_BIT_MAP_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f100 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f100 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f100 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_RMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_BMSK 0x8 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT3_SHFT 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_BMSK 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT2_SHFT 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_GP_INT1_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_STTS_ERROR_INT_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f108 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f108 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_EN_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f108 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f110 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f110 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GLOB_IRQ_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f110 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f118 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f118 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f118 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_RMSK 0xf +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_ATTR 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_INMI(n, \ + mask) \ + in_dword_masked(HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_ADDR( \ + n), \ + mask) +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_BMSK \ + 0x8 +#define \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_MCS_STACK_OVRFLOW_SHFT \ + 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_BMSK \ + 0x4 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_CMD_FIFO_OVRFLOW_SHFT \ + 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_BMSK 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BUS_ERROR_SHFT 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_BMSK 0x1 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_STTS_GSI_BREAK_POINT_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f120 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f120 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_EN_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f120 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f128 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f128 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_GSI_IRQ_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f128 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f180 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f180 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INTSET_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f180 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f188 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f188 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_LSB_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f188 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f18c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f18c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_MSI_BASE_MSB_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f18c + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f190 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f190 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_INT_VEC_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f190 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ADDR(n) (IPA_GSI_TOP_GSI_REG_BASE \ + + 0x0001f200 + 0x4000 * \ + (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f200 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f200 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ADDR(n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ERROR_LOG_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_ERROR_LOG_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f210 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f210 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f210 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_ATTR 0x2 +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_ERROR_LOG_CLR_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_ERROR_LOG_CLR_ERROR_LOG_CLR_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f400 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f400 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f400 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_INMI(n, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR( \ + n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_0_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0001f404 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0001f404 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0001f404 + 0x4000 * (n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_RMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_MAXn 2 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ATTR 0x3 +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_INI(n) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR(n), \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_RMSK) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_INMI(n, \ + mask) in_dword_masked( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR( \ + n), \ + mask) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_OUTI(n, val) out_dword( \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR(n), \ + val) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_INI(n)) +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_SCRATCH_BMSK 0xffffffff +#define HWIO_IPA_GSI_TOP_EE_n_CNTXT_SCRATCH_1_SCRATCH_SHFT 0x0 +#define HWIO_IPA_GSI_TOP_GSI_MCS_CFG_ADDR (IPA_GSI_TOP_GSI_REG_BASE + \ + 0x0000b000) +#define HWIO_IPA_GSI_TOP_GSI_MCS_CFG_PHYS (IPA_GSI_TOP_GSI_REG_BASE_PHYS + \ + 0x0000b000) +#define HWIO_IPA_GSI_TOP_GSI_MCS_CFG_OFFS (IPA_GSI_TOP_GSI_REG_BASE_OFFS + \ + 0x0000b000) +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000b008) +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000b008) +#define HWIO_IPA_GSI_TOP_GSI_TZ_FW_AUTH_LOCK_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000b008) +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000b010) +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000b010) +#define HWIO_IPA_GSI_TOP_GSI_MSA_FW_AUTH_LOCK_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000b010) +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_ADDR ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000b018) +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_PHYS ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000b018) +#define HWIO_IPA_GSI_TOP_GSI_SP_FW_AUTH_LOCK_OFFS ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000b018) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c000 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c000 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_ORIGINATOR_EE_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c000 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c008 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c008 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_GSI_CH_CMD_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c008 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c010 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c010 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_EV_CH_CMD_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c010 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c018 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c018 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c018 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c01c + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c01c + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c01c + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c020 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c020 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_MSK_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c020 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c024 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c024 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_MSK_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c024 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c028 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c028 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_GSI_CH_IRQ_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c028 + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_ADDR(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE + 0x0000c02c + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_PHYS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_PHYS + 0x0000c02c + 0x1000 * (n)) +#define HWIO_IPA_GSI_TOP_INTER_EE_n_SRC_EV_CH_IRQ_CLR_OFFS(n) ( \ + IPA_GSI_TOP_GSI_REG_BASE_OFFS + 0x0000c02c + 0x1000 * (n)) +#define IPA_CFG_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00040000) +#define IPA_CFG_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00040000) +#define IPA_CFG_REG_BASE_OFFS 0x00040000 +#define HWIO_IPA_COMP_HW_VERSION_ADDR (IPA_CFG_REG_BASE + 0x00000030) +#define HWIO_IPA_COMP_HW_VERSION_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000030) +#define HWIO_IPA_COMP_HW_VERSION_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000030) +#define HWIO_IPA_COMP_HW_VERSION_RMSK 0xffffffff +#define HWIO_IPA_COMP_HW_VERSION_ATTR 0x1 +#define HWIO_IPA_COMP_HW_VERSION_IN in_dword_masked( \ + HWIO_IPA_COMP_HW_VERSION_ADDR, \ + HWIO_IPA_COMP_HW_VERSION_RMSK) +#define HWIO_IPA_COMP_HW_VERSION_INM(m) in_dword_masked( \ + HWIO_IPA_COMP_HW_VERSION_ADDR, \ + m) +#define HWIO_IPA_COMP_HW_VERSION_MAJOR_BMSK 0xf0000000 +#define HWIO_IPA_COMP_HW_VERSION_MAJOR_SHFT 0x1c +#define HWIO_IPA_COMP_HW_VERSION_MINOR_BMSK 0xfff0000 +#define HWIO_IPA_COMP_HW_VERSION_MINOR_SHFT 0x10 +#define HWIO_IPA_COMP_HW_VERSION_STEP_BMSK 0xffff +#define HWIO_IPA_COMP_HW_VERSION_STEP_SHFT 0x0 +#define HWIO_IPA_VERSION_ADDR (IPA_CFG_REG_BASE + 0x00000034) +#define HWIO_IPA_VERSION_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000034) +#define HWIO_IPA_VERSION_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000034) +#define HWIO_IPA_ENABLED_PIPES_ADDR (IPA_CFG_REG_BASE + 0x00000038) +#define HWIO_IPA_ENABLED_PIPES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000038) +#define HWIO_IPA_ENABLED_PIPES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000038) +#define HWIO_IPA_COMP_CFG_ADDR (IPA_CFG_REG_BASE + 0x0000003c) +#define HWIO_IPA_COMP_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_IPA_COMP_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_IPA_COMP_CFG_RMSK 0x1fffff +#define HWIO_IPA_COMP_CFG_ATTR 0x3 +#define HWIO_IPA_COMP_CFG_IN in_dword_masked(HWIO_IPA_COMP_CFG_ADDR, \ + HWIO_IPA_COMP_CFG_RMSK) +#define HWIO_IPA_COMP_CFG_INM(m) in_dword_masked(HWIO_IPA_COMP_CFG_ADDR, m) +#define HWIO_IPA_COMP_CFG_OUT(v) out_dword(HWIO_IPA_COMP_CFG_ADDR, v) +#define HWIO_IPA_COMP_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_COMP_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_COMP_CFG_IN) +#define HWIO_IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK 0x1e0000 +#define HWIO_IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT 0x11 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_BMSK 0x10000 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_SHFT 0x10 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_BMSK 0x8000 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_SHFT 0xf +#define HWIO_IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK \ + 0x4000 +#define HWIO_IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT 0xe +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK \ + 0x2000 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT \ + 0xd +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_BMSK 0x1000 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_SHFT 0xc +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_BMSK 0x800 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_SHFT 0xb +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_BMSK 0x400 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_SHFT 0xa +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_BMSK 0x200 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_SHFT 0x9 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_BMSK 0x100 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_SHFT 0x8 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_BMSK 0x80 +#define HWIO_IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_SHFT 0x7 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_BMSK 0x40 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_SHFT 0x6 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_BMSK 0x20 +#define HWIO_IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_SHFT 0x5 +#define HWIO_IPA_COMP_CFG_IPA_DCMP_FAST_CLK_EN_BMSK 0x10 +#define HWIO_IPA_COMP_CFG_IPA_DCMP_FAST_CLK_EN_SHFT 0x4 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_BMSK 0x8 +#define HWIO_IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_SHFT 0x3 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_BMSK 0x4 +#define HWIO_IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_SHFT 0x2 +#define HWIO_IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_BMSK 0x2 +#define HWIO_IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_SHFT 0x1 +#define HWIO_IPA_COMP_CFG_ENABLE_BMSK 0x1 +#define HWIO_IPA_COMP_CFG_ENABLE_SHFT 0x0 +#define HWIO_IPA_COMP_SW_RESET_ADDR (IPA_CFG_REG_BASE + 0x00000040) +#define HWIO_IPA_COMP_SW_RESET_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000040) +#define HWIO_IPA_COMP_SW_RESET_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000040) +#define HWIO_IPA_CLKON_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000044) +#define HWIO_IPA_CLKON_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000044) +#define HWIO_IPA_CLKON_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000044) +#define HWIO_IPA_ROUTE_ADDR (IPA_CFG_REG_BASE + 0x00000048) +#define HWIO_IPA_ROUTE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000048) +#define HWIO_IPA_ROUTE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000048) +#define HWIO_IPA_ROUTE_RMSK 0x13fffff +#define HWIO_IPA_ROUTE_ATTR 0x3 +#define HWIO_IPA_ROUTE_IN in_dword_masked(HWIO_IPA_ROUTE_ADDR, \ + HWIO_IPA_ROUTE_RMSK) +#define HWIO_IPA_ROUTE_INM(m) in_dword_masked(HWIO_IPA_ROUTE_ADDR, m) +#define HWIO_IPA_ROUTE_OUT(v) out_dword(HWIO_IPA_ROUTE_ADDR, v) +#define HWIO_IPA_ROUTE_OUTM(m, v) out_dword_masked_ns(HWIO_IPA_ROUTE_ADDR, \ + m, \ + v, \ + HWIO_IPA_ROUTE_IN) +#define HWIO_IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_BMSK 0x1000000 +#define HWIO_IPA_ROUTE_ROUTE_DEF_RETAIN_HDR_SHFT 0x18 +#define HWIO_IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_BMSK 0x3e0000 +#define HWIO_IPA_ROUTE_ROUTE_FRAG_DEF_PIPE_SHFT 0x11 +#define HWIO_IPA_ROUTE_ROUTE_DEF_HDR_OFST_BMSK 0x1ff80 +#define HWIO_IPA_ROUTE_ROUTE_DEF_HDR_OFST_SHFT 0x7 +#define HWIO_IPA_ROUTE_ROUTE_DEF_HDR_TABLE_BMSK 0x40 +#define HWIO_IPA_ROUTE_ROUTE_DEF_HDR_TABLE_SHFT 0x6 +#define HWIO_IPA_ROUTE_ROUTE_DEF_PIPE_BMSK 0x3e +#define HWIO_IPA_ROUTE_ROUTE_DEF_PIPE_SHFT 0x1 +#define HWIO_IPA_ROUTE_ROUTE_DIS_BMSK 0x1 +#define HWIO_IPA_ROUTE_ROUTE_DIS_SHFT 0x0 +#define HWIO_IPA_FILTER_ADDR (IPA_CFG_REG_BASE + 0x0000004c) +#define HWIO_IPA_FILTER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_IPA_FILTER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_IPA_MASTER_PRIORITY_ADDR (IPA_CFG_REG_BASE + 0x00000050) +#define HWIO_IPA_MASTER_PRIORITY_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000050) +#define HWIO_IPA_MASTER_PRIORITY_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000050) +#define HWIO_IPA_SHARED_MEM_SIZE_ADDR (IPA_CFG_REG_BASE + 0x00000054) +#define HWIO_IPA_SHARED_MEM_SIZE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000054) +#define HWIO_IPA_SHARED_MEM_SIZE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000054) +#define HWIO_IPA_NAT_TIMER_ADDR (IPA_CFG_REG_BASE + 0x00000058) +#define HWIO_IPA_NAT_TIMER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000058) +#define HWIO_IPA_NAT_TIMER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000058) +#define HWIO_IPA_NAT_TIMER_RESET_ADDR (IPA_CFG_REG_BASE + 0x0000005c) +#define HWIO_IPA_NAT_TIMER_RESET_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_IPA_NAT_TIMER_RESET_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_IPA_TAG_TIMER_ADDR (IPA_CFG_REG_BASE + 0x00000060) +#define HWIO_IPA_TAG_TIMER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000060) +#define HWIO_IPA_TAG_TIMER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000060) +#define HWIO_IPA_TAG_TIMER_RMSK 0xffffff +#define HWIO_IPA_TAG_TIMER_ATTR 0x3 +#define HWIO_IPA_TAG_TIMER_IN in_dword_masked(HWIO_IPA_TAG_TIMER_ADDR, \ + HWIO_IPA_TAG_TIMER_RMSK) +#define HWIO_IPA_TAG_TIMER_INM(m) in_dword_masked(HWIO_IPA_TAG_TIMER_ADDR, \ + m) +#define HWIO_IPA_TAG_TIMER_OUT(v) out_dword(HWIO_IPA_TAG_TIMER_ADDR, v) +#define HWIO_IPA_TAG_TIMER_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_TAG_TIMER_ADDR, \ + m, \ + v, \ + HWIO_IPA_TAG_TIMER_IN) +#define HWIO_IPA_TAG_TIMER_TAG_TIMER_BMSK 0xffffff +#define HWIO_IPA_TAG_TIMER_TAG_TIMER_SHFT 0x0 +#define HWIO_IPA_FRAG_RULES_CLR_ADDR (IPA_CFG_REG_BASE + 0x0000006c) +#define HWIO_IPA_FRAG_RULES_CLR_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_IPA_FRAG_RULES_CLR_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_IPA_PROC_IPH_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000070) +#define HWIO_IPA_PROC_IPH_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000070) +#define HWIO_IPA_PROC_IPH_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000070) +#define HWIO_IPA_PROC_IPH_CFG_RMSK 0xff0fff +#define HWIO_IPA_PROC_IPH_CFG_ATTR 0x3 +#define HWIO_IPA_PROC_IPH_CFG_IN in_dword_masked( \ + HWIO_IPA_PROC_IPH_CFG_ADDR, \ + HWIO_IPA_PROC_IPH_CFG_RMSK) +#define HWIO_IPA_PROC_IPH_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_PROC_IPH_CFG_ADDR, \ + m) +#define HWIO_IPA_PROC_IPH_CFG_OUT(v) out_dword(HWIO_IPA_PROC_IPH_CFG_ADDR, \ + v) +#define HWIO_IPA_PROC_IPH_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_PROC_IPH_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_PROC_IPH_CFG_IN) +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_VALUE_BMSK \ + 0xff0000 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_VALUE_SHFT 0x10 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_IHL_TO_2ND_FRAG_EN_BMSK 0x800 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_IHL_TO_2ND_FRAG_EN_SHFT 0xb +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_DEST_BMSK 0x400 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_DEST_SHFT 0xa +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_HOP_BMSK 0x200 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_HOP_SHFT 0x9 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_ENABLE_BMSK \ + 0x100 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PKT_PARSER_PROTOCOL_STOP_ENABLE_SHFT 0x8 +#define HWIO_IPA_PROC_IPH_CFG_FTCH_DCPH_OVERLAP_ENABLE_BMSK 0x80 +#define HWIO_IPA_PROC_IPH_CFG_FTCH_DCPH_OVERLAP_ENABLE_SHFT 0x7 +#define HWIO_IPA_PROC_IPH_CFG_PIPESTAGE_OVERLAP_DISABLE_BMSK 0x40 +#define HWIO_IPA_PROC_IPH_CFG_PIPESTAGE_OVERLAP_DISABLE_SHFT 0x6 +#define HWIO_IPA_PROC_IPH_CFG_STATUS_FROM_IPH_FRST_ALWAYS_BMSK 0x10 +#define HWIO_IPA_PROC_IPH_CFG_STATUS_FROM_IPH_FRST_ALWAYS_SHFT 0x4 +#define HWIO_IPA_PROC_IPH_CFG_IPH_TIME_CNT_CLK_SRC_BMSK 0x8 +#define HWIO_IPA_PROC_IPH_CFG_IPH_TIME_CNT_CLK_SRC_SHFT 0x3 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PIPELINING_DISABLE_BMSK 0x4 +#define HWIO_IPA_PROC_IPH_CFG_IPH_PIPELINING_DISABLE_SHFT 0x2 +#define HWIO_IPA_PROC_IPH_CFG_IPH_THRESHOLD_BMSK 0x3 +#define HWIO_IPA_PROC_IPH_CFG_IPH_THRESHOLD_SHFT 0x0 +#define HWIO_IPA_QSB_MAX_WRITES_ADDR (IPA_CFG_REG_BASE + 0x00000074) +#define HWIO_IPA_QSB_MAX_WRITES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000074) +#define HWIO_IPA_QSB_MAX_WRITES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000074) +#define HWIO_IPA_QSB_MAX_READS_ADDR (IPA_CFG_REG_BASE + 0x00000078) +#define HWIO_IPA_QSB_MAX_READS_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000078) +#define HWIO_IPA_QSB_MAX_READS_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000078) +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_ADDR (IPA_CFG_REG_BASE + \ + 0x0000007c) +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000007c) +#define HWIO_IPA_QSB_OUTSTANDING_COUNTER_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000007c) +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_ADDR (IPA_CFG_REG_BASE + \ + 0x00000080) +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_PHYS (IPA_CFG_REG_BASE_PHYS \ + + 0x00000080) +#define HWIO_IPA_QSB_OUTSTANDING_BEATS_COUNTER_OFFS (IPA_CFG_REG_BASE_OFFS \ + + 0x00000080) +#define HWIO_IPA_QSB_READ_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000084) +#define HWIO_IPA_QSB_READ_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000084) +#define HWIO_IPA_QSB_READ_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000084) +#define HWIO_IPA_DPL_TIMER_LSB_ADDR (IPA_CFG_REG_BASE + 0x00000088) +#define HWIO_IPA_DPL_TIMER_LSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000088) +#define HWIO_IPA_DPL_TIMER_LSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000088) +#define HWIO_IPA_DPL_TIMER_LSB_RMSK 0xffffffff +#define HWIO_IPA_DPL_TIMER_LSB_ATTR 0x3 +#define HWIO_IPA_DPL_TIMER_LSB_IN in_dword_masked( \ + HWIO_IPA_DPL_TIMER_LSB_ADDR, \ + HWIO_IPA_DPL_TIMER_LSB_RMSK) +#define HWIO_IPA_DPL_TIMER_LSB_INM(m) in_dword_masked( \ + HWIO_IPA_DPL_TIMER_LSB_ADDR, \ + m) +#define HWIO_IPA_DPL_TIMER_LSB_OUT(v) out_dword( \ + HWIO_IPA_DPL_TIMER_LSB_ADDR, \ + v) +#define HWIO_IPA_DPL_TIMER_LSB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_DPL_TIMER_LSB_ADDR, \ + m, \ + v, \ + HWIO_IPA_DPL_TIMER_LSB_IN) +#define HWIO_IPA_DPL_TIMER_LSB_TOD_LSB_BMSK 0xffffffff +#define HWIO_IPA_DPL_TIMER_LSB_TOD_LSB_SHFT 0x0 +#define HWIO_IPA_DPL_TIMER_MSB_ADDR (IPA_CFG_REG_BASE + 0x0000008c) +#define HWIO_IPA_DPL_TIMER_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000008c) +#define HWIO_IPA_DPL_TIMER_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000008c) +#define HWIO_IPA_DPL_TIMER_MSB_RMSK 0x8000ffff +#define HWIO_IPA_DPL_TIMER_MSB_ATTR 0x3 +#define HWIO_IPA_DPL_TIMER_MSB_IN in_dword_masked( \ + HWIO_IPA_DPL_TIMER_MSB_ADDR, \ + HWIO_IPA_DPL_TIMER_MSB_RMSK) +#define HWIO_IPA_DPL_TIMER_MSB_INM(m) in_dword_masked( \ + HWIO_IPA_DPL_TIMER_MSB_ADDR, \ + m) +#define HWIO_IPA_DPL_TIMER_MSB_OUT(v) out_dword( \ + HWIO_IPA_DPL_TIMER_MSB_ADDR, \ + v) +#define HWIO_IPA_DPL_TIMER_MSB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_DPL_TIMER_MSB_ADDR, \ + m, \ + v, \ + HWIO_IPA_DPL_TIMER_MSB_IN) +#define HWIO_IPA_DPL_TIMER_MSB_TIMER_EN_BMSK 0x80000000 +#define HWIO_IPA_DPL_TIMER_MSB_TIMER_EN_SHFT 0x1f +#define HWIO_IPA_DPL_TIMER_MSB_TOD_MSB_BMSK 0xffff +#define HWIO_IPA_DPL_TIMER_MSB_TOD_MSB_SHFT 0x0 +#define HWIO_IPA_STATE_TX_WRAPPER_ADDR (IPA_CFG_REG_BASE + 0x00000090) +#define HWIO_IPA_STATE_TX_WRAPPER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000090) +#define HWIO_IPA_STATE_TX_WRAPPER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000090) +#define HWIO_IPA_STATE_TX_WRAPPER_RMSK 0x3ff +#define HWIO_IPA_STATE_TX_WRAPPER_ATTR 0x1 +#define HWIO_IPA_STATE_TX_WRAPPER_IN in_dword_masked( \ + HWIO_IPA_STATE_TX_WRAPPER_ADDR, \ + HWIO_IPA_STATE_TX_WRAPPER_RMSK) +#define HWIO_IPA_STATE_TX_WRAPPER_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_TX_WRAPPER_ADDR, \ + m) +#define HWIO_IPA_STATE_TX_WRAPPER_PKT_DROP_CNT_IDLE_BMSK 0x200 +#define HWIO_IPA_STATE_TX_WRAPPER_PKT_DROP_CNT_IDLE_SHFT 0x9 +#define HWIO_IPA_STATE_TX_WRAPPER_TRNSEQ_FORCE_VALID_BMSK 0x100 +#define HWIO_IPA_STATE_TX_WRAPPER_TRNSEQ_FORCE_VALID_SHFT 0x8 +#define HWIO_IPA_STATE_TX_WRAPPER_MBIM_EXPIRY_BMSK 0x80 +#define HWIO_IPA_STATE_TX_WRAPPER_MBIM_EXPIRY_SHFT 0x7 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_MBIM_PKT_FMS_IDLE_BMSK 0x40 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_MBIM_PKT_FMS_IDLE_SHFT 0x6 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_TOGGLE_IDLE_BMSK 0x20 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_TOGGLE_IDLE_SHFT 0x5 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_EMPTY_BMSK 0x10 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_BRESP_EMPTY_SHFT 0x4 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_STATE_IDLE_BMSK 0x8 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_STATE_IDLE_SHFT 0x3 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_DB_EMPTY_BMSK 0x4 +#define HWIO_IPA_STATE_TX_WRAPPER_IPA_PROD_ACKMNGR_DB_EMPTY_SHFT 0x2 +#define HWIO_IPA_STATE_TX_WRAPPER_TX1_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_TX_WRAPPER_TX1_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_TX_WRAPPER_TX0_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_TX_WRAPPER_TX0_IDLE_SHFT 0x0 +#define HWIO_IPA_STATE_TX1_ADDR (IPA_CFG_REG_BASE + 0x00000094) +#define HWIO_IPA_STATE_TX1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000094) +#define HWIO_IPA_STATE_TX1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000094) +#define HWIO_IPA_STATE_TX1_RMSK 0xfffffff +#define HWIO_IPA_STATE_TX1_ATTR 0x1 +#define HWIO_IPA_STATE_TX1_IN in_dword_masked(HWIO_IPA_STATE_TX1_ADDR, \ + HWIO_IPA_STATE_TX1_RMSK) +#define HWIO_IPA_STATE_TX1_INM(m) in_dword_masked(HWIO_IPA_STATE_TX1_ADDR, \ + m) +#define HWIO_IPA_STATE_TX1_LAST_CMD_PIPE_BMSK 0xf800000 +#define HWIO_IPA_STATE_TX1_LAST_CMD_PIPE_SHFT 0x17 +#define HWIO_IPA_STATE_TX1_CS_SNIF_IDLE_BMSK 0x400000 +#define HWIO_IPA_STATE_TX1_CS_SNIF_IDLE_SHFT 0x16 +#define HWIO_IPA_STATE_TX1_SUSPEND_EMPTY_BMSK 0x200000 +#define HWIO_IPA_STATE_TX1_SUSPEND_EMPTY_SHFT 0x15 +#define HWIO_IPA_STATE_TX1_RSRCREL_IDLE_BMSK 0x100000 +#define HWIO_IPA_STATE_TX1_RSRCREL_IDLE_SHFT 0x14 +#define HWIO_IPA_STATE_TX1_HOLB_MASK_IDLE_BMSK 0x80000 +#define HWIO_IPA_STATE_TX1_HOLB_MASK_IDLE_SHFT 0x13 +#define HWIO_IPA_STATE_TX1_HOLB_IDLE_BMSK 0x40000 +#define HWIO_IPA_STATE_TX1_HOLB_IDLE_SHFT 0x12 +#define HWIO_IPA_STATE_TX1_ALIGNER_EMPTY_BMSK 0x20000 +#define HWIO_IPA_STATE_TX1_ALIGNER_EMPTY_SHFT 0x11 +#define HWIO_IPA_STATE_TX1_PF_EMPTY_BMSK 0x10000 +#define HWIO_IPA_STATE_TX1_PF_EMPTY_SHFT 0x10 +#define HWIO_IPA_STATE_TX1_PF_IDLE_BMSK 0x8000 +#define HWIO_IPA_STATE_TX1_PF_IDLE_SHFT 0xf +#define HWIO_IPA_STATE_TX1_DMAW_LAST_OUTSD_IDLE_BMSK 0x4000 +#define HWIO_IPA_STATE_TX1_DMAW_LAST_OUTSD_IDLE_SHFT 0xe +#define HWIO_IPA_STATE_TX1_DMAW_IDLE_BMSK 0x2000 +#define HWIO_IPA_STATE_TX1_DMAW_IDLE_SHFT 0xd +#define HWIO_IPA_STATE_TX1_AR_IDLE_BMSK 0x1000 +#define HWIO_IPA_STATE_TX1_AR_IDLE_SHFT 0xc +#define HWIO_IPA_STATE_TX1_TX_CMD_BRESP_INJ_IDLE_BMSK 0x800 +#define HWIO_IPA_STATE_TX1_TX_CMD_BRESP_INJ_IDLE_SHFT 0xb +#define HWIO_IPA_STATE_TX1_TX_CMD_BRESP_ALOC_IDLE_BMSK 0x400 +#define HWIO_IPA_STATE_TX1_TX_CMD_BRESP_ALOC_IDLE_SHFT 0xa +#define HWIO_IPA_STATE_TX1_TX_CMD_SNIF_IDLE_BMSK 0x200 +#define HWIO_IPA_STATE_TX1_TX_CMD_SNIF_IDLE_SHFT 0x9 +#define HWIO_IPA_STATE_TX1_TX_CMD_TRNSEQ_IDLE_BMSK 0x100 +#define HWIO_IPA_STATE_TX1_TX_CMD_TRNSEQ_IDLE_SHFT 0x8 +#define HWIO_IPA_STATE_TX1_TX_CMD_MAIN_IDLE_BMSK 0x80 +#define HWIO_IPA_STATE_TX1_TX_CMD_MAIN_IDLE_SHFT 0x7 +#define HWIO_IPA_STATE_TX1_PA_PUB_CNT_EMPTY_BMSK 0x40 +#define HWIO_IPA_STATE_TX1_PA_PUB_CNT_EMPTY_SHFT 0x6 +#define HWIO_IPA_STATE_TX1_PA_CTX_IDLE_BMSK 0x20 +#define HWIO_IPA_STATE_TX1_PA_CTX_IDLE_SHFT 0x5 +#define HWIO_IPA_STATE_TX1_PA_IDLE_BMSK 0x10 +#define HWIO_IPA_STATE_TX1_PA_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_TX1_NEXT_ARBIT_TYPE_BMSK 0xc +#define HWIO_IPA_STATE_TX1_NEXT_ARBIT_TYPE_SHFT 0x2 +#define HWIO_IPA_STATE_TX1_LAST_ARBIT_TYPE_BMSK 0x3 +#define HWIO_IPA_STATE_TX1_LAST_ARBIT_TYPE_SHFT 0x0 +#define HWIO_IPA_STATE_FETCHER_ADDR (IPA_CFG_REG_BASE + 0x00000098) +#define HWIO_IPA_STATE_FETCHER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000098) +#define HWIO_IPA_STATE_FETCHER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000098) +#define HWIO_IPA_STATE_FETCHER_RMSK 0x7ffffff +#define HWIO_IPA_STATE_FETCHER_ATTR 0x1 +#define HWIO_IPA_STATE_FETCHER_IN in_dword_masked( \ + HWIO_IPA_STATE_FETCHER_ADDR, \ + HWIO_IPA_STATE_FETCHER_RMSK) +#define HWIO_IPA_STATE_FETCHER_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_FETCHER_ADDR, \ + m) +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_IMM_CMD_EXEC_STATE_IDLE_BMSK \ + 0x4000000 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_IMM_CMD_EXEC_STATE_IDLE_SHFT 0x1a +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_SLOT_STATE_IDLE_BMSK 0x3f80000 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_SLOT_STATE_IDLE_SHFT 0x13 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_REP_STATE_IDLE_BMSK 0x7f000 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_REP_STATE_IDLE_SHFT 0xc +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_STATE_IDLE_BMSK 0xfe0 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_DMAR_STATE_IDLE_SHFT 0x5 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_CMPLT_STATE_IDLE_BMSK 0x10 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_CMPLT_STATE_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_IMM_STATE_IDLE_BMSK 0x8 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_IMM_STATE_IDLE_SHFT 0x3 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_PKT_STATE_IDLE_BMSK 0x4 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_PKT_STATE_IDLE_SHFT 0x2 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_ALLOC_STATE_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_ALLOC_STATE_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_STATE_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_FETCHER_IPA_HPS_FTCH_STATE_IDLE_SHFT 0x0 +#define HWIO_IPA_STATE_FETCHER_MASK_ADDR (IPA_CFG_REG_BASE + 0x0000009c) +#define HWIO_IPA_STATE_FETCHER_MASK_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000009c) +#define HWIO_IPA_STATE_FETCHER_MASK_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000009c) +#define HWIO_IPA_STATE_FETCHER_MASK_RMSK 0xfffffff +#define HWIO_IPA_STATE_FETCHER_MASK_ATTR 0x1 +#define HWIO_IPA_STATE_FETCHER_MASK_IN in_dword_masked( \ + HWIO_IPA_STATE_FETCHER_MASK_ADDR, \ + HWIO_IPA_STATE_FETCHER_MASK_RMSK) +#define HWIO_IPA_STATE_FETCHER_MASK_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_FETCHER_MASK_ADDR, \ + m) +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_STEP_MODE_BMSK 0xf000000 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_STEP_MODE_SHFT 0x18 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_ARB_LOCK_BMSK 0xf00000 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_ARB_LOCK_SHFT 0x14 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_NO_RESOURCES_ACK_ENTRY_BMSK \ + 0xf0000 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_NO_RESOURCES_ACK_ENTRY_SHFT \ + 0x10 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_NO_RESOURCES_HPS_DMAR_BMSK \ + 0xf000 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_NO_RESOURCES_HPS_DMAR_SHFT \ + 0xc +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_NO_RESOURCES_CONTEXT_BMSK \ + 0xf00 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_NO_RESOURCES_CONTEXT_SHFT \ + 0x8 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_IMM_EXEC_BMSK 0xf0 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_IMM_EXEC_SHFT 0x4 +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_DMAR_USES_QUEUE_BMSK 0xf +#define HWIO_IPA_STATE_FETCHER_MASK_MASK_QUEUE_DMAR_USES_QUEUE_SHFT 0x0 +#define HWIO_IPA_STATE_DFETCHER_ADDR (IPA_CFG_REG_BASE + 0x000000a0) +#define HWIO_IPA_STATE_DFETCHER_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000a0) +#define HWIO_IPA_STATE_DFETCHER_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000a0) +#define HWIO_IPA_STATE_DFETCHER_RMSK 0x3f3f3 +#define HWIO_IPA_STATE_DFETCHER_ATTR 0x1 +#define HWIO_IPA_STATE_DFETCHER_IN in_dword_masked( \ + HWIO_IPA_STATE_DFETCHER_ADDR, \ + HWIO_IPA_STATE_DFETCHER_RMSK) +#define HWIO_IPA_STATE_DFETCHER_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_DFETCHER_ADDR, \ + m) +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_DMAR_SLOT_STATE_IDLE_BMSK 0x3f000 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_DMAR_SLOT_STATE_IDLE_SHFT 0xc +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_DMAR_STATE_IDLE_BMSK 0x3f0 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_DMAR_STATE_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_FTCH_CMPLT_STATE_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_FTCH_CMPLT_STATE_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_FTCH_PKT_STATE_IDLE_BMSK 0x1 +#define HWIO_IPA_STATE_DFETCHER_IPA_DPS_FTCH_PKT_STATE_IDLE_SHFT 0x0 +#define HWIO_IPA_STATE_ACL_ADDR (IPA_CFG_REG_BASE + 0x000000a4) +#define HWIO_IPA_STATE_ACL_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000a4) +#define HWIO_IPA_STATE_ACL_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000a4) +#define HWIO_IPA_STATE_ACL_RMSK 0xffffff +#define HWIO_IPA_STATE_ACL_ATTR 0x1 +#define HWIO_IPA_STATE_ACL_IN in_dword_masked(HWIO_IPA_STATE_ACL_ADDR, \ + HWIO_IPA_STATE_ACL_RMSK) +#define HWIO_IPA_STATE_ACL_INM(m) in_dword_masked(HWIO_IPA_STATE_ACL_ADDR, \ + m) +#define HWIO_IPA_STATE_ACL_IPA_DPS_SEQUENCER_IDLE_BMSK 0x800000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_SEQUENCER_IDLE_SHFT 0x17 +#define HWIO_IPA_STATE_ACL_IPA_HPS_SEQUENCER_IDLE_BMSK 0x400000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_SEQUENCER_IDLE_SHFT 0x16 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2_ACTIVE_BMSK 0x200000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2_ACTIVE_SHFT 0x15 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2_EMPTY_BMSK 0x100000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_2_EMPTY_SHFT 0x14 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DISPATCHER_ACTIVE_BMSK 0x80000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DISPATCHER_ACTIVE_SHFT 0x13 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DISPATCHER_EMPTY_BMSK 0x40000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DISPATCHER_EMPTY_SHFT 0x12 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DCMP_ACTIVE_BMSK 0x20000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DCMP_ACTIVE_SHFT 0x11 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DCMP_EMPTY_BMSK 0x10000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_DCMP_EMPTY_SHFT 0x10 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_ACTIVE_BMSK 0x8000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_ACTIVE_SHFT 0xf +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_EMPTY_BMSK 0x4000 +#define HWIO_IPA_STATE_ACL_IPA_DPS_D_DCPH_EMPTY_SHFT 0xe +#define HWIO_IPA_STATE_ACL_IPA_HPS_ENQUEUER_ACTIVE_BMSK 0x2000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ENQUEUER_ACTIVE_SHFT 0xd +#define HWIO_IPA_STATE_ACL_IPA_HPS_ENQUEUER_EMPTY_BMSK 0x1000 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ENQUEUER_EMPTY_SHFT 0xc +#define HWIO_IPA_STATE_ACL_IPA_HPS_UCP_ACTIVE_BMSK 0x800 +#define HWIO_IPA_STATE_ACL_IPA_HPS_UCP_ACTIVE_SHFT 0xb +#define HWIO_IPA_STATE_ACL_IPA_HPS_UCP_EMPTY_BMSK 0x400 +#define HWIO_IPA_STATE_ACL_IPA_HPS_UCP_EMPTY_SHFT 0xa +#define HWIO_IPA_STATE_ACL_IPA_HPS_HDRI_ACTIVE_BMSK 0x200 +#define HWIO_IPA_STATE_ACL_IPA_HPS_HDRI_ACTIVE_SHFT 0x9 +#define HWIO_IPA_STATE_ACL_IPA_HPS_HDRI_EMPTY_BMSK 0x100 +#define HWIO_IPA_STATE_ACL_IPA_HPS_HDRI_EMPTY_SHFT 0x8 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ROUTER_ACTIVE_BMSK 0x80 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ROUTER_ACTIVE_SHFT 0x7 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ROUTER_EMPTY_BMSK 0x40 +#define HWIO_IPA_STATE_ACL_IPA_HPS_ROUTER_EMPTY_SHFT 0x6 +#define HWIO_IPA_STATE_ACL_IPA_HPS_FILTER_NAT_ACTIVE_BMSK 0x20 +#define HWIO_IPA_STATE_ACL_IPA_HPS_FILTER_NAT_ACTIVE_SHFT 0x5 +#define HWIO_IPA_STATE_ACL_IPA_HPS_FILTER_NAT_EMPTY_BMSK 0x10 +#define HWIO_IPA_STATE_ACL_IPA_HPS_FILTER_NAT_EMPTY_SHFT 0x4 +#define HWIO_IPA_STATE_ACL_IPA_HPS_PKT_PARSER_ACTIVE_BMSK 0x8 +#define HWIO_IPA_STATE_ACL_IPA_HPS_PKT_PARSER_ACTIVE_SHFT 0x3 +#define HWIO_IPA_STATE_ACL_IPA_HPS_PKT_PARSER_EMPTY_BMSK 0x4 +#define HWIO_IPA_STATE_ACL_IPA_HPS_PKT_PARSER_EMPTY_SHFT 0x2 +#define HWIO_IPA_STATE_ACL_IPA_HPS_H_DCPH_ACTIVE_BMSK 0x2 +#define HWIO_IPA_STATE_ACL_IPA_HPS_H_DCPH_ACTIVE_SHFT 0x1 +#define HWIO_IPA_STATE_ACL_IPA_HPS_H_DCPH_EMPTY_BMSK 0x1 +#define HWIO_IPA_STATE_ACL_IPA_HPS_H_DCPH_EMPTY_SHFT 0x0 +#define HWIO_IPA_STATE_GSI_TLV_ADDR (IPA_CFG_REG_BASE + 0x000000b8) +#define HWIO_IPA_STATE_GSI_TLV_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000b8) +#define HWIO_IPA_STATE_GSI_TLV_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000b8) +#define HWIO_IPA_STATE_GSI_TLV_RMSK 0x3ff +#define HWIO_IPA_STATE_GSI_TLV_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_TLV_IN in_dword_masked( \ + HWIO_IPA_STATE_GSI_TLV_ADDR, \ + HWIO_IPA_STATE_GSI_TLV_RMSK) +#define HWIO_IPA_STATE_GSI_TLV_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_GSI_TLV_ADDR, \ + m) +#define HWIO_IPA_STATE_GSI_TLV_IPA_GSI_TOGGLE_FSM_IDLE_BMSK 0x3ff +#define HWIO_IPA_STATE_GSI_TLV_IPA_GSI_TOGGLE_FSM_IDLE_SHFT 0x0 +#define HWIO_IPA_STATE_GSI_AOS_ADDR (IPA_CFG_REG_BASE + 0x000000bc) +#define HWIO_IPA_STATE_GSI_AOS_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000bc) +#define HWIO_IPA_STATE_GSI_AOS_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000bc) +#define HWIO_IPA_STATE_GSI_AOS_RMSK 0x7fffff +#define HWIO_IPA_STATE_GSI_AOS_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_AOS_IN in_dword_masked( \ + HWIO_IPA_STATE_GSI_AOS_ADDR, \ + HWIO_IPA_STATE_GSI_AOS_RMSK) +#define HWIO_IPA_STATE_GSI_AOS_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_GSI_AOS_ADDR, \ + m) +#define HWIO_IPA_STATE_GSI_AOS_IPA_GSI_AOS_FSM_IDLE_BMSK 0x7fffff +#define HWIO_IPA_STATE_GSI_AOS_IPA_GSI_AOS_FSM_IDLE_SHFT 0x0 +#define HWIO_IPA_STATE_GSI_IF_ADDR (IPA_CFG_REG_BASE + 0x000000c0) +#define HWIO_IPA_STATE_GSI_IF_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000c0) +#define HWIO_IPA_STATE_GSI_IF_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000c0) +#define HWIO_IPA_STATE_GSI_IF_RMSK 0xf +#define HWIO_IPA_STATE_GSI_IF_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_IF_IN in_dword_masked( \ + HWIO_IPA_STATE_GSI_IF_ADDR, \ + HWIO_IPA_STATE_GSI_IF_RMSK) +#define HWIO_IPA_STATE_GSI_IF_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_GSI_IF_ADDR, \ + m) +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_PROD_FSM_TX_1_BMSK 0xc +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_PROD_FSM_TX_1_SHFT 0x2 +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_PROD_FSM_TX_0_BMSK 0x3 +#define HWIO_IPA_STATE_GSI_IF_IPA_GSI_PROD_FSM_TX_0_SHFT 0x0 +#define HWIO_IPA_STATE_GSI_SKIP_ADDR (IPA_CFG_REG_BASE + 0x000000c4) +#define HWIO_IPA_STATE_GSI_SKIP_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000c4) +#define HWIO_IPA_STATE_GSI_SKIP_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000c4) +#define HWIO_IPA_STATE_GSI_SKIP_RMSK 0x3ffffff +#define HWIO_IPA_STATE_GSI_SKIP_ATTR 0x1 +#define HWIO_IPA_STATE_GSI_SKIP_IN in_dword_masked( \ + HWIO_IPA_STATE_GSI_SKIP_ADDR, \ + HWIO_IPA_STATE_GSI_SKIP_RMSK) +#define HWIO_IPA_STATE_GSI_SKIP_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_GSI_SKIP_ADDR, \ + m) +#define HWIO_IPA_STATE_GSI_SKIP_IPA_GSI_SKIP_FSM_BMSK 0x3ffffff +#define HWIO_IPA_STATE_GSI_SKIP_IPA_GSI_SKIP_FSM_SHFT 0x0 +#define HWIO_IPA_STATE_ADDR (IPA_CFG_REG_BASE + 0x000000a8) +#define HWIO_IPA_STATE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000a8) +#define HWIO_IPA_STATE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000a8) +#define HWIO_IPA_STATE_RMSK 0xf3fdfff7 +#define HWIO_IPA_STATE_ATTR 0x1 +#define HWIO_IPA_STATE_IN in_dword_masked(HWIO_IPA_STATE_ADDR, \ + HWIO_IPA_STATE_RMSK) +#define HWIO_IPA_STATE_INM(m) in_dword_masked(HWIO_IPA_STATE_ADDR, m) +#define HWIO_IPA_STATE_IPA_UC_RX_HND_CMDQ_EMPTY_BMSK 0x80000000 +#define HWIO_IPA_STATE_IPA_UC_RX_HND_CMDQ_EMPTY_SHFT 0x1f +#define HWIO_IPA_STATE_IPA_DPS_TX_EMPTY_BMSK 0x40000000 +#define HWIO_IPA_STATE_IPA_DPS_TX_EMPTY_SHFT 0x1e +#define HWIO_IPA_STATE_IPA_HPS_DPS_EMPTY_BMSK 0x20000000 +#define HWIO_IPA_STATE_IPA_HPS_DPS_EMPTY_SHFT 0x1d +#define HWIO_IPA_STATE_IPA_RX_HPS_EMPTY_BMSK 0x10000000 +#define HWIO_IPA_STATE_IPA_RX_HPS_EMPTY_SHFT 0x1c +#define HWIO_IPA_STATE_IPA_RX_SPLT_CMDQ_2_EMPTY_BMSK 0x2000000 +#define HWIO_IPA_STATE_IPA_RX_SPLT_CMDQ_2_EMPTY_SHFT 0x19 +#define HWIO_IPA_STATE_IPA_RX_SPLT_CMDQ_1_EMPTY_BMSK 0x1000000 +#define HWIO_IPA_STATE_IPA_RX_SPLT_CMDQ_1_EMPTY_SHFT 0x18 +#define HWIO_IPA_STATE_IPA_RX_SPLT_CMDQ_0_EMPTY_BMSK 0x800000 +#define HWIO_IPA_STATE_IPA_RX_SPLT_CMDQ_0_EMPTY_SHFT 0x17 +#define HWIO_IPA_STATE_IPA_TX_COMMANDER_CMDQ_EMPTY_BMSK 0x400000 +#define HWIO_IPA_STATE_IPA_TX_COMMANDER_CMDQ_EMPTY_SHFT 0x16 +#define HWIO_IPA_STATE_IPA_RX_ACKQ_EMPTY_BMSK 0x200000 +#define HWIO_IPA_STATE_IPA_RX_ACKQ_EMPTY_SHFT 0x15 +#define HWIO_IPA_STATE_IPA_UC_ACKQ_EMPTY_BMSK 0x100000 +#define HWIO_IPA_STATE_IPA_UC_ACKQ_EMPTY_SHFT 0x14 +#define HWIO_IPA_STATE_IPA_TX_ACKQ_EMPTY_BMSK 0x80000 +#define HWIO_IPA_STATE_IPA_TX_ACKQ_EMPTY_SHFT 0x13 +#define HWIO_IPA_STATE_IPA_NTF_TX_EMPTY_BMSK 0x40000 +#define HWIO_IPA_STATE_IPA_NTF_TX_EMPTY_SHFT 0x12 +#define HWIO_IPA_STATE_IPA_PROD_BRESP_IDLE_BMSK 0x10000 +#define HWIO_IPA_STATE_IPA_PROD_BRESP_IDLE_SHFT 0x10 +#define HWIO_IPA_STATE_IPA_PROD_ACKMNGR_STATE_IDLE_BMSK 0x8000 +#define HWIO_IPA_STATE_IPA_PROD_ACKMNGR_STATE_IDLE_SHFT 0xf +#define HWIO_IPA_STATE_IPA_PROD_ACKMNGR_DB_EMPTY_BMSK 0x4000 +#define HWIO_IPA_STATE_IPA_PROD_ACKMNGR_DB_EMPTY_SHFT 0xe +#define HWIO_IPA_STATE_IPA_TX_ACKQ_FULL_BMSK 0x2000 +#define HWIO_IPA_STATE_IPA_TX_ACKQ_FULL_SHFT 0xd +#define HWIO_IPA_STATE_IPA_ACKMNGR_STATE_IDLE_BMSK 0x1000 +#define HWIO_IPA_STATE_IPA_ACKMNGR_STATE_IDLE_SHFT 0xc +#define HWIO_IPA_STATE_IPA_ACKMNGR_DB_EMPTY_BMSK 0x800 +#define HWIO_IPA_STATE_IPA_ACKMNGR_DB_EMPTY_SHFT 0xb +#define HWIO_IPA_STATE_IPA_RSRC_STATE_IDLE_BMSK 0x400 +#define HWIO_IPA_STATE_IPA_RSRC_STATE_IDLE_SHFT 0xa +#define HWIO_IPA_STATE_IPA_RSRC_MNGR_DB_EMPTY_BMSK 0x200 +#define HWIO_IPA_STATE_IPA_RSRC_MNGR_DB_EMPTY_SHFT 0x9 +#define HWIO_IPA_STATE_MBIM_AGGR_IDLE_BMSK 0x100 +#define HWIO_IPA_STATE_MBIM_AGGR_IDLE_SHFT 0x8 +#define HWIO_IPA_STATE_AGGR_IDLE_BMSK 0x80 +#define HWIO_IPA_STATE_AGGR_IDLE_SHFT 0x7 +#define HWIO_IPA_STATE_IPA_NOC_IDLE_BMSK 0x40 +#define HWIO_IPA_STATE_IPA_NOC_IDLE_SHFT 0x6 +#define HWIO_IPA_STATE_IPA_STATUS_SNIFFER_IDLE_BMSK 0x20 +#define HWIO_IPA_STATE_IPA_STATUS_SNIFFER_IDLE_SHFT 0x5 +#define HWIO_IPA_STATE_BAM_GSI_IDLE_BMSK 0x10 +#define HWIO_IPA_STATE_BAM_GSI_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_TX_IDLE_BMSK 0x4 +#define HWIO_IPA_STATE_TX_IDLE_SHFT 0x2 +#define HWIO_IPA_STATE_RX_IDLE_BMSK 0x2 +#define HWIO_IPA_STATE_RX_IDLE_SHFT 0x1 +#define HWIO_IPA_STATE_RX_WAIT_BMSK 0x1 +#define HWIO_IPA_STATE_RX_WAIT_SHFT 0x0 +#define HWIO_IPA_STATE_RX_ACTIVE_ADDR (IPA_CFG_REG_BASE + 0x000000ac) +#define HWIO_IPA_STATE_RX_ACTIVE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000ac) +#define HWIO_IPA_STATE_RX_ACTIVE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000ac) +#define HWIO_IPA_STATE_RX_ACTIVE_RMSK 0x3ff +#define HWIO_IPA_STATE_RX_ACTIVE_ATTR 0x1 +#define HWIO_IPA_STATE_RX_ACTIVE_IN in_dword_masked( \ + HWIO_IPA_STATE_RX_ACTIVE_ADDR, \ + HWIO_IPA_STATE_RX_ACTIVE_RMSK) +#define HWIO_IPA_STATE_RX_ACTIVE_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_RX_ACTIVE_ADDR, \ + m) +#define HWIO_IPA_STATE_RX_ACTIVE_ENDPOINTS_BMSK 0x3ff +#define HWIO_IPA_STATE_RX_ACTIVE_ENDPOINTS_SHFT 0x0 +#define HWIO_IPA_STATE_TX0_ADDR (IPA_CFG_REG_BASE + 0x000000b0) +#define HWIO_IPA_STATE_TX0_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000000b0) +#define HWIO_IPA_STATE_TX0_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000000b0) +#define HWIO_IPA_STATE_TX0_RMSK 0xfffffff +#define HWIO_IPA_STATE_TX0_ATTR 0x1 +#define HWIO_IPA_STATE_TX0_IN in_dword_masked(HWIO_IPA_STATE_TX0_ADDR, \ + HWIO_IPA_STATE_TX0_RMSK) +#define HWIO_IPA_STATE_TX0_INM(m) in_dword_masked(HWIO_IPA_STATE_TX0_ADDR, \ + m) +#define HWIO_IPA_STATE_TX0_LAST_CMD_PIPE_BMSK 0xf800000 +#define HWIO_IPA_STATE_TX0_LAST_CMD_PIPE_SHFT 0x17 +#define HWIO_IPA_STATE_TX0_CS_SNIF_IDLE_BMSK 0x400000 +#define HWIO_IPA_STATE_TX0_CS_SNIF_IDLE_SHFT 0x16 +#define HWIO_IPA_STATE_TX0_SUSPEND_EMPTY_BMSK 0x200000 +#define HWIO_IPA_STATE_TX0_SUSPEND_EMPTY_SHFT 0x15 +#define HWIO_IPA_STATE_TX0_RSRCREL_IDLE_BMSK 0x100000 +#define HWIO_IPA_STATE_TX0_RSRCREL_IDLE_SHFT 0x14 +#define HWIO_IPA_STATE_TX0_HOLB_MASK_IDLE_BMSK 0x80000 +#define HWIO_IPA_STATE_TX0_HOLB_MASK_IDLE_SHFT 0x13 +#define HWIO_IPA_STATE_TX0_HOLB_IDLE_BMSK 0x40000 +#define HWIO_IPA_STATE_TX0_HOLB_IDLE_SHFT 0x12 +#define HWIO_IPA_STATE_TX0_ALIGNER_EMPTY_BMSK 0x20000 +#define HWIO_IPA_STATE_TX0_ALIGNER_EMPTY_SHFT 0x11 +#define HWIO_IPA_STATE_TX0_PF_EMPTY_BMSK 0x10000 +#define HWIO_IPA_STATE_TX0_PF_EMPTY_SHFT 0x10 +#define HWIO_IPA_STATE_TX0_PF_IDLE_BMSK 0x8000 +#define HWIO_IPA_STATE_TX0_PF_IDLE_SHFT 0xf +#define HWIO_IPA_STATE_TX0_DMAW_LAST_OUTSD_IDLE_BMSK 0x4000 +#define HWIO_IPA_STATE_TX0_DMAW_LAST_OUTSD_IDLE_SHFT 0xe +#define HWIO_IPA_STATE_TX0_DMAW_IDLE_BMSK 0x2000 +#define HWIO_IPA_STATE_TX0_DMAW_IDLE_SHFT 0xd +#define HWIO_IPA_STATE_TX0_AR_IDLE_BMSK 0x1000 +#define HWIO_IPA_STATE_TX0_AR_IDLE_SHFT 0xc +#define HWIO_IPA_STATE_TX0_TX_CMD_BRESP_INJ_IDLE_BMSK 0x800 +#define HWIO_IPA_STATE_TX0_TX_CMD_BRESP_INJ_IDLE_SHFT 0xb +#define HWIO_IPA_STATE_TX0_TX_CMD_BRESP_ALOC_IDLE_BMSK 0x400 +#define HWIO_IPA_STATE_TX0_TX_CMD_BRESP_ALOC_IDLE_SHFT 0xa +#define HWIO_IPA_STATE_TX0_TX_CMD_SNIF_IDLE_BMSK 0x200 +#define HWIO_IPA_STATE_TX0_TX_CMD_SNIF_IDLE_SHFT 0x9 +#define HWIO_IPA_STATE_TX0_TX_CMD_TRNSEQ_IDLE_BMSK 0x100 +#define HWIO_IPA_STATE_TX0_TX_CMD_TRNSEQ_IDLE_SHFT 0x8 +#define HWIO_IPA_STATE_TX0_TX_CMD_MAIN_IDLE_BMSK 0x80 +#define HWIO_IPA_STATE_TX0_TX_CMD_MAIN_IDLE_SHFT 0x7 +#define HWIO_IPA_STATE_TX0_PA_PUB_CNT_EMPTY_BMSK 0x40 +#define HWIO_IPA_STATE_TX0_PA_PUB_CNT_EMPTY_SHFT 0x6 +#define HWIO_IPA_STATE_TX0_PA_CTX_IDLE_BMSK 0x20 +#define HWIO_IPA_STATE_TX0_PA_CTX_IDLE_SHFT 0x5 +#define HWIO_IPA_STATE_TX0_PA_IDLE_BMSK 0x10 +#define HWIO_IPA_STATE_TX0_PA_IDLE_SHFT 0x4 +#define HWIO_IPA_STATE_TX0_NEXT_ARBIT_TYPE_BMSK 0xc +#define HWIO_IPA_STATE_TX0_NEXT_ARBIT_TYPE_SHFT 0x2 +#define HWIO_IPA_STATE_TX0_LAST_ARBIT_TYPE_BMSK 0x3 +#define HWIO_IPA_STATE_TX0_LAST_ARBIT_TYPE_SHFT 0x0 +#define HWIO_IPA_STATE_AGGR_ACTIVE_ADDR (IPA_CFG_REG_BASE + 0x000000b4) +#define HWIO_IPA_STATE_AGGR_ACTIVE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000000b4) +#define HWIO_IPA_STATE_AGGR_ACTIVE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000000b4) +#define HWIO_IPA_STATE_AGGR_ACTIVE_RMSK 0x7fffff +#define HWIO_IPA_STATE_AGGR_ACTIVE_ATTR 0x1 +#define HWIO_IPA_STATE_AGGR_ACTIVE_IN in_dword_masked( \ + HWIO_IPA_STATE_AGGR_ACTIVE_ADDR, \ + HWIO_IPA_STATE_AGGR_ACTIVE_RMSK) +#define HWIO_IPA_STATE_AGGR_ACTIVE_INM(m) in_dword_masked( \ + HWIO_IPA_STATE_AGGR_ACTIVE_ADDR, \ + m) +#define HWIO_IPA_STATE_AGGR_ACTIVE_ENDPOINTS_BMSK 0x7fffff +#define HWIO_IPA_STATE_AGGR_ACTIVE_ENDPOINTS_SHFT 0x0 +#define HWIO_IPA_YELLOW_MARKER_BELOW_ADDR (IPA_CFG_REG_BASE + 0x00000110) +#define HWIO_IPA_YELLOW_MARKER_BELOW_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000110) +#define HWIO_IPA_YELLOW_MARKER_BELOW_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000110) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_ADDR (IPA_CFG_REG_BASE + \ + 0x00000114) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000114) +#define HWIO_IPA_YELLOW_MARKER_BELOW_EN_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000114) +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_ADDR (IPA_CFG_REG_BASE + \ + 0x00000118) +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000118) +#define HWIO_IPA_YELLOW_MARKER_BELOW_CLR_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000118) +#define HWIO_IPA_RED_MARKER_BELOW_ADDR (IPA_CFG_REG_BASE + 0x0000011c) +#define HWIO_IPA_RED_MARKER_BELOW_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000011c) +#define HWIO_IPA_RED_MARKER_BELOW_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000011c) +#define HWIO_IPA_RED_MARKER_BELOW_EN_ADDR (IPA_CFG_REG_BASE + 0x00000120) +#define HWIO_IPA_RED_MARKER_BELOW_EN_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000120) +#define HWIO_IPA_RED_MARKER_BELOW_EN_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000120) +#define HWIO_IPA_RED_MARKER_BELOW_CLR_ADDR (IPA_CFG_REG_BASE + 0x00000124) +#define HWIO_IPA_RED_MARKER_BELOW_CLR_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000124) +#define HWIO_IPA_RED_MARKER_BELOW_CLR_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000124) +#define HWIO_IPA_YELLOW_MARKER_SHADOW_ADDR (IPA_CFG_REG_BASE + 0x00000128) +#define HWIO_IPA_YELLOW_MARKER_SHADOW_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000128) +#define HWIO_IPA_YELLOW_MARKER_SHADOW_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000128) +#define HWIO_IPA_RED_MARKER_SHADOW_ADDR (IPA_CFG_REG_BASE + 0x0000012c) +#define HWIO_IPA_RED_MARKER_SHADOW_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000012c) +#define HWIO_IPA_RED_MARKER_SHADOW_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000012c) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_ADDR (IPA_CFG_REG_BASE + 0x00000130) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000130) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000130) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_ADDR (IPA_CFG_REG_BASE + \ + 0x00000134) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000134) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_EN_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000134) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_ADDR (IPA_CFG_REG_BASE + \ + 0x00000138) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000138) +#define HWIO_IPA_YELLOW_MARKER_ABOVE_CLR_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000138) +#define HWIO_IPA_RED_MARKER_ABOVE_ADDR (IPA_CFG_REG_BASE + 0x0000013c) +#define HWIO_IPA_RED_MARKER_ABOVE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000013c) +#define HWIO_IPA_RED_MARKER_ABOVE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000013c) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_ADDR (IPA_CFG_REG_BASE + 0x00000140) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000140) +#define HWIO_IPA_RED_MARKER_ABOVE_EN_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000140) +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_ADDR (IPA_CFG_REG_BASE + 0x00000144) +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000144) +#define HWIO_IPA_RED_MARKER_ABOVE_CLR_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000144) +#define HWIO_IPA_FILT_ROUT_HASH_EN_ADDR (IPA_CFG_REG_BASE + 0x00000148) +#define HWIO_IPA_FILT_ROUT_HASH_EN_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000148) +#define HWIO_IPA_FILT_ROUT_HASH_EN_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000148) +#define HWIO_IPA_FILT_ROUT_HASH_EN_RMSK 0x1111 +#define HWIO_IPA_FILT_ROUT_HASH_EN_ATTR 0x3 +#define HWIO_IPA_FILT_ROUT_HASH_EN_IN in_dword_masked( \ + HWIO_IPA_FILT_ROUT_HASH_EN_ADDR, \ + HWIO_IPA_FILT_ROUT_HASH_EN_RMSK) +#define HWIO_IPA_FILT_ROUT_HASH_EN_INM(m) in_dword_masked( \ + HWIO_IPA_FILT_ROUT_HASH_EN_ADDR, \ + m) +#define HWIO_IPA_FILT_ROUT_HASH_EN_OUT(v) out_dword( \ + HWIO_IPA_FILT_ROUT_HASH_EN_ADDR, \ + v) +#define HWIO_IPA_FILT_ROUT_HASH_EN_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_FILT_ROUT_HASH_EN_ADDR, \ + m, \ + v, \ + HWIO_IPA_FILT_ROUT_HASH_EN_IN) +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV4_FILTER_HASH_EN_BMSK 0x1000 +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV4_FILTER_HASH_EN_SHFT 0xc +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV4_ROUTER_HASH_EN_BMSK 0x100 +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV4_ROUTER_HASH_EN_SHFT 0x8 +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV6_FILTER_HASH_EN_BMSK 0x10 +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV6_FILTER_HASH_EN_SHFT 0x4 +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV6_ROUTER_HASH_EN_BMSK 0x1 +#define HWIO_IPA_FILT_ROUT_HASH_EN_IPV6_ROUTER_HASH_EN_SHFT 0x0 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_ADDR (IPA_CFG_REG_BASE + 0x0000014c) +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000014c) +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000014c) +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_RMSK 0x1111 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_ATTR 0x3 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IN in_dword_masked( \ + HWIO_IPA_FILT_ROUT_HASH_FLUSH_ADDR, \ + HWIO_IPA_FILT_ROUT_HASH_FLUSH_RMSK) +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_INM(m) in_dword_masked( \ + HWIO_IPA_FILT_ROUT_HASH_FLUSH_ADDR, \ + m) +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_OUT(v) out_dword( \ + HWIO_IPA_FILT_ROUT_HASH_FLUSH_ADDR, \ + v) +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_FILT_ROUT_HASH_FLUSH_ADDR, \ + m, \ + v, \ + HWIO_IPA_FILT_ROUT_HASH_FLUSH_IN) +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV4_FILTER_HASH_FLUSH_BMSK 0x1000 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV4_FILTER_HASH_FLUSH_SHFT 0xc +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV4_ROUTER_HASH_FLUSH_BMSK 0x100 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV4_ROUTER_HASH_FLUSH_SHFT 0x8 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV6_FILTER_HASH_FLUSH_BMSK 0x10 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV6_FILTER_HASH_FLUSH_SHFT 0x4 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV6_ROUTER_HASH_FLUSH_BMSK 0x1 +#define HWIO_IPA_FILT_ROUT_HASH_FLUSH_IPV6_ROUTER_HASH_FLUSH_SHFT 0x0 +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_ADDR (IPA_CFG_REG_BASE + \ + 0x00000160) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000160) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000160) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_ATTR 0x1 +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_IN in_dword_masked( \ + HWIO_IPA_IPV4_FILTER_INIT_VALUES_ADDR, \ + HWIO_IPA_IPV4_FILTER_INIT_VALUES_RMSK) +#define HWIO_IPA_IPV4_FILTER_INIT_VALUES_INM(m) in_dword_masked( \ + HWIO_IPA_IPV4_FILTER_INIT_VALUES_ADDR, \ + m) +#define \ + HWIO_IPA_IPV4_FILTER_INIT_VALUES_IP_V4_FILTER_INIT_HASHED_ADDR_BMSK \ + 0xffff +#define \ + HWIO_IPA_IPV4_FILTER_INIT_VALUES_IP_V4_FILTER_INIT_HASHED_ADDR_SHFT \ + 0x0 +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_ADDR (IPA_CFG_REG_BASE + \ + 0x00000164) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000164) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000164) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_ATTR 0x1 +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_IN in_dword_masked( \ + HWIO_IPA_IPV6_FILTER_INIT_VALUES_ADDR, \ + HWIO_IPA_IPV6_FILTER_INIT_VALUES_RMSK) +#define HWIO_IPA_IPV6_FILTER_INIT_VALUES_INM(m) in_dword_masked( \ + HWIO_IPA_IPV6_FILTER_INIT_VALUES_ADDR, \ + m) +#define \ + HWIO_IPA_IPV6_FILTER_INIT_VALUES_IP_V6_FILTER_INIT_HASHED_ADDR_BMSK \ + 0xffff +#define \ + HWIO_IPA_IPV6_FILTER_INIT_VALUES_IP_V6_FILTER_INIT_HASHED_ADDR_SHFT \ + 0x0 +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_ADDR (IPA_CFG_REG_BASE + \ + 0x00000178) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000178) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000178) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_ADDR (IPA_CFG_REG_BASE + \ + 0x0000017c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000017c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_0_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000017c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_ADDR (IPA_CFG_REG_BASE + \ + 0x00000180) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000180) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000180) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_ADDR (IPA_CFG_REG_BASE + \ + 0x00000184) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000184) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_1_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000184) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_ADDR (IPA_CFG_REG_BASE + \ + 0x00000188) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000188) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000188) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_ADDR (IPA_CFG_REG_BASE + \ + 0x0000018c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000018c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_2_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000018c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_ADDR (IPA_CFG_REG_BASE + \ + 0x00000190) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000190) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000190) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_ADDR (IPA_CFG_REG_BASE + \ + 0x00000194) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000194) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_3_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000194) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_ADDR (IPA_CFG_REG_BASE + \ + 0x00000198) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000198) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_4_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000198) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_ADDR (IPA_CFG_REG_BASE + \ + 0x0000019c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000019c) +#define HWIO_IPA_IPV4_NAT_INIT_VALUES_5_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000019c) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_ADDR (IPA_CFG_REG_BASE + \ + 0x000001a0) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001a0) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001a0) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_ATTR 0x1 +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IN in_dword_masked( \ + HWIO_IPA_IPV4_ROUTE_INIT_VALUES_ADDR, \ + HWIO_IPA_IPV4_ROUTE_INIT_VALUES_RMSK) +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_INM(m) in_dword_masked( \ + HWIO_IPA_IPV4_ROUTE_INIT_VALUES_ADDR, \ + m) +#define \ + HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IP_V4_ROUTE_INIT_NON_HASHED_ADDR_BMSK \ + 0xffff0000 +#define \ + HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IP_V4_ROUTE_INIT_NON_HASHED_ADDR_SHFT \ + 0x10 +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IP_V4_ROUTE_INIT_HASHED_ADDR_BMSK \ + 0xffff +#define HWIO_IPA_IPV4_ROUTE_INIT_VALUES_IP_V4_ROUTE_INIT_HASHED_ADDR_SHFT \ + 0x0 +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_ADDR (IPA_CFG_REG_BASE + \ + 0x000001a4) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001a4) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001a4) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_RMSK 0xffffffff +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_ATTR 0x1 +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IN in_dword_masked( \ + HWIO_IPA_IPV6_ROUTE_INIT_VALUES_ADDR, \ + HWIO_IPA_IPV6_ROUTE_INIT_VALUES_RMSK) +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_INM(m) in_dword_masked( \ + HWIO_IPA_IPV6_ROUTE_INIT_VALUES_ADDR, \ + m) +#define \ + HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IP_V6_ROUTE_INIT_NON_HASHED_ADDR_BMSK \ + 0xffff0000 +#define \ + HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IP_V6_ROUTE_INIT_NON_HASHED_ADDR_SHFT \ + 0x10 +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IP_V6_ROUTE_INIT_HASHED_ADDR_BMSK \ + 0xffff +#define HWIO_IPA_IPV6_ROUTE_INIT_VALUES_IP_V6_ROUTE_INIT_HASHED_ADDR_SHFT \ + 0x0 +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_ADDR (IPA_CFG_REG_BASE + \ + 0x000001a8) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_PHYS (IPA_CFG_REG_BASE_PHYS \ + + 0x000001a8) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_OFFS (IPA_CFG_REG_BASE_OFFS \ + + 0x000001a8) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_ADDR (IPA_CFG_REG_BASE \ + + 0x000001ac) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_PHYS ( \ + IPA_CFG_REG_BASE_PHYS + 0x000001ac) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_0_MSB_OFFS ( \ + IPA_CFG_REG_BASE_OFFS + 0x000001ac) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_ADDR (IPA_CFG_REG_BASE + \ + 0x000001b0) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_PHYS (IPA_CFG_REG_BASE_PHYS \ + + 0x000001b0) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_OFFS (IPA_CFG_REG_BASE_OFFS \ + + 0x000001b0) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_ADDR (IPA_CFG_REG_BASE \ + + 0x000001b4) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_PHYS ( \ + IPA_CFG_REG_BASE_PHYS + 0x000001b4) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_1_MSB_OFFS ( \ + IPA_CFG_REG_BASE_OFFS + 0x000001b4) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_ADDR (IPA_CFG_REG_BASE + \ + 0x000001b8) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_PHYS (IPA_CFG_REG_BASE_PHYS \ + + 0x000001b8) +#define HWIO_IPA_IPV6_CONN_TRACK_INIT_VALUES_2_OFFS (IPA_CFG_REG_BASE_OFFS \ + + 0x000001b8) +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_ADDR (IPA_CFG_REG_BASE + 0x000001c0) +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001c0) +#define HWIO_IPA_HDR_INIT_LOCAL_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001c0) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_ADDR (IPA_CFG_REG_BASE + \ + 0x000001c4) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001c4) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001c4) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_ADDR (IPA_CFG_REG_BASE + \ + 0x000001c8) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001c8) +#define HWIO_IPA_HDR_INIT_SYSTEM_VALUES_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001c8) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_ADDR (IPA_CFG_REG_BASE + \ + 0x000001cc) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001cc) +#define HWIO_IPA_IMM_CMD_ACCESS_PIPE_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001cc) +#define HWIO_IPA_BCR_ADDR (IPA_CFG_REG_BASE + 0x000001d0) +#define HWIO_IPA_BCR_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000001d0) +#define HWIO_IPA_BCR_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000001d0) +#define HWIO_IPA_BCR_RMSK 0x3ff +#define HWIO_IPA_BCR_ATTR 0x3 +#define HWIO_IPA_BCR_IN in_dword_masked(HWIO_IPA_BCR_ADDR, \ + HWIO_IPA_BCR_RMSK) +#define HWIO_IPA_BCR_INM(m) in_dword_masked(HWIO_IPA_BCR_ADDR, m) +#define HWIO_IPA_BCR_OUT(v) out_dword(HWIO_IPA_BCR_ADDR, v) +#define HWIO_IPA_BCR_OUTM(m, v) out_dword_masked_ns(HWIO_IPA_BCR_ADDR, \ + m, \ + v, \ + HWIO_IPA_BCR_IN) +#define HWIO_IPA_BCR_BCR_ROUTER_PREFETCH_EN_BMSK 0x200 +#define HWIO_IPA_BCR_BCR_ROUTER_PREFETCH_EN_SHFT 0x9 +#define HWIO_IPA_BCR_BCR_FILTER_PREFETCH_EN_BMSK 0x100 +#define HWIO_IPA_BCR_BCR_FILTER_PREFETCH_EN_SHFT 0x8 +#define HWIO_IPA_BCR_BCR_NOTIF_PRIORITY_OVER_ZLT_BMSK 0x80 +#define HWIO_IPA_BCR_BCR_NOTIF_PRIORITY_OVER_ZLT_SHFT 0x7 +#define HWIO_IPA_BCR_BCR_ENABLE_FILTER_DATA_CACHE_BMSK 0x40 +#define HWIO_IPA_BCR_BCR_ENABLE_FILTER_DATA_CACHE_SHFT 0x6 +#define HWIO_IPA_BCR_BCR_DUAL_TX_BMSK 0x20 +#define HWIO_IPA_BCR_BCR_DUAL_TX_SHFT 0x5 +#define HWIO_IPA_BCR_BCR_HOLB_DROP_L2_IRQ_BMSK 0x10 +#define HWIO_IPA_BCR_BCR_HOLB_DROP_L2_IRQ_SHFT 0x4 +#define HWIO_IPA_BCR_BCR_SUSPEND_L2_IRQ_BMSK 0x8 +#define HWIO_IPA_BCR_BCR_SUSPEND_L2_IRQ_SHFT 0x3 +#define HWIO_IPA_BCR_BCR_TX_SUSPEND_IRQ_ONLY_ASSERT_ONCE_PER_PKT_BMSK 0x4 +#define HWIO_IPA_BCR_BCR_TX_SUSPEND_IRQ_ONLY_ASSERT_ONCE_PER_PKT_SHFT 0x2 +#define HWIO_IPA_BCR_BCR_TX_NOT_USING_BRESP_BMSK 0x2 +#define HWIO_IPA_BCR_BCR_TX_NOT_USING_BRESP_SHFT 0x1 +#define HWIO_IPA_BCR_BCR_CMDQ_L_LACK_ONE_ENTRY_BMSK 0x1 +#define HWIO_IPA_BCR_BCR_CMDQ_L_LACK_ONE_ENTRY_SHFT 0x0 +#define HWIO_IPA_MVS_ADDR (IPA_CFG_REG_BASE + 0x000001d4) +#define HWIO_IPA_MVS_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000001d4) +#define HWIO_IPA_MVS_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000001d4) +#define HWIO_IPA_FRAG_VALUES_ADDR (IPA_CFG_REG_BASE + 0x000001d8) +#define HWIO_IPA_FRAG_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000001d8) +#define HWIO_IPA_FRAG_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000001d8) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_ADDR (IPA_CFG_REG_BASE + 0x000001dc) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001dc) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001dc) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_RMSK 0x7fffff +#define HWIO_IPA_BAM_ACTIVATED_PORTS_ATTR 0x1 +#define HWIO_IPA_BAM_ACTIVATED_PORTS_IN in_dword_masked( \ + HWIO_IPA_BAM_ACTIVATED_PORTS_ADDR, \ + HWIO_IPA_BAM_ACTIVATED_PORTS_RMSK) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_INM(m) in_dword_masked( \ + HWIO_IPA_BAM_ACTIVATED_PORTS_ADDR, \ + m) +#define HWIO_IPA_BAM_ACTIVATED_PORTS_ENDPOINTS_BMSK 0x7fffff +#define HWIO_IPA_BAM_ACTIVATED_PORTS_ENDPOINTS_SHFT 0x0 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR (IPA_CFG_REG_BASE + \ + 0x000001e0) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001e0) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001e0) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_RMSK 0xffffffff +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ATTR 0x3 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_IN in_dword_masked( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR, \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_RMSK) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_INM(m) in_dword_masked( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR, \ + m) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_OUT(v) out_dword( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR, \ + v) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR, \ + m, \ + v, \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_IN) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR_BMSK 0xfffffff8 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ZERO_BMSK 0x7 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_ZERO_SHFT 0x0 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR (IPA_CFG_REG_BASE + \ + 0x000001e4) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001e4) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001e4) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_RMSK 0xffffffff +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ATTR 0x3 +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_IN in_dword_masked( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR, \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_RMSK) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_INM(m) in_dword_masked( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR, \ + m) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_OUT(v) out_dword( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR, \ + v) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_OUTM(m, \ + v) out_dword_masked_ns( \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR, \ + m, \ + v, \ + HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_IN) +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR_BMSK 0xffffffff +#define HWIO_IPA_SYS_PKT_PROC_CNTXT_BASE_MSB_ADDR_SHFT 0x0 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR (IPA_CFG_REG_BASE + \ + 0x000001e8) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001e8) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001e8) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_RMSK 0x1ffff +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ATTR 0x3 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_IN in_dword_masked( \ + HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR, \ + HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_RMSK) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_INM(m) in_dword_masked( \ + HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR, \ + m) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_OUT(v) out_dword( \ + HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR, \ + v) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_IN) +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR_BMSK 0x1fff8 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ADDR_SHFT 0x3 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ZERO_BMSK 0x7 +#define HWIO_IPA_LOCAL_PKT_PROC_CNTXT_BASE_ZERO_SHFT 0x0 +#define HWIO_IPA_AGGR_FORCE_CLOSE_ADDR (IPA_CFG_REG_BASE + 0x000001ec) +#define HWIO_IPA_AGGR_FORCE_CLOSE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000001ec) +#define HWIO_IPA_AGGR_FORCE_CLOSE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000001ec) +#define HWIO_IPA_COUNTER_CFG_ADDR (IPA_CFG_REG_BASE + 0x000001f0) +#define HWIO_IPA_COUNTER_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000001f0) +#define HWIO_IPA_COUNTER_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000001f0) +#define HWIO_IPA_SCND_FRAG_VALUES_ADDR (IPA_CFG_REG_BASE + 0x000001f4) +#define HWIO_IPA_SCND_FRAG_VALUES_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000001f4) +#define HWIO_IPA_SCND_FRAG_VALUES_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000001f4) +#define HWIO_IPA_HOL_BLOCK_TIMER_START_ADDR (IPA_CFG_REG_BASE + 0x000001f8) +#define HWIO_IPA_HOL_BLOCK_TIMER_START_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000001f8) +#define HWIO_IPA_HOL_BLOCK_TIMER_START_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000001f8) +#define HWIO_IPA_TX_CFG_ADDR (IPA_CFG_REG_BASE + 0x000001fc) +#define HWIO_IPA_TX_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000001fc) +#define HWIO_IPA_TX_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000001fc) +#define HWIO_IPA_RAM_INTLV_CFG_ADDR (IPA_CFG_REG_BASE + 0x0000020c) +#define HWIO_IPA_RAM_INTLV_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000020c) +#define HWIO_IPA_RAM_INTLV_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000020c) +#define HWIO_IPA_FLAVOR_0_ADDR (IPA_CFG_REG_BASE + 0x00000210) +#define HWIO_IPA_FLAVOR_0_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000210) +#define HWIO_IPA_FLAVOR_0_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000210) +#define HWIO_IPA_FLAVOR_1_ADDR (IPA_CFG_REG_BASE + 0x00000214) +#define HWIO_IPA_FLAVOR_1_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000214) +#define HWIO_IPA_FLAVOR_1_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000214) +#define HWIO_IPA_FLAVOR_2_ADDR (IPA_CFG_REG_BASE + 0x00000218) +#define HWIO_IPA_FLAVOR_2_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00000218) +#define HWIO_IPA_FLAVOR_2_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00000218) +#define HWIO_IPA_FLAVOR_3_ADDR (IPA_CFG_REG_BASE + 0x0000021c) +#define HWIO_IPA_FLAVOR_3_PHYS (IPA_CFG_REG_BASE_PHYS + 0x0000021c) +#define HWIO_IPA_FLAVOR_3_OFFS (IPA_CFG_REG_BASE_OFFS + 0x0000021c) +#define HWIO_IPA_IDLE_INDICATION_CFG_ADDR (IPA_CFG_REG_BASE + 0x00000220) +#define HWIO_IPA_IDLE_INDICATION_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000220) +#define HWIO_IPA_IDLE_INDICATION_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000220) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_ADDR (IPA_CFG_REG_BASE + \ + 0x00000334) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000334) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_EN_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000334) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR (IPA_CFG_REG_BASE + \ + 0x00000338) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_PHYS ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000338) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_0_OFFS ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000338) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_ADDR (IPA_CFG_REG_BASE + \ + 0x0000033c) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_PHYS ( \ + IPA_CFG_REG_BASE_PHYS + 0x0000033c) +#define HWIO_IPA_SRC_RSRC_AMOUNT_REDUCE_VALUES_1_OFFS ( \ + IPA_CFG_REG_BASE_OFFS + 0x0000033c) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_ADDR (IPA_CFG_REG_BASE + \ + 0x00000340) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000340) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_EN_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000340) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_ADDR (IPA_CFG_REG_BASE + \ + 0x00000344) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_PHYS ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000344) +#define HWIO_IPA_DST_RSRC_AMOUNT_REDUCE_VALUES_0_OFFS ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000344) +#define HWIO_IPA_HPS_DPS_CMDQ_RED_IRQ_MASK_ENABLE_ADDR (IPA_CFG_REG_BASE + \ + 0x00000348) +#define HWIO_IPA_HPS_DPS_CMDQ_RED_IRQ_MASK_ENABLE_PHYS ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000348) +#define HWIO_IPA_HPS_DPS_CMDQ_RED_IRQ_MASK_ENABLE_OFFS ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000348) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000400 + 0x20 * \ + (n)) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000400 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000400 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_INI(n) in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), \ + HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), \ + mask) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), \ + val) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_1_MAX_LIMIT_BMSK \ + 0x3f000000 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_1_MAX_LIMIT_SHFT \ + 0x18 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_1_MIN_LIMIT_BMSK \ + 0x3f0000 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_1_MIN_LIMIT_SHFT \ + 0x10 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_0_MAX_LIMIT_BMSK \ + 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_0_MAX_LIMIT_SHFT \ + 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_0_MIN_LIMIT_BMSK \ + 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_01_RSRC_TYPE_n_SRC_RSRC_GRP_0_MIN_LIMIT_SHFT \ + 0x0 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000404 + 0x20 * \ + (n)) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000404 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000404 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_INI(n) in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), \ + HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), \ + mask) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), \ + val) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_3_MAX_LIMIT_BMSK \ + 0x3f000000 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_3_MAX_LIMIT_SHFT \ + 0x18 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_3_MIN_LIMIT_BMSK \ + 0x3f0000 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_3_MIN_LIMIT_SHFT \ + 0x10 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_2_MAX_LIMIT_BMSK \ + 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_2_MAX_LIMIT_SHFT \ + 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_2_MIN_LIMIT_BMSK \ + 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n_SRC_RSRC_GRP_2_MIN_LIMIT_SHFT \ + 0x0 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n) ( \ + IPA_CFG_REG_BASE + 0x00000410 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000410 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000410 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_MAXn 4 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ATTR 0x1 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_INI(n) in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n), \ + HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_RMSK) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n), \ + mask) +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_3_CNT_BMSK \ + 0x3f000000 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_3_CNT_SHFT \ + 0x18 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_2_CNT_BMSK \ + 0x3f0000 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_2_CNT_SHFT \ + 0x10 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_1_CNT_BMSK \ + 0x3f00 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_1_CNT_SHFT \ + 0x8 +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_0_CNT_BMSK \ + 0x3f +#define HWIO_IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n_SRC_RSRC_GRP_0_CNT_SHFT \ + 0x0 +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000418 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000418 + 0x20 * (n)) +#define HWIO_IPA_SRC_RSRC_TYPE_AMOUNT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000418 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000500 + 0x20 * \ + (n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000500 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000500 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_MAXn 1 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_INI(n) in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), \ + HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), \ + mask) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR(n), \ + val) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_1_MAX_LIMIT_BMSK \ + 0x3f000000 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_1_MAX_LIMIT_SHFT \ + 0x18 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_1_MIN_LIMIT_BMSK \ + 0x3f0000 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_1_MIN_LIMIT_SHFT \ + 0x10 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_0_MAX_LIMIT_BMSK \ + 0x3f00 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_0_MAX_LIMIT_SHFT \ + 0x8 +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_0_MIN_LIMIT_BMSK \ + 0x3f +#define HWIO_IPA_DST_RSRC_GRP_01_RSRC_TYPE_n_DST_RSRC_GRP_0_MIN_LIMIT_SHFT \ + 0x0 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000504 + 0x20 * \ + (n)) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000504 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000504 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_MAXn 1 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ATTR 0x3 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_INI(n) in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), \ + HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_RMSK) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), \ + mask) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR(n), \ + val) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_INI(n)) +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_3_MAX_LIMIT_BMSK \ + 0x3f000000 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_3_MAX_LIMIT_SHFT \ + 0x18 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_3_MIN_LIMIT_BMSK \ + 0x3f0000 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_3_MIN_LIMIT_SHFT \ + 0x10 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_2_MAX_LIMIT_BMSK \ + 0x3f00 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_2_MAX_LIMIT_SHFT \ + 0x8 +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_2_MIN_LIMIT_BMSK \ + 0x3f +#define HWIO_IPA_DST_RSRC_GRP_23_RSRC_TYPE_n_DST_RSRC_GRP_2_MIN_LIMIT_SHFT \ + 0x0 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n) ( \ + IPA_CFG_REG_BASE + 0x00000510 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000510 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000510 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_RMSK 0x3f3f3f3f +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_MAXn 1 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ATTR 0x1 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_INI(n) in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n), \ + HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_RMSK) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_ADDR(n), \ + mask) +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_3_CNT_BMSK \ + 0x3f000000 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_3_CNT_SHFT \ + 0x18 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_2_CNT_BMSK \ + 0x3f0000 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_2_CNT_SHFT \ + 0x10 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_1_CNT_BMSK \ + 0x3f00 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_1_CNT_SHFT \ + 0x8 +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_0_CNT_BMSK \ + 0x3f +#define HWIO_IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n_DST_RSRC_GRP_0_CNT_SHFT \ + 0x0 +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000518 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000518 + 0x20 * (n)) +#define HWIO_IPA_DST_RSRC_TYPE_AMOUNT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000518 + 0x20 * (n)) +#define HWIO_IPA_RSRC_GRP_CFG_ADDR (IPA_CFG_REG_BASE + 0x000005a0) +#define HWIO_IPA_RSRC_GRP_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000005a0) +#define HWIO_IPA_RSRC_GRP_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000005a0) +#define HWIO_IPA_RSRC_GRP_CFG_RMSK 0x311f131 +#define HWIO_IPA_RSRC_GRP_CFG_ATTR 0x3 +#define HWIO_IPA_RSRC_GRP_CFG_IN in_dword_masked( \ + HWIO_IPA_RSRC_GRP_CFG_ADDR, \ + HWIO_IPA_RSRC_GRP_CFG_RMSK) +#define HWIO_IPA_RSRC_GRP_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_RSRC_GRP_CFG_ADDR, \ + m) +#define HWIO_IPA_RSRC_GRP_CFG_OUT(v) out_dword(HWIO_IPA_RSRC_GRP_CFG_ADDR, \ + v) +#define HWIO_IPA_RSRC_GRP_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_RSRC_GRP_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_RSRC_GRP_CFG_IN) +#define HWIO_IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_INDEX_BMSK 0x3000000 +#define HWIO_IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_INDEX_SHFT 0x18 +#define HWIO_IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_VALID_BMSK 0x100000 +#define HWIO_IPA_RSRC_GRP_CFG_DST_GRP_SPECIAL_VALID_SHFT 0x14 +#define HWIO_IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_INDEX_BMSK 0x1f000 +#define HWIO_IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_INDEX_SHFT 0xc +#define HWIO_IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_VALID_BMSK 0x100 +#define HWIO_IPA_RSRC_GRP_CFG_DST_PIPE_SPECIAL_VALID_SHFT 0x8 +#define HWIO_IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_INDEX_BMSK 0x30 +#define HWIO_IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_INDEX_SHFT 0x4 +#define HWIO_IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_VALID_BMSK 0x1 +#define HWIO_IPA_RSRC_GRP_CFG_SRC_GRP_SPECIAL_VALID_SHFT 0x0 +#define HWIO_IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_ADDR (IPA_CFG_REG_BASE + \ + 0x000005a4) +#define HWIO_IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x000005a4) +#define HWIO_IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x000005a4) +#define HWIO_IPA_PIPELINE_DISABLE_ADDR (IPA_CFG_REG_BASE + 0x000005a8) +#define HWIO_IPA_PIPELINE_DISABLE_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000005a8) +#define HWIO_IPA_PIPELINE_DISABLE_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000005a8) +#define HWIO_IPA_AXI_CFG_ADDR (IPA_CFG_REG_BASE + 0x000005ac) +#define HWIO_IPA_AXI_CFG_PHYS (IPA_CFG_REG_BASE_PHYS + 0x000005ac) +#define HWIO_IPA_AXI_CFG_OFFS (IPA_CFG_REG_BASE_OFFS + 0x000005ac) +#define HWIO_STAT_QUOTA_BASE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000700 + \ + 0x4 * (n)) +#define HWIO_STAT_QUOTA_BASE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000700 + 0x4 * (n)) +#define HWIO_STAT_QUOTA_BASE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000700 + 0x4 * (n)) +#define HWIO_STAT_QUOTA_MASK_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000708 + \ + 0x4 * (n)) +#define HWIO_STAT_QUOTA_MASK_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000708 + 0x4 * (n)) +#define HWIO_STAT_QUOTA_MASK_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000708 + 0x4 * (n)) +#define HWIO_STAT_TETHERING_BASE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000710 + 0x4 * (n)) +#define HWIO_STAT_TETHERING_BASE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000710 + 0x4 * (n)) +#define HWIO_STAT_TETHERING_BASE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000710 + 0x4 * (n)) +#define HWIO_STAT_TETHERING_MASK_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000718 + 0x4 * (n)) +#define HWIO_STAT_TETHERING_MASK_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000718 + 0x4 * (n)) +#define HWIO_STAT_TETHERING_MASK_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000718 + 0x4 * (n)) +#define HWIO_STAT_FILTER_IPV4_BASE_ADDR (IPA_CFG_REG_BASE + 0x00000720) +#define HWIO_STAT_FILTER_IPV4_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000720) +#define HWIO_STAT_FILTER_IPV4_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000720) +#define HWIO_STAT_FILTER_IPV6_BASE_ADDR (IPA_CFG_REG_BASE + 0x00000724) +#define HWIO_STAT_FILTER_IPV6_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000724) +#define HWIO_STAT_FILTER_IPV6_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000724) +#define HWIO_STAT_ROUTER_IPV4_BASE_ADDR (IPA_CFG_REG_BASE + 0x00000728) +#define HWIO_STAT_ROUTER_IPV4_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000728) +#define HWIO_STAT_ROUTER_IPV4_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000728) +#define HWIO_STAT_ROUTER_IPV6_BASE_ADDR (IPA_CFG_REG_BASE + 0x0000072c) +#define HWIO_STAT_ROUTER_IPV6_BASE_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000072c) +#define HWIO_STAT_ROUTER_IPV6_BASE_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000072c) +#define HWIO_STAT_FILTER_IPV4_START_ID_ADDR (IPA_CFG_REG_BASE + 0x00000730) +#define HWIO_STAT_FILTER_IPV4_START_ID_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000730) +#define HWIO_STAT_FILTER_IPV4_START_ID_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000730) +#define HWIO_STAT_FILTER_IPV6_START_ID_ADDR (IPA_CFG_REG_BASE + 0x00000734) +#define HWIO_STAT_FILTER_IPV6_START_ID_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000734) +#define HWIO_STAT_FILTER_IPV6_START_ID_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000734) +#define HWIO_STAT_ROUTER_IPV4_START_ID_ADDR (IPA_CFG_REG_BASE + 0x00000738) +#define HWIO_STAT_ROUTER_IPV4_START_ID_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000738) +#define HWIO_STAT_ROUTER_IPV4_START_ID_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000738) +#define HWIO_STAT_ROUTER_IPV6_START_ID_ADDR (IPA_CFG_REG_BASE + 0x0000073c) +#define HWIO_STAT_ROUTER_IPV6_START_ID_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000073c) +#define HWIO_STAT_ROUTER_IPV6_START_ID_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000073c) +#define HWIO_STAT_FILTER_IPV4_END_ID_ADDR (IPA_CFG_REG_BASE + 0x00000740) +#define HWIO_STAT_FILTER_IPV4_END_ID_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000740) +#define HWIO_STAT_FILTER_IPV4_END_ID_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000740) +#define HWIO_STAT_FILTER_IPV6_END_ID_ADDR (IPA_CFG_REG_BASE + 0x00000744) +#define HWIO_STAT_FILTER_IPV6_END_ID_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000744) +#define HWIO_STAT_FILTER_IPV6_END_ID_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000744) +#define HWIO_STAT_ROUTER_IPV4_END_ID_ADDR (IPA_CFG_REG_BASE + 0x00000748) +#define HWIO_STAT_ROUTER_IPV4_END_ID_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x00000748) +#define HWIO_STAT_ROUTER_IPV4_END_ID_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x00000748) +#define HWIO_STAT_ROUTER_IPV6_END_ID_ADDR (IPA_CFG_REG_BASE + 0x0000074c) +#define HWIO_STAT_ROUTER_IPV6_END_ID_PHYS (IPA_CFG_REG_BASE_PHYS + \ + 0x0000074c) +#define HWIO_STAT_ROUTER_IPV6_END_ID_OFFS (IPA_CFG_REG_BASE_OFFS + \ + 0x0000074c) +#define HWIO_STAT_DROP_CNT_BASE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000750 + \ + 0x4 * (n)) +#define HWIO_STAT_DROP_CNT_BASE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000750 + 0x4 * (n)) +#define HWIO_STAT_DROP_CNT_BASE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000750 + 0x4 * (n)) +#define HWIO_STAT_DROP_CNT_MASK_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000758 + \ + 0x4 * (n)) +#define HWIO_STAT_DROP_CNT_MASK_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000758 + 0x4 * (n)) +#define HWIO_STAT_DROP_CNT_MASK_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000758 + 0x4 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000800 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000800 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000800 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_RMSK 0x3 +#define HWIO_IPA_ENDP_INIT_CTRL_n_MAXn 22 +#define HWIO_IPA_ENDP_INIT_CTRL_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_CTRL_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_CTRL_n_RMSK) +#define HWIO_IPA_ENDP_INIT_CTRL_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_CTRL_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_CTRL_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_CTRL_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_CTRL_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_CTRL_n_ENDP_DELAY_BMSK 0x2 +#define HWIO_IPA_ENDP_INIT_CTRL_n_ENDP_DELAY_SHFT 0x1 +#define HWIO_IPA_ENDP_INIT_CTRL_n_ENDP_SUSPEND_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_CTRL_n_ENDP_SUSPEND_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000804 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000804 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000804 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_RMSK 0x2 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_MAXn 22 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_CTRL_SCND_n_RMSK) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_CTRL_SCND_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ENDP_DELAY_BMSK 0x2 +#define HWIO_IPA_ENDP_INIT_CTRL_SCND_n_ENDP_DELAY_SHFT 0x1 +#define HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000808 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000808 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000808 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CFG_n_RMSK 0x17f +#define HWIO_IPA_ENDP_INIT_CFG_n_MAXn 22 +#define HWIO_IPA_ENDP_INIT_CFG_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_CFG_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_CFG_n_RMSK) +#define HWIO_IPA_ENDP_INIT_CFG_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_CFG_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_CFG_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_CFG_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_CFG_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_CFG_n_GEN_QMB_MASTER_SEL_BMSK 0x100 +#define HWIO_IPA_ENDP_INIT_CFG_n_GEN_QMB_MASTER_SEL_SHFT 0x8 +#define HWIO_IPA_ENDP_INIT_CFG_n_CS_METADATA_HDR_OFFSET_BMSK 0x78 +#define HWIO_IPA_ENDP_INIT_CFG_n_CS_METADATA_HDR_OFFSET_SHFT 0x3 +#define HWIO_IPA_ENDP_INIT_CFG_n_CS_OFFLOAD_EN_BMSK 0x6 +#define HWIO_IPA_ENDP_INIT_CFG_n_CS_OFFLOAD_EN_SHFT 0x1 +#define HWIO_IPA_ENDP_INIT_CFG_n_FRAG_OFFLOAD_EN_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_CFG_n_FRAG_OFFLOAD_EN_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000080c + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_NAT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x0000080c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_NAT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x0000080c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_NAT_n_RMSK 0x3 +#define HWIO_IPA_ENDP_INIT_NAT_n_MAXn 9 +#define HWIO_IPA_ENDP_INIT_NAT_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_NAT_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_NAT_n_RMSK) +#define HWIO_IPA_ENDP_INIT_NAT_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_NAT_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_NAT_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_NAT_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_NAT_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_NAT_n_NAT_EN_BMSK 0x3 +#define HWIO_IPA_ENDP_INIT_NAT_n_NAT_EN_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000810 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000810 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000810 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_n_RMSK 0x1fffffff +#define HWIO_IPA_ENDP_INIT_HDR_n_MAXn 22 +#define HWIO_IPA_ENDP_INIT_HDR_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_HDR_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HDR_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_HDR_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_HDR_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_HDR_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_HDR_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_METADATA_REG_VALID_BMSK 0x10000000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_METADATA_REG_VALID_SHFT 0x1c +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_BMSK 0x8000000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_SHFT 0x1b +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_BMSK 0x4000000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_SHFT 0x1a +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_BMSK 0x3f00000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_SHFT 0x14 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_BMSK 0x80000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_VALID_SHFT 0x13 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_BMSK 0x7e000 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_ADDITIONAL_CONST_LEN_SHFT 0xd +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_BMSK 0x1f80 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_SHFT 0x7 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_BMSK 0x40 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_VALID_SHFT 0x6 +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_BMSK 0x3f +#define HWIO_IPA_ENDP_INIT_HDR_n_HDR_LEN_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000814 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000814 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000814 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_RMSK 0x3fff +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_MAXn 22 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_HDR_EXT_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_HDR_EXT_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_HDR_EXT_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_BMSK 0x3c00 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_PAD_TO_ALIGNMENT_SHFT 0xa +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_BMSK \ + 0x3f0 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_OFFSET_SHFT 0x4 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_PAYLOAD_LEN_INC_PADDING_BMSK 0x8 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_PAYLOAD_LEN_INC_PADDING_SHFT 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_BMSK 0x4 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_SHFT 0x2 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_VALID_BMSK 0x2 +#define HWIO_IPA_ENDP_INIT_HDR_EXT_n_HDR_TOTAL_LEN_OR_PAD_VALID_SHFT 0x1 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000818 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000818 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000818 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_RMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_MAXn 22 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_INMI(n, \ + mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR( \ + n), \ + mask) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_METADATA_MASK_BMSK \ + 0xffffffff +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_MASK_n_METADATA_MASK_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x0000081c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x0000081c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x0000081c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_RMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_MAXn 9 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_HDR_METADATA_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_METADATA_BMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HDR_METADATA_n_METADATA_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000820 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_MODE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000820 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_MODE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000820 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_MODE_n_RMSK 0x7ffff1f7 +#define HWIO_IPA_ENDP_INIT_MODE_n_MAXn 9 +#define HWIO_IPA_ENDP_INIT_MODE_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_MODE_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_MODE_n_RMSK) +#define HWIO_IPA_ENDP_INIT_MODE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_MODE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_MODE_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_MODE_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_MODE_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_MODE_n_HDR_FTCH_DISABLE_BMSK 0x40000000 +#define HWIO_IPA_ENDP_INIT_MODE_n_HDR_FTCH_DISABLE_SHFT 0x1e +#define HWIO_IPA_ENDP_INIT_MODE_n_PAD_EN_BMSK 0x20000000 +#define HWIO_IPA_ENDP_INIT_MODE_n_PAD_EN_SHFT 0x1d +#define HWIO_IPA_ENDP_INIT_MODE_n_PIPE_REPLICATE_EN_BMSK 0x10000000 +#define HWIO_IPA_ENDP_INIT_MODE_n_PIPE_REPLICATE_EN_SHFT 0x1c +#define HWIO_IPA_ENDP_INIT_MODE_n_BYTE_THRESHOLD_BMSK 0xffff000 +#define HWIO_IPA_ENDP_INIT_MODE_n_BYTE_THRESHOLD_SHFT 0xc +#define HWIO_IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_BMSK 0x1f0 +#define HWIO_IPA_ENDP_INIT_MODE_n_DEST_PIPE_INDEX_SHFT 0x4 +#define HWIO_IPA_ENDP_INIT_MODE_n_MODE_BMSK 0x7 +#define HWIO_IPA_ENDP_INIT_MODE_n_MODE_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000824 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_AGGR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000824 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_AGGR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000824 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_AGGR_n_RMSK 0x17fffff +#define HWIO_IPA_ENDP_INIT_AGGR_n_MAXn 22 +#define HWIO_IPA_ENDP_INIT_AGGR_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_AGGR_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_AGGR_n_RMSK) +#define HWIO_IPA_ENDP_INIT_AGGR_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_AGGR_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_AGGR_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_AGGR_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_AGGR_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_BMSK \ + 0x1000000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_HARD_BYTE_LIMIT_ENABLE_SHFT 0x18 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_BMSK 0x400000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_FORCE_CLOSE_SHFT 0x16 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_BMSK 0x200000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_SW_EOF_ACTIVE_SHFT 0x15 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_BMSK 0x1f8000 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_PKT_LIMIT_SHFT 0xf +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_BMSK 0x7c00 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_TIME_LIMIT_SHFT 0xa +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_BMSK 0x3e0 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_BYTE_LIMIT_SHFT 0x5 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_BMSK 0x1c +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_TYPE_SHFT 0x2 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_EN_BMSK 0x3 +#define HWIO_IPA_ENDP_INIT_AGGR_n_AGGR_EN_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x0000082c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x0000082c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x0000082c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_RMSK 0x1 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_MAXn 22 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_EN_BMSK 0x1 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_EN_n_EN_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000830 + 0x70 * \ + (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000830 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000830 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_RMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_MAXn 22 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_RMSK) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIMER_BMSK 0xffffffff +#define HWIO_IPA_ENDP_INIT_HOL_BLOCK_TIMER_n_TIMER_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000834 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000834 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000834 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_RMSK 0xffff7fff +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_MAXn 9 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_DEAGGR_n_RMSK) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_DEAGGR_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_DEAGGR_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_BMSK 0xffff0000 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_MAX_PACKET_LEN_SHFT 0x10 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_IGNORE_MIN_PKT_ERR_BMSK 0x4000 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_IGNORE_MIN_PKT_ERR_SHFT 0xe +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_LOCATION_BMSK 0x3f00 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_LOCATION_SHFT 0x8 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_BMSK 0x80 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_PACKET_OFFSET_VALID_SHFT 0x7 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_SYSPIPE_ERR_DETECTION_BMSK 0x40 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_SYSPIPE_ERR_DETECTION_SHFT 0x6 +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_BMSK 0x3f +#define HWIO_IPA_ENDP_INIT_DEAGGR_n_DEAGGR_HDR_LEN_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000838 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000838 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000838 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_RMSK 0x3 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_MAXn 22 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_RSRC_GRP_n_RMSK) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_RSRC_GRP_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_RSRC_GRP_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK 0x3 +#define HWIO_IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT 0x0 +#define HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n) (IPA_CFG_REG_BASE + 0x0000083c + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_SEQ_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x0000083c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_SEQ_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x0000083c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_SEQ_n_RMSK 0xffff +#define HWIO_IPA_ENDP_INIT_SEQ_n_MAXn 9 +#define HWIO_IPA_ENDP_INIT_SEQ_n_ATTR 0x3 +#define HWIO_IPA_ENDP_INIT_SEQ_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n), \ + HWIO_IPA_ENDP_INIT_SEQ_n_RMSK) +#define HWIO_IPA_ENDP_INIT_SEQ_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_INIT_SEQ_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_INIT_SEQ_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_INIT_SEQ_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_INIT_SEQ_n_INI(n)) +#define HWIO_IPA_ENDP_INIT_SEQ_n_DPS_REP_SEQ_TYPE_BMSK 0xf000 +#define HWIO_IPA_ENDP_INIT_SEQ_n_DPS_REP_SEQ_TYPE_SHFT 0xc +#define HWIO_IPA_ENDP_INIT_SEQ_n_HPS_REP_SEQ_TYPE_BMSK 0xf00 +#define HWIO_IPA_ENDP_INIT_SEQ_n_HPS_REP_SEQ_TYPE_SHFT 0x8 +#define HWIO_IPA_ENDP_INIT_SEQ_n_DPS_SEQ_TYPE_BMSK 0xf0 +#define HWIO_IPA_ENDP_INIT_SEQ_n_DPS_SEQ_TYPE_SHFT 0x4 +#define HWIO_IPA_ENDP_INIT_SEQ_n_HPS_SEQ_TYPE_BMSK 0xf +#define HWIO_IPA_ENDP_INIT_SEQ_n_HPS_SEQ_TYPE_SHFT 0x0 +#define HWIO_IPA_ENDP_STATUS_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000840 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_STATUS_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000840 + 0x70 * (n)) +#define HWIO_IPA_ENDP_STATUS_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000840 + 0x70 * (n)) +#define HWIO_IPA_ENDP_STATUS_n_RMSK 0x33f +#define HWIO_IPA_ENDP_STATUS_n_MAXn 22 +#define HWIO_IPA_ENDP_STATUS_n_ATTR 0x3 +#define HWIO_IPA_ENDP_STATUS_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_STATUS_n_ADDR(n), \ + HWIO_IPA_ENDP_STATUS_n_RMSK) +#define HWIO_IPA_ENDP_STATUS_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_STATUS_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_STATUS_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_STATUS_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_STATUS_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_STATUS_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_STATUS_n_INI(n)) +#define HWIO_IPA_ENDP_STATUS_n_STATUS_LOCATION_BMSK 0x100 +#define HWIO_IPA_ENDP_STATUS_n_STATUS_LOCATION_SHFT 0x8 +#define HWIO_IPA_ENDP_STATUS_n_STATUS_ENDP_BMSK 0x3e +#define HWIO_IPA_ENDP_STATUS_n_STATUS_ENDP_SHFT 0x1 +#define HWIO_IPA_ENDP_STATUS_n_STATUS_EN_BMSK 0x1 +#define HWIO_IPA_ENDP_STATUS_n_STATUS_EN_SHFT 0x0 +#define HWIO_IPA_ENDP_WEIGHTS_n_ADDR(n) (IPA_CFG_REG_BASE + 0x00000844 + \ + 0x70 * (n)) +#define HWIO_IPA_ENDP_WEIGHTS_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000844 + 0x70 * (n)) +#define HWIO_IPA_ENDP_WEIGHTS_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000844 + 0x70 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000848 + 0x70 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000848 + 0x70 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_WRITE_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000848 + 0x70 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_READ_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x0000084c + 0x70 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_READ_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x0000084c + 0x70 * (n)) +#define HWIO_IPA_ENDP_SRC_ID_READ_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x0000084c + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000850 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000850 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CONN_TRACK_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000850 + 0x70 * (n)) +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x0000085c + 0x70 * \ + (n)) +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x0000085c + 0x70 * (n)) +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x0000085c + 0x70 * (n)) +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_RMSK 0x7f007f +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_MAXn 31 +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ATTR 0x3 +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ADDR(n), \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_RMSK) +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_INMI(n, \ + mask) in_dword_masked( \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ADDR( \ + n), \ + mask) +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns(HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ADDR( \ + n), \ + mask, val, \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_INI(n)) +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_METADATA_BMSK \ + 0x400000 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_METADATA_SHFT \ + 0x16 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_PROTOCOL_BMSK \ + 0x200000 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_PROTOCOL_SHFT \ + 0x15 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_PORT_BMSK \ + 0x100000 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_PORT_SHFT \ + 0x14 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_PORT_BMSK \ + 0x80000 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_PORT_SHFT \ + 0x13 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_IP_ADD_BMSK \ + 0x40000 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_DST_IP_ADD_SHFT \ + 0x12 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_IP_ADD_BMSK \ + 0x20000 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_IP_ADD_SHFT \ + 0x11 +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_ID_BMSK \ + 0x10000 +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_ROUTER_HASH_MSK_SRC_ID_SHFT \ + 0x10 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_METADATA_BMSK \ + 0x40 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_METADATA_SHFT \ + 0x6 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_PROTOCOL_BMSK \ + 0x20 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_PROTOCOL_SHFT \ + 0x5 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_PORT_BMSK \ + 0x10 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_PORT_SHFT \ + 0x4 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_PORT_BMSK \ + 0x8 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_PORT_SHFT \ + 0x3 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_IP_ADD_BMSK \ + 0x4 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_DST_IP_ADD_SHFT \ + 0x2 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_IP_ADD_BMSK \ + 0x2 +#define \ + HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_IP_ADD_SHFT \ + 0x1 +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_ID_BMSK \ + 0x1 +#define HWIO_IPA_ENDP_FILTER_ROUTER_HSH_CFG_n_FILTER_HASH_MSK_SRC_ID_SHFT \ + 0x0 +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000860 + 0x70 * \ + (n)) +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_PHYS(n) ( \ + IPA_CFG_REG_BASE_PHYS + 0x00000860 + 0x70 * (n)) +#define HWIO_IPA_ENDP_YELLOW_RED_MARKER_CFG_n_OFFS(n) ( \ + IPA_CFG_REG_BASE_OFFS + 0x00000860 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000864 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000864 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_CTRL_STATUS_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000864 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_ADDR(n) (IPA_CFG_REG_BASE + \ + 0x00000868 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_PHYS(n) (IPA_CFG_REG_BASE_PHYS + \ + 0x00000868 + 0x70 * (n)) +#define HWIO_IPA_ENDP_INIT_PROD_CFG_n_OFFS(n) (IPA_CFG_REG_BASE_OFFS + \ + 0x00000868 + 0x70 * (n)) +#define HWIO_IPA_SNIFFER_QMB_SEL_ADDR (IPA_CFG_REG_BASE + 0x00001800) +#define HWIO_IPA_SNIFFER_QMB_SEL_PHYS (IPA_CFG_REG_BASE_PHYS + 0x00001800) +#define HWIO_IPA_SNIFFER_QMB_SEL_OFFS (IPA_CFG_REG_BASE_OFFS + 0x00001800) +#define IPA_DEBUG_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00042000) +#define IPA_DEBUG_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00042000) +#define IPA_DEBUG_REG_BASE_OFFS 0x00042000 +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000000) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000000) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000000) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_BLOCK_STATUS_ADDR (IPA_DEBUG_REG_BASE \ + + 0x00000004) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000004) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000004) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CFG_MASK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000008) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CFG_MASK_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000008) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CFG_MASK_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000008) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CFG_BLOCK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000000c) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CFG_BLOCK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000000c) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CFG_BLOCK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000000c) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000010) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000010) +#define HWIO_IPA_HPS_FTCH_ARB_DEBUG_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000010) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000014) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000014) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000014) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_BLOCK_STATUS_ADDR (IPA_DEBUG_REG_BASE \ + + 0x00000018) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000018) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000018) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CFG_MASK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000001c) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CFG_MASK_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000001c) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CFG_MASK_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000001c) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CFG_BLOCK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000020) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CFG_BLOCK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000020) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CFG_BLOCK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000020) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000024) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000024) +#define HWIO_IPA_DPS_FTCH_ARB_DEBUG_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000024) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE \ + + 0x00000028) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000028) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000028) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_BLOCK_STATUS_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x0000002c) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000002c) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000002c) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CFG_MASK_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000030) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CFG_MASK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000030) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CFG_MASK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000030) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CFG_BLOCK_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000034) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CFG_BLOCK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000034) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CFG_BLOCK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000034) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000038) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CMD_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000038) +#define HWIO_IPA_RSRC_MNGR_FUNC_ARB_DEBUG_CMD_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000038) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE \ + + 0x0000003c) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000003c) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000003c) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_BLOCK_STATUS_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000040) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000040) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000040) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CFG_MASK_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000044) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CFG_MASK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000044) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CFG_MASK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000044) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CFG_BLOCK_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000048) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CFG_BLOCK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000048) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CFG_BLOCK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000048) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000004c) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CMD_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000004c) +#define HWIO_IPA_RSRC_MNGR_ALLOC_ARB_DEBUG_CMD_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000004c) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE \ + + 0x00000050) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000050) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000050) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_BLOCK_STATUS_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000054) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000054) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000054) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CFG_MASK_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000058) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CFG_MASK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000058) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CFG_MASK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000058) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CFG_BLOCK_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x0000005c) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CFG_BLOCK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000005c) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CFG_BLOCK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000005c) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000060) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CMD_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000060) +#define HWIO_IPA_RSRC_MNGR_SRCH_ARB_DEBUG_CMD_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000060) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000064) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000064) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000064) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_BLOCK_STATUS_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000068) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000068) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000068) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CFG_MASK_ADDR (IPA_DEBUG_REG_BASE \ + + 0x0000006c) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CFG_MASK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000006c) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CFG_MASK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000006c) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CFG_BLOCK_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000070) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CFG_BLOCK_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000070) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CFG_BLOCK_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000070) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000074) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000074) +#define HWIO_IPA_RSRC_MNGR_REL_ARB_DEBUG_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000074) +#define HWIO_IPA_TX_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000078) +#define HWIO_IPA_TX_ARB_DEBUG_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000078) +#define HWIO_IPA_TX_ARB_DEBUG_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000078) +#define HWIO_IPA_TX_ARB_DEBUG_BLOCK_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000007c) +#define HWIO_IPA_TX_ARB_DEBUG_BLOCK_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000007c) +#define HWIO_IPA_TX_ARB_DEBUG_BLOCK_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000007c) +#define HWIO_IPA_TX_ARB_DEBUG_CFG_MASK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000080) +#define HWIO_IPA_TX_ARB_DEBUG_CFG_MASK_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000080) +#define HWIO_IPA_TX_ARB_DEBUG_CFG_MASK_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000080) +#define HWIO_IPA_TX_ARB_DEBUG_CFG_BLOCK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000084) +#define HWIO_IPA_TX_ARB_DEBUG_CFG_BLOCK_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000084) +#define HWIO_IPA_TX_ARB_DEBUG_CFG_BLOCK_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000084) +#define HWIO_IPA_TX_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000088) +#define HWIO_IPA_TX_ARB_DEBUG_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000088) +#define HWIO_IPA_TX_ARB_DEBUG_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000088) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000008c) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000008c) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000008c) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_BLOCK_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000090) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000090) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000090) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CFG_MASK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000094) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CFG_MASK_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000094) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CFG_MASK_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000094) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CFG_BLOCK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000098) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CFG_BLOCK_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000098) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CFG_BLOCK_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000098) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000009c) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000009c) +#define HWIO_IPA_HPS_SEQ_ARB_DEBUG_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000009c) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000100) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000100) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000100) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_BLOCK_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000104) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_BLOCK_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000104) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_BLOCK_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000104) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CFG_MASK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000108) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CFG_MASK_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000108) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CFG_MASK_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000108) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CFG_BLOCK_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000010c) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CFG_BLOCK_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000010c) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CFG_BLOCK_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000010c) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000110) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000110) +#define HWIO_IPA_DPS_SEQ_ARB_DEBUG_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000110) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000114) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000114) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_ALLOC_CFG_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000114) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000118) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000118) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_SRCH_CFG_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000118) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000011c) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000011c) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_REL_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000011c) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000120) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000120) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000120) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000124) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000124) +#define HWIO_IPA_RSRC_MNGR_SW_ACCESS_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000124) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000128) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000128) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000128) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RMSK 0x3f73 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_ATTR 0x3 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_IN in_dword_masked( \ + HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR, \ + HWIO_IPA_RSRC_MNGR_DB_CFG_RMSK) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR, \ + m) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_OUT(v) out_dword( \ + HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR, \ + v) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_RSRC_MNGR_DB_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_RSRC_MNGR_DB_CFG_IN) +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_ID_SEL_BMSK 0x3f00 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_ID_SEL_SHFT 0x8 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_TYPE_SEL_BMSK 0x70 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_TYPE_SEL_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_GRP_SEL_BMSK 0x3 +#define HWIO_IPA_RSRC_MNGR_DB_CFG_RSRC_GRP_SEL_SHFT 0x0 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000012c) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000012c) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000012c) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RMSK 0x3f3 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ATTR 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_IN in_dword_masked( \ + HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ADDR, \ + HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RMSK) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_INM(m) in_dword_masked( \ + HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_ADDR, \ + m) +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_NEXT_INDEX_BMSK 0x3f0 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_NEXT_INDEX_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_NEXT_VALID_BMSK 0x2 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_NEXT_VALID_SHFT 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_OCCUPIED_BMSK 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_RSRC_READ_RSRC_OCCUPIED_SHFT 0x0 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000130) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000130) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000130) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RMSK 0x7f7f3f3 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ATTR 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_IN in_dword_masked( \ + HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ADDR, \ + HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RMSK) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_INM(m) in_dword_masked( \ + HWIO_IPA_RSRC_MNGR_DB_LIST_READ_ADDR, \ + m) +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_ENTRY_CNT_BMSK 0x7f00000 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_ENTRY_CNT_SHFT 0x14 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HEAD_CNT_BMSK 0x7f000 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HEAD_CNT_SHFT 0xc +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HEAD_RSRC_BMSK 0x3f0 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HEAD_RSRC_SHFT 0x4 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HOLD_BMSK 0x2 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_HOLD_SHFT 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_VALID_BMSK 0x1 +#define HWIO_IPA_RSRC_MNGR_DB_LIST_READ_RSRC_LIST_VALID_SHFT 0x0 +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_ADDR (IPA_DEBUG_REG_BASE + 0x00000134) +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000134) +#define HWIO_IPA_RSRC_MNGR_CONTEXTS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000134) +#define HWIO_IPA_BRESP_DB_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000138) +#define HWIO_IPA_BRESP_DB_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000138) +#define HWIO_IPA_BRESP_DB_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000138) +#define HWIO_IPA_BRESP_DB_DATA_ADDR (IPA_DEBUG_REG_BASE + 0x0000013c) +#define HWIO_IPA_BRESP_DB_DATA_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000013c) +#define HWIO_IPA_BRESP_DB_DATA_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000013c) +#define HWIO_IPA_DEBUG_DATA_SEL_ADDR (IPA_DEBUG_REG_BASE + 0x00000200) +#define HWIO_IPA_DEBUG_DATA_SEL_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000200) +#define HWIO_IPA_DEBUG_DATA_SEL_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000200) +#define HWIO_IPA_DEBUG_DATA_SEL_RMSK 0x11fffff +#define HWIO_IPA_DEBUG_DATA_SEL_ATTR 0x3 +#define HWIO_IPA_DEBUG_DATA_SEL_IN in_dword_masked( \ + HWIO_IPA_DEBUG_DATA_SEL_ADDR, \ + HWIO_IPA_DEBUG_DATA_SEL_RMSK) +#define HWIO_IPA_DEBUG_DATA_SEL_INM(m) in_dword_masked( \ + HWIO_IPA_DEBUG_DATA_SEL_ADDR, \ + m) +#define HWIO_IPA_DEBUG_DATA_SEL_OUT(v) out_dword( \ + HWIO_IPA_DEBUG_DATA_SEL_ADDR, \ + v) +#define HWIO_IPA_DEBUG_DATA_SEL_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_DEBUG_DATA_SEL_ADDR, \ + m, \ + v, \ + HWIO_IPA_DEBUG_DATA_SEL_IN) +#define HWIO_IPA_DEBUG_DATA_SEL_UC_DAP_EN_BMSK 0x1000000 +#define HWIO_IPA_DEBUG_DATA_SEL_UC_DAP_EN_SHFT 0x18 +#define HWIO_IPA_DEBUG_DATA_SEL_PIPE_SELECT_BMSK 0x1f0000 +#define HWIO_IPA_DEBUG_DATA_SEL_PIPE_SELECT_SHFT 0x10 +#define HWIO_IPA_DEBUG_DATA_SEL_INTERNAL_BLOCK_SELECT_BMSK 0xff00 +#define HWIO_IPA_DEBUG_DATA_SEL_INTERNAL_BLOCK_SELECT_SHFT 0x8 +#define HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_BMSK 0xff +#define HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_SHFT 0x0 +#define HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_IPA_RX_DEBUGBUS_FVAL \ + 0x0 +#define HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_IPA_TX_DEBUGBUS_FVAL \ + 0x1 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_HPS_FRAG_DEBUGBUS_FVAL \ + 0x2 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_HPS_UCP_DEBUGBUS_FVAL \ + 0x3 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_HPS_ROUTER_DEBUGBUS_FVAL \ + 0x5 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_DPS_DCMP_DEBUGBUS_FVAL \ + 0xb +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_DPS_D_DCPH_DEBUGBUS_FVAL \ + 0xd +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_GSI_TEST_BUS_OUT_FVAL \ + 0xe +#define HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_DEADBEAF_FVAL 0xf +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_IPA_MISC_DEBUGBUS_FVAL \ + 0x10 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_IPA_QMB_DEBUGBUS_0_FVAL \ + 0x12 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_IPA_QMB_DEBUGBUS_1_FVAL \ + 0x13 +#define HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_AGGR_DEBUGBUS_FVAL \ + 0x16 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_HPS_H_DCPH_DEBUGBUS_FVAL \ + 0x17 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_IPA_CMDQ_L_TESTBUS_FVAL \ + 0x1b +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_IPA_GSI_DEBUGBUS_FVAL \ + 0x1e +#define HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_RSRC_DEBUGBUS_FVAL \ + 0x32 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_ACKMNGR_DEBUGBUS_FVAL \ + 0x33 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_HPS_SEQ_DEBUGBUS_FVAL \ + 0x34 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_DPS_SEQ_DEBUGBUS_FVAL \ + 0x35 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_HPS_FTCH_DEBUGBUS_FVAL \ + 0x36 +#define \ + HWIO_IPA_DEBUG_DATA_SEL_EXTERNAL_BLOCK_SELECT_DPS_FTCH_DEBUGBUS_FVAL \ + 0x37 +#define HWIO_IPA_DEBUG_DATA_ADDR (IPA_DEBUG_REG_BASE + 0x00000204) +#define HWIO_IPA_DEBUG_DATA_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000204) +#define HWIO_IPA_DEBUG_DATA_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000204) +#define HWIO_IPA_DEBUG_DATA_RMSK 0xffffffff +#define HWIO_IPA_DEBUG_DATA_ATTR 0x1 +#define HWIO_IPA_DEBUG_DATA_IN in_dword_masked(HWIO_IPA_DEBUG_DATA_ADDR, \ + HWIO_IPA_DEBUG_DATA_RMSK) +#define HWIO_IPA_DEBUG_DATA_INM(m) in_dword_masked( \ + HWIO_IPA_DEBUG_DATA_ADDR, \ + m) +#define HWIO_IPA_DEBUG_DATA_DEBUG_DATA_BMSK 0xffffffff +#define HWIO_IPA_DEBUG_DATA_DEBUG_DATA_SHFT 0x0 +#define HWIO_IPA_TESTBUS_SEL_ADDR (IPA_DEBUG_REG_BASE + 0x00000208) +#define HWIO_IPA_TESTBUS_SEL_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000208) +#define HWIO_IPA_TESTBUS_SEL_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000208) +#define HWIO_IPA_TESTBUS_SEL_RMSK 0x1fffff1 +#define HWIO_IPA_TESTBUS_SEL_ATTR 0x3 +#define HWIO_IPA_TESTBUS_SEL_IN in_dword_masked(HWIO_IPA_TESTBUS_SEL_ADDR, \ + HWIO_IPA_TESTBUS_SEL_RMSK) +#define HWIO_IPA_TESTBUS_SEL_INM(m) in_dword_masked( \ + HWIO_IPA_TESTBUS_SEL_ADDR, \ + m) +#define HWIO_IPA_TESTBUS_SEL_OUT(v) out_dword(HWIO_IPA_TESTBUS_SEL_ADDR, v) +#define HWIO_IPA_TESTBUS_SEL_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_TESTBUS_SEL_ADDR, \ + m, \ + v, \ + HWIO_IPA_TESTBUS_SEL_IN) +#define HWIO_IPA_TESTBUS_SEL_PIPE_SELECT_BMSK 0x1f00000 +#define HWIO_IPA_TESTBUS_SEL_PIPE_SELECT_SHFT 0x14 +#define HWIO_IPA_TESTBUS_SEL_INTERNAL_BLOCK_SELECT_BMSK 0xff000 +#define HWIO_IPA_TESTBUS_SEL_INTERNAL_BLOCK_SELECT_SHFT 0xc +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_BMSK 0xff0 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_SHFT 0x4 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_RX_TESTBUS_FVAL 0x0 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_TX_TESTBUS_FVAL 0x1 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_FRAG_TESTBUS_FVAL \ + 0x2 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_UCP_TESTBUS_FVAL \ + 0x3 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_ENQUEUER_TESTBUS_FVAL \ + 0x4 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_ROUTER_TESTBUS_FVAL \ + 0x5 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_PKT_PARSER_TESTBUS_FVAL \ + 0x6 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_FILTER_NAT_TESTBUS_FVAL \ + 0x7 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_AHB2AHB_TESTBUS_FVAL \ + 0x9 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_MAXI2AXI_TESTBUS_FVAL \ + 0xa +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_DPS_DCMP_TESTBUS_FVAL \ + 0xb +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_DPS_DISPATCHER_TESTBUS_FVAL \ + 0xc +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_DPS_D_DCPH_TESTBUS_FVAL \ + 0xd +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_GSI_TEST_BUS_OUT_FVAL \ + 0xe +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_DEADBEAF_FVAL 0xf +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_MISC_TESTBUS_FVAL \ + 0x10 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_QMB_TESTBUS_0_FVAL \ + 0x12 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_QMB_TESTBUS_1_FVAL \ + 0x13 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_UC_ACKQ_TESTBUS_FVAL \ + 0x14 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_RX_ACKQ_TESTBUS_FVAL \ + 0x15 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_AGGR_TESTBUS_FVAL 0x16 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_RX_HPS_CMDQ_TESTBUS_FVAL \ + 0x17 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_DPS_CMDQ_TESTBUS_FVAL \ + 0x18 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_DPS_TX_CMDQ_TESTBUS_FVAL \ + 0x19 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_CMDQ_L_TESTBUS_FVAL \ + 0x1b +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_IPA_GSI_TESTBUS_FVAL \ + 0x1e +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_ACK_MNGR_CMDQ_TESTBUS_FVAL \ + 0x1f +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_RSRC_TESTBUS_FVAL 0x32 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_ACKMNGR_TESTBUS_FVAL \ + 0x33 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_SEQ_TESTBUS_FVAL \ + 0x34 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_DPS_SEQ_TESTBUS_FVAL \ + 0x35 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_FTCH_TESTBUS_FVAL \ + 0x36 +#define HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_DPS_FTCH_TESTBUS_FVAL \ + 0x37 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_HPS_D_DCPH_2_TESTBUS_FVAL \ + 0x38 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_NTF_TX_CMDQ_TESTBUS_FVAL \ + 0x39 +#define \ + HWIO_IPA_TESTBUS_SEL_EXTERNAL_BLOCK_SELECT_PROD_ACK_MNGR_DEBUGBUS_FVAL \ + 0x3b +#define HWIO_IPA_TESTBUS_SEL_TESTBUS_EN_BMSK 0x1 +#define HWIO_IPA_TESTBUS_SEL_TESTBUS_EN_SHFT 0x0 +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000020c) +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000020c) +#define HWIO_IPA_STEP_MODE_BREAKPOINTS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000020c) +#define HWIO_IPA_STEP_MODE_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000210) +#define HWIO_IPA_STEP_MODE_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000210) +#define HWIO_IPA_STEP_MODE_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000210) +#define HWIO_IPA_STEP_MODE_STATUS_RMSK 0xffffffff +#define HWIO_IPA_STEP_MODE_STATUS_ATTR 0x1 +#define HWIO_IPA_STEP_MODE_STATUS_IN in_dword_masked( \ + HWIO_IPA_STEP_MODE_STATUS_ADDR, \ + HWIO_IPA_STEP_MODE_STATUS_RMSK) +#define HWIO_IPA_STEP_MODE_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_STEP_MODE_STATUS_ADDR, \ + m) +#define HWIO_IPA_STEP_MODE_STATUS_HW_EN_BMSK 0xffffffff +#define HWIO_IPA_STEP_MODE_STATUS_HW_EN_SHFT 0x0 +#define HWIO_IPA_STEP_MODE_GO_ADDR (IPA_DEBUG_REG_BASE + 0x00000214) +#define HWIO_IPA_STEP_MODE_GO_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000214) +#define HWIO_IPA_STEP_MODE_GO_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000214) +#define HWIO_IPA_HW_EVENTS_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000218) +#define HWIO_IPA_HW_EVENTS_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000218) +#define HWIO_IPA_HW_EVENTS_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000218) +#define HWIO_IPA_LOG_ADDR (IPA_DEBUG_REG_BASE + 0x0000021c) +#define HWIO_IPA_LOG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000021c) +#define HWIO_IPA_LOG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000021c) +#define HWIO_IPA_LOG_RMSK 0x3ff1f2 +#define HWIO_IPA_LOG_ATTR 0x3 +#define HWIO_IPA_LOG_IN in_dword_masked(HWIO_IPA_LOG_ADDR, \ + HWIO_IPA_LOG_RMSK) +#define HWIO_IPA_LOG_INM(m) in_dword_masked(HWIO_IPA_LOG_ADDR, m) +#define HWIO_IPA_LOG_OUT(v) out_dword(HWIO_IPA_LOG_ADDR, v) +#define HWIO_IPA_LOG_OUTM(m, v) out_dword_masked_ns(HWIO_IPA_LOG_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_IN) +#define HWIO_IPA_LOG_LOG_DPL_L2_REMOVE_EN_BMSK 0x200000 +#define HWIO_IPA_LOG_LOG_DPL_L2_REMOVE_EN_SHFT 0x15 +#define HWIO_IPA_LOG_LOG_REDUCTION_EN_BMSK 0x100000 +#define HWIO_IPA_LOG_LOG_REDUCTION_EN_SHFT 0x14 +#define HWIO_IPA_LOG_LOG_LENGTH_BMSK 0xff000 +#define HWIO_IPA_LOG_LOG_LENGTH_SHFT 0xc +#define HWIO_IPA_LOG_LOG_PIPE_BMSK 0x1f0 +#define HWIO_IPA_LOG_LOG_PIPE_SHFT 0x4 +#define HWIO_IPA_LOG_LOG_EN_BMSK 0x2 +#define HWIO_IPA_LOG_LOG_EN_SHFT 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR (IPA_DEBUG_REG_BASE + 0x00000224) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000224) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000224) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR, \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_IN) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_START_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_START_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000228) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000228) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000228) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR, \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_IN) +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_START_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_ADDR_MSB_START_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000022c) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000022c) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000022c) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_ADDR, \ + HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_WRITR_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_WRITR_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000230) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000230) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000230) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_ADDR, \ + HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_WRITR_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_CMD_WRITE_PTR_MSB_WRITR_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000234) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000234) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000234) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_RMSK 0x3ffff +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR, \ + HWIO_IPA_LOG_BUF_HW_CMD_CFG_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_CMD_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_HW_CMD_CFG_IN) +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_SKIP_DDR_DMA_BMSK 0x20000 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_SKIP_DDR_DMA_SHFT 0x11 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_ENABLE_BMSK 0x10000 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_ENABLE_SHFT 0x10 +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_SIZE_BMSK 0xffff +#define HWIO_IPA_LOG_BUF_HW_CMD_CFG_SIZE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000238) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000238) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000238) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_RMSK 0xbfff3fff +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_ADDR, \ + HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_RMSK) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_SKIP_DDR_WRAP_HAPPENED_BMSK \ + 0x80000000 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_SKIP_DDR_WRAP_HAPPENED_SHFT 0x1f +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_WRITE_PTR_BMSK 0x3fff0000 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_WRITE_PTR_SHFT 0x10 +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_READ_PTR_BMSK 0x3fff +#define HWIO_IPA_LOG_BUF_HW_CMD_RAM_PTR_READ_PTR_SHFT 0x0 +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000023c) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000023c) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_LSB_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000023c) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000240) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000240) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_MSB_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000240) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000244) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000244) +#define HWIO_IPA_STEP_MODE_HFETCHER_ADDR_RESULT_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000244) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000248) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000248) +#define HWIO_IPA_STEP_MODE_HSEQ_BREAKPOINT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000248) +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000024c) +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000024c) +#define HWIO_IPA_STEP_MODE_HSEQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000024c) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000250) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000250) +#define HWIO_IPA_STEP_MODE_DSEQ_BREAKPOINT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000250) +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000254) +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000254) +#define HWIO_IPA_STEP_MODE_DSEQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000254) +#define HWIO_IPA_RX_ACKQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000258) +#define HWIO_IPA_RX_ACKQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000258) +#define HWIO_IPA_RX_ACKQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000258) +#define HWIO_IPA_RX_ACKQ_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x0000025c) +#define HWIO_IPA_RX_ACKQ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000025c) +#define HWIO_IPA_RX_ACKQ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000025c) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000260) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000260) +#define HWIO_IPA_RX_ACKQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000260) +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000264) +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000264) +#define HWIO_IPA_RX_ACKQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000264) +#define HWIO_IPA_RX_ACKQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000268) +#define HWIO_IPA_RX_ACKQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000268) +#define HWIO_IPA_RX_ACKQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000268) +#define HWIO_IPA_UC_ACKQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x0000026c) +#define HWIO_IPA_UC_ACKQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000026c) +#define HWIO_IPA_UC_ACKQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000026c) +#define HWIO_IPA_UC_ACKQ_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x00000270) +#define HWIO_IPA_UC_ACKQ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000270) +#define HWIO_IPA_UC_ACKQ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000270) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000274) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000274) +#define HWIO_IPA_UC_ACKQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000274) +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + 0x00000278) +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000278) +#define HWIO_IPA_UC_ACKQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000278) +#define HWIO_IPA_UC_ACKQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x0000027c) +#define HWIO_IPA_UC_ACKQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000027c) +#define HWIO_IPA_UC_ACKQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000027c) +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x00000280 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000280 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000280 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RMSK 0x7f +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_ATTR 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_OUTI(n, val) out_dword( \ + HWIO_IPA_RX_SPLT_CMDQ_CMD_n_ADDR(n), \ + val) +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_PKT_ENHANCED_BMSK 0x40 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_PKT_ENHANCED_SHFT 0x6 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_WR_PKT_BMSK 0x20 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_WR_PKT_SHFT 0x5 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_PKT_BMSK 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_PKT_SHFT 0x4 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_WR_CMD_BMSK 0x8 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_WR_CMD_SHFT 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_CMD_BMSK 0x4 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_RELEASE_RD_CMD_SHFT 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_POP_CMD_BMSK 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_POP_CMD_SHFT 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_CMD_n_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x00000284 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000284 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000284 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_RMSK 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ATTR 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_INI(n) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ADDR(n), \ + HWIO_IPA_RX_SPLT_CMDQ_CFG_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ADDR(n), \ + mask) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_OUTI(n, val) out_dword( \ + HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ADDR(n), \ + val) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_RX_SPLT_CMDQ_CFG_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_RX_SPLT_CMDQ_CFG_n_INI(n)) +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_BLOCK_WR_BMSK 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_BLOCK_WR_SHFT 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_BLOCK_RD_BMSK 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_CFG_n_BLOCK_RD_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x00000288 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000288 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000288 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ATTR 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_INI(n) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ADDR(n), \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ADDR(n), \ + mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_OUTI(n, val) out_dword( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ADDR(n), \ + val) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_INI(n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_CMDQ_SRC_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_CMDQ_SRC_LEN_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_0_n_CMDQ_PACKET_LEN_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x0000028c + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000028c + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000028c + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ATTR 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_INI(n) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ADDR(n), \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ADDR(n), \ + mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_OUTI(n, val) out_dword( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ADDR(n), \ + val) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_INI(n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_1_n_CMDQ_SRC_PIPE_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x00000290 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000290 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000290 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ATTR 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_INI(n) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ADDR(n), \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ADDR(n), \ + mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_OUTI(n, val) out_dword( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ADDR(n), \ + val) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_INI(n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_CMDQ_ADDR_LSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_2_n_CMDQ_ADDR_LSB_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x00000294 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000294 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000294 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ATTR 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_INI(n) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ADDR(n), \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ADDR(n), \ + mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_OUTI(n, val) out_dword( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ADDR(n), \ + val) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_INI(n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_WR_3_n_CMDQ_ADDR_MSB_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x00000298 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000298 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000298 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_INI(n) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_ADDR(n), \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_ADDR(n), \ + mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_CMDQ_SRC_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_CMDQ_SRC_LEN_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_0_n_CMDQ_PACKET_LEN_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x0000029c + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000029c + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000029c + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_INI(n) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_ADDR(n), \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_ADDR(n), \ + mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_1_n_CMDQ_SRC_PIPE_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x000002a0 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS \ + + 0x000002a0 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS \ + + 0x000002a0 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_INI(n) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_ADDR(n), \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_ADDR(n), \ + mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_CMDQ_ADDR_LSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_2_n_CMDQ_ADDR_LSB_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x000002a4 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS \ + + 0x000002a4 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS \ + + 0x000002a4 + 0x2C * \ + (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_RMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_INI(n) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_ADDR(n), \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_ADDR(n), \ + mask) +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_SPLT_CMDQ_DATA_RD_3_n_CMDQ_ADDR_MSB_F_SHFT 0x0 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x000002a8 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000002a8 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000002a8 + 0x2C * (n)) +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_RMSK 0x7f +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_MAXn 3 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_ATTR 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_INI(n) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_ADDR(n), \ + HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_RMSK) +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_ADDR(n), \ + mask) +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_DEPTH_BMSK 0x60 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_DEPTH_SHFT 0x5 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_COUNT_BMSK 0x18 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_COUNT_SHFT 0x3 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_FULL_BMSK 0x4 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_FULL_SHFT 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_EMPTY_BMSK 0x2 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_CMDQ_EMPTY_SHFT 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_STATUS_BMSK 0x1 +#define HWIO_IPA_RX_SPLT_CMDQ_STATUS_n_STATUS_SHFT 0x0 +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000035c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000035c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000035c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000360) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000360) +#define HWIO_IPA_TX_COMMANDER_CMDQ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000360) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000364) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000364) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000364) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000368) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000368) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_1_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000368) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000036c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000036c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_WR_2_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000036c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000370) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000370) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000370) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000374) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000374) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_1_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000374) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000378) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_2_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000378) +#define HWIO_IPA_TX_COMMANDER_CMDQ_DATA_RD_2_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000378) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000037c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000037c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000037c) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_RMSK 0x7 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_IN in_dword_masked( \ + HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_ADDR, \ + HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_RMSK) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_ADDR, \ + m) +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_CMDQ_FULL_BMSK 0x4 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_CMDQ_FULL_SHFT 0x2 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_CMDQ_EMPTY_BMSK 0x2 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_CMDQ_EMPTY_SHFT 0x1 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_TX_COMMANDER_CMDQ_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000380) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000380) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000380) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_RMSK 0x2f +#define HWIO_IPA_RX_HPS_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_CMD_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_OUT(v) out_dword( \ + HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR, \ + v) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_RX_HPS_CMDQ_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_RX_HPS_CMDQ_CMD_IN) +#define HWIO_IPA_RX_HPS_CMDQ_CMD_RD_REQ_BMSK 0x20 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_RD_REQ_SHFT 0x5 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_CMD_CLIENT_BMSK 0xc +#define HWIO_IPA_RX_HPS_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_CMD_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000384) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000384) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000384) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000388) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000388) +#define HWIO_IPA_RX_HPS_CMDQ_RELEASE_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000388) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + 0x0000038c) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000038c) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000038c) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_RMSK 0xf +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_CFG_WR_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR, m) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR, v) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_OUTM(m, v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CMDQ_CFG_WR_ADDR, \ + m, \ + v, \ + HWIO_IPA_RX_HPS_CMDQ_CFG_WR_IN) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_BLOCK_WR_BMSK 0xf +#define HWIO_IPA_RX_HPS_CMDQ_CFG_WR_BLOCK_WR_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000390) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000390) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000390) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_RMSK 0xf +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_IN \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_CFG_RD_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_INM(m) \ + in_dword_masked(HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR, m) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_OUT(v) \ + out_dword(HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR, v) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_OUTM(m, v) \ + out_dword_masked_ns(HWIO_IPA_RX_HPS_CMDQ_CFG_RD_ADDR, \ + m, \ + v, \ + HWIO_IPA_RX_HPS_CMDQ_CFG_RD_IN) +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_BLOCK_RD_BMSK 0xf +#define HWIO_IPA_RX_HPS_CMDQ_CFG_RD_BLOCK_RD_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000394) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000394) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000394) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000398) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000398) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000398) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000039c) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000039c) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000039c) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003a0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003a0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_WR_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003a0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003a4) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003a4) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003a4) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_CMDQ_DEST_LEN_F_BMSK 0xffff0000 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_CMDQ_DEST_LEN_F_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_CMDQ_PACKET_LEN_F_BMSK 0xffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_0_CMDQ_PACKET_LEN_F_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003a8) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003a8) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003a8) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_METADATA_F_BMSK 0xff000000 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_METADATA_F_SHFT 0x18 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_OPCODE_F_BMSK 0xff0000 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_OPCODE_F_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_FLAGS_F_BMSK 0xfc00 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_FLAGS_F_SHFT 0xa +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_ORDER_F_BMSK 0x300 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_ORDER_F_SHFT 0x8 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_SRC_PIPE_F_BMSK 0xff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_1_CMDQ_SRC_PIPE_F_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003ac) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003ac) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003ac) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_CMDQ_ADDR_LSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_2_CMDQ_ADDR_LSB_F_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003b0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003b0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003b0) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_RMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_CMDQ_ADDR_MSB_F_BMSK 0xffffffff +#define HWIO_IPA_RX_HPS_CMDQ_DATA_RD_3_CMDQ_ADDR_MSB_F_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000003b4) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003b4) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003b4) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_STATUS_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_STATUS_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_STATUS_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003b8) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003b8) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003b8) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_RMSK 0xf +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0xf +#define HWIO_IPA_RX_HPS_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 +#define HWIO_IPA_RX_HPS_SNP_ADDR (IPA_DEBUG_REG_BASE + 0x000003bc) +#define HWIO_IPA_RX_HPS_SNP_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000003bc) +#define HWIO_IPA_RX_HPS_SNP_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000003bc) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x000003c0) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003c0) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003c0) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_COUNT_ADDR, \ + HWIO_IPA_RX_HPS_CMDQ_COUNT_RMSK) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CMDQ_COUNT_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_RX_HPS_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003c4) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x000003c4) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x000003c4) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_RMSK 0xf0f0f0f +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR, \ + HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_RMSK) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_OUT(v) out_dword( \ + HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR, \ + v) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_ADDR, \ + m, \ + v, \ + HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_IN) +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_3_MIN_DEPTH_BMSK \ + 0xf000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_3_MIN_DEPTH_SHFT 0x18 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_2_MIN_DEPTH_BMSK \ + 0xf0000 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_2_MIN_DEPTH_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_1_MIN_DEPTH_BMSK 0xf00 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_1_MIN_DEPTH_SHFT 0x8 +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_0_MIN_DEPTH_BMSK 0xf +#define HWIO_IPA_RX_HPS_CLIENTS_MIN_DEPTH_0_CLIENT_0_MIN_DEPTH_SHFT 0x0 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003cc) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x000003cc) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x000003cc) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_RMSK 0xf0f0f0f +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ATTR 0x3 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_IN in_dword_masked( \ + HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR, \ + HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_RMSK) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_INM(m) in_dword_masked( \ + HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR, \ + m) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_OUT(v) out_dword( \ + HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR, \ + v) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_ADDR, \ + m, \ + v, \ + HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_IN) +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_3_MAX_DEPTH_BMSK \ + 0xf000000 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_3_MAX_DEPTH_SHFT 0x18 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_2_MAX_DEPTH_BMSK \ + 0xf0000 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_2_MAX_DEPTH_SHFT 0x10 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_1_MAX_DEPTH_BMSK 0xf00 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_1_MAX_DEPTH_SHFT 0x8 +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_0_MAX_DEPTH_BMSK 0xf +#define HWIO_IPA_RX_HPS_CLIENTS_MAX_DEPTH_0_CLIENT_0_MAX_DEPTH_SHFT 0x0 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x000003d4) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003d4) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003d4) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_RMSK 0xff +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_IN in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR, \ + HWIO_IPA_HPS_DPS_CMDQ_CMD_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_INM(m) in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR, \ + m) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_OUT(v) out_dword( \ + HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR, \ + v) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_HPS_DPS_CMDQ_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_HPS_DPS_CMDQ_CMD_IN) +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_RD_REQ_BMSK 0x80 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_RD_REQ_SHFT 0x7 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_CMD_CLIENT_BMSK 0x7c +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_CMD_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003d8) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003d8) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003d8) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003dc) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003dc) +#define HWIO_IPA_HPS_DPS_CMDQ_RELEASE_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003dc) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + 0x000003e0) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003e0) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003e0) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x000003e4) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003e4) +#define HWIO_IPA_HPS_DPS_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003e4) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003e8) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003e8) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003e8) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003ec) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003ec) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003ec) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_RMSK 0xfffff +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_IN in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ADDR, \ + HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_INM(m) in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_ADDR, \ + m) +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_REP_F_BMSK 0x80000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_REP_F_SHFT 0x13 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_BMSK 0x60000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_SHFT 0x11 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_BMSK 0x1f000 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_HPS_DPS_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_SHFT 0x0 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000003f0) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003f0) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003f0) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_RMSK 0x7f +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_IN in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_STATUS_ADDR, \ + HWIO_IPA_HPS_DPS_CMDQ_STATUS_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_STATUS_ADDR, \ + m) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x7c +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000003f4) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003f4) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003f4) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_RMSK 0x7fffff +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_IN in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_ADDR, \ + HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_INM(m) in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_ADDR, \ + m) +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0x7fffff +#define HWIO_IPA_HPS_DPS_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 +#define HWIO_IPA_HPS_DPS_SNP_ADDR (IPA_DEBUG_REG_BASE + 0x000003f8) +#define HWIO_IPA_HPS_DPS_SNP_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000003f8) +#define HWIO_IPA_HPS_DPS_SNP_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000003f8) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x000003fc) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000003fc) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000003fc) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_RMSK 0x1f +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_IN in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_COUNT_ADDR, \ + HWIO_IPA_HPS_DPS_CMDQ_COUNT_RMSK) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_INM(m) in_dword_masked( \ + HWIO_IPA_HPS_DPS_CMDQ_COUNT_ADDR, \ + m) +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_FIFO_COUNT_BMSK 0x1f +#define HWIO_IPA_HPS_DPS_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000400) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000400) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000400) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_RMSK 0x9f +#define HWIO_IPA_DPS_TX_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_IN in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR, \ + HWIO_IPA_DPS_TX_CMDQ_CMD_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_INM(m) in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR, \ + m) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_OUT(v) out_dword( \ + HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR, \ + v) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_DPS_TX_CMDQ_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_DPS_TX_CMDQ_CMD_IN) +#define HWIO_IPA_DPS_TX_CMDQ_CMD_RD_REQ_BMSK 0x80 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_RD_REQ_SHFT 0x7 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_CMD_CLIENT_BMSK 0x1c +#define HWIO_IPA_DPS_TX_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_CMD_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000404) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000404) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000404) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000408) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000408) +#define HWIO_IPA_DPS_TX_CMDQ_RELEASE_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000408) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + 0x0000040c) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000040c) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000040c) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000410) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000410) +#define HWIO_IPA_DPS_TX_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000410) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000414) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000414) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000414) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000418) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000418) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000418) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_RMSK 0xfffff +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_IN in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ADDR, \ + HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_INM(m) in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_ADDR, \ + m) +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_REP_F_BMSK 0x80000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_REP_F_SHFT 0x13 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_BMSK 0x60000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_SHFT 0x11 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_BMSK 0x1f000 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_DPS_TX_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_SHFT 0x0 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x0000041c) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000041c) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000041c) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_IN in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_STATUS_ADDR, \ + HWIO_IPA_DPS_TX_CMDQ_STATUS_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_STATUS_ADDR, \ + m) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000420) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000420) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000420) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_RMSK 0xff +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_IN in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_ADDR, \ + HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_INM(m) in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_ADDR, \ + m) +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0xff +#define HWIO_IPA_DPS_TX_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 +#define HWIO_IPA_DPS_TX_SNP_ADDR (IPA_DEBUG_REG_BASE + 0x00000424) +#define HWIO_IPA_DPS_TX_SNP_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000424) +#define HWIO_IPA_DPS_TX_SNP_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000424) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x00000428) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000428) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000428) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_IN in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_COUNT_ADDR, \ + HWIO_IPA_DPS_TX_CMDQ_COUNT_RMSK) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_INM(m) in_dword_masked( \ + HWIO_IPA_DPS_TX_CMDQ_COUNT_ADDR, \ + m) +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_DPS_TX_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000042c) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000042c) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000042c) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_RMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ADDR, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_IN) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_BITMAP_BMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_EN_BITMAP_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000430) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000430) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000430) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_RMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ADDR, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_OUTM(m, \ + v) \ + out_dword_masked_ns(HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_IN) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_BITMAP_BMSK 0x7 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_WR_N_RD_SEL_BITMAP_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000434) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000434) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000434) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_RMSK 0xfff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ADDR, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_IN) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ALL_CLI_MUX_CONCAT_BMSK 0xfff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_CLI_MUX_ALL_CLI_MUX_CONCAT_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x00000438 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000438 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000438 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_0_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x0000043c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000043c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000043c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_1_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x00000440 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000440 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000440 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_2_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x00000444 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000444 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000444 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_COMP_VAL_3_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x00000468 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000468 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000468 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_0_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x0000046c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000046c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000046c + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_1_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x00000470 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000470 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000470 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_2_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR(n) ( \ + IPA_DEBUG_REG_BASE + 0x00000474 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_PHYS(n) ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000474 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_OFFS(n) ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000474 + 0x10 * (n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_MAXn 2 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_INI(n) \ + in_dword_masked(HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR( \ + n), \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_INMI(n, \ + mask) \ + in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR(n), \ + mask) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_OUTI(n, \ + val) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR( \ + n), \ + val) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_OUTMI(n, mask, \ + val) \ + out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_INI(n)) +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_HW_SNIF_EL_MASK_VAL_3_CLI_n_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000498) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000498) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000498) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_RMSK 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR, \ + HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_RMSK) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_IN) +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_SRC_GROUP_SEL_BMSK 0x3 +#define HWIO_IPA_LOG_BUF_HW_SNIF_LEGACY_RX_SRC_GROUP_SEL_SHFT 0x0 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x000004a0) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004a0) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004a0) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_RMSK 0xff +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_IN in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR, \ + HWIO_IPA_ACKMNGR_CMDQ_CMD_RMSK) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_INM(m) in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR, \ + m) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_OUT(v) out_dword( \ + HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR, \ + v) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_ACKMNGR_CMDQ_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_ACKMNGR_CMDQ_CMD_IN) +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_RD_REQ_BMSK 0x80 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_RD_REQ_SHFT 0x7 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_CMD_CLIENT_BMSK 0x7c +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_CMD_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_ACKMNGR_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004a4) +#define HWIO_IPA_ACKMNGR_CMDQ_RELEASE_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004a4) +#define HWIO_IPA_ACKMNGR_CMDQ_RELEASE_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004a4) +#define HWIO_IPA_ACKMNGR_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004a8) +#define HWIO_IPA_ACKMNGR_CMDQ_RELEASE_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004a8) +#define HWIO_IPA_ACKMNGR_CMDQ_RELEASE_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004a8) +#define HWIO_IPA_ACKMNGR_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + 0x000004ac) +#define HWIO_IPA_ACKMNGR_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004ac) +#define HWIO_IPA_ACKMNGR_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004ac) +#define HWIO_IPA_ACKMNGR_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x000004b0) +#define HWIO_IPA_ACKMNGR_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004b0) +#define HWIO_IPA_ACKMNGR_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004b0) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004b4) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004b4) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004b4) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004b8) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004b8) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004b8) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_RMSK 0x7ffffff +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_IN in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ADDR, \ + HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_RMSK) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_INM(m) in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_ADDR, \ + m) +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_VALID_BMSK 0x4000000 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_VALID_SHFT 0x1a +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SENT_BMSK 0x2000000 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SENT_SHFT 0x19 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_ORIGIN_BMSK 0x1000000 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_ORIGIN_SHFT 0x18 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_LENGTH_BMSK 0xffff00 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_LENGTH_SHFT 0x8 +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_BMSK 0xff +#define HWIO_IPA_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_SHFT 0x0 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000004bc) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004bc) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004bc) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_IN in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_STATUS_ADDR, \ + HWIO_IPA_ACKMNGR_CMDQ_STATUS_RMSK) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_STATUS_ADDR, \ + m) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004c0) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004c0) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004c0) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_RMSK 0x3ff +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_IN in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_ADDR, \ + HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_INM(m) in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_ADDR, \ + m) +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0x3ff +#define HWIO_IPA_ACKMNGR_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x000004c4) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004c4) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004c4) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_IN in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_COUNT_ADDR, \ + HWIO_IPA_ACKMNGR_CMDQ_COUNT_RMSK) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_INM(m) in_dword_masked( \ + HWIO_IPA_ACKMNGR_CMDQ_COUNT_ADDR, \ + m) +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_ACKMNGR_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004c8) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004c8) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004c8) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_RMSK 0x3f +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_ATTR 0x3 +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IN in_dword_masked( \ + HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR, \ + HWIO_IPA_GSI_FIFO_STATUS_CTRL_RMSK) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR, \ + m) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_OUT(v) out_dword( \ + HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR, \ + v) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_FIFO_STATUS_CTRL_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_FIFO_STATUS_CTRL_IN) +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IPA_GSI_FIFO_STATUS_EN_BMSK 0x20 +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IPA_GSI_FIFO_STATUS_EN_SHFT 0x5 +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IPA_GSI_FIFO_STATUS_PORT_SEL_BMSK \ + 0x1f +#define HWIO_IPA_GSI_FIFO_STATUS_CTRL_IPA_GSI_FIFO_STATUS_PORT_SEL_SHFT \ + 0x0 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000004cc) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004cc) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004cc) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_RMSK 0xc007ffff +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_ATTR 0x1 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_IN in_dword_masked( \ + HWIO_IPA_GSI_TLV_FIFO_STATUS_ADDR, \ + HWIO_IPA_GSI_TLV_FIFO_STATUS_RMSK) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TLV_FIFO_STATUS_ADDR, \ + m) +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FSM_STATE_BMSK 0xc0000000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_FSM_STATE_SHFT 0x1e +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_EMPTY_BMSK 0x40000 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_EMPTY_SHFT 0x12 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_WR_ADDR_BMSK 0x3fe00 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_WR_ADDR_SHFT 0x9 +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_RD_ADDR_BMSK 0x1ff +#define HWIO_IPA_GSI_TLV_FIFO_STATUS_RD_ADDR_SHFT 0x0 +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004d0) +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004d0) +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004d0) +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_RMSK 0xc007ffff +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_ATTR 0x1 +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_IN in_dword_masked( \ + HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_ADDR, \ + HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_RMSK) +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_ADDR, \ + m) +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_FSM_STATE_BMSK 0xc0000000 +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_FSM_STATE_SHFT 0x1e +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_EMPTY_PUB_BMSK 0x40000 +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_EMPTY_PUB_SHFT 0x12 +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_WR_ADDR_BMSK 0x3fe00 +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_WR_ADDR_SHFT 0x9 +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_RD_ADDR_PUB_BMSK 0x1ff +#define HWIO_IPA_GSI_TLV_PUB_FIFO_STATUS_RD_ADDR_PUB_SHFT 0x0 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000004d4) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004d4) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004d4) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_RMSK 0xe01fffff +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_ATTR 0x1 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_IN in_dword_masked( \ + HWIO_IPA_GSI_AOS_FIFO_STATUS_ADDR, \ + HWIO_IPA_GSI_AOS_FIFO_STATUS_RMSK) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_GSI_AOS_FIFO_STATUS_ADDR, \ + m) +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FSM_STATE_BMSK 0xe0000000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_FSM_STATE_SHFT 0x1d +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_EMPTY_BMSK 0x100000 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_EMPTY_SHFT 0x14 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_WR_ADDR_BMSK 0xffc00 +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_WR_ADDR_SHFT 0xa +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_RD_ADDR_BMSK 0x3ff +#define HWIO_IPA_GSI_AOS_FIFO_STATUS_RD_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004d8) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004d8) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004d8) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_0_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004dc) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004dc) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004dc) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_1_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004e0) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004e0) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004e0) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_2_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004e4) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004e4) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004e4) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_3_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004e8) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004e8) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004e8) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_4_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004ec) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004ec) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004ec) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_5_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004f0) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004f0) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004f0) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_6_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004f4) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004f4) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004f4) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_ADDR, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_RMSK) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_IN) +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_COMP_VAL_7_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004f8) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004f8) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004f8) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_0_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x000004fc) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000004fc) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000004fc) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_1_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000500) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000500) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000500) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_2_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000504) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000504) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000504) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_3_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000508) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000508) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000508) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_4_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000050c) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000050c) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000050c) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_5_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000510) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000510) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000510) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_6_VALUE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000514) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000514) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000514) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_ADDR, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_RMSK) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_IN) +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_VALUE_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_SW_MASK_VAL_7_VALUE_SHFT 0x0 +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000518) +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000518) +#define HWIO_IPA_UC_RX_HND_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000518) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_ADDR (IPA_DEBUG_REG_BASE + 0x0000051c) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000051c) +#define HWIO_IPA_UC_RX_HND_CMDQ_CFG_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000051c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000520) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000520) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000520) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000524) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000524) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000524) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000528) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000528) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000528) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000052c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000052c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_WR_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000052c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000530) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000530) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000530) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000534) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000534) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000534) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000538) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000538) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000538) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000053c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000053c) +#define HWIO_IPA_UC_RX_HND_CMDQ_DATA_RD_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000053c) +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000540) +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000540) +#define HWIO_IPA_UC_RX_HND_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000540) +#define HWIO_IPA_HPS_UC2SEQ_PUSH_ADDR (IPA_DEBUG_REG_BASE + 0x00000580) +#define HWIO_IPA_HPS_UC2SEQ_PUSH_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000580) +#define HWIO_IPA_HPS_UC2SEQ_PUSH_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000580) +#define HWIO_IPA_HPS_UC2SEQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000584) +#define HWIO_IPA_HPS_UC2SEQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000584) +#define HWIO_IPA_HPS_UC2SEQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000584) +#define HWIO_IPA_HPS_SEQ2UC_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000588) +#define HWIO_IPA_HPS_SEQ2UC_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000588) +#define HWIO_IPA_HPS_SEQ2UC_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000588) +#define HWIO_IPA_HPS_SEQ2UC_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x0000058c) +#define HWIO_IPA_HPS_SEQ2UC_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000058c) +#define HWIO_IPA_HPS_SEQ2UC_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000058c) +#define HWIO_IPA_HPS_SEQ2UC_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000590) +#define HWIO_IPA_HPS_SEQ2UC_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000590) +#define HWIO_IPA_HPS_SEQ2UC_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000590) +#define HWIO_IPA_DPS_UC2SEQ_PUSH_ADDR (IPA_DEBUG_REG_BASE + 0x00000594) +#define HWIO_IPA_DPS_UC2SEQ_PUSH_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000594) +#define HWIO_IPA_DPS_UC2SEQ_PUSH_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000594) +#define HWIO_IPA_DPS_UC2SEQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x00000598) +#define HWIO_IPA_DPS_UC2SEQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000598) +#define HWIO_IPA_DPS_UC2SEQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000598) +#define HWIO_IPA_DPS_SEQ2UC_RD_ADDR (IPA_DEBUG_REG_BASE + 0x0000059c) +#define HWIO_IPA_DPS_SEQ2UC_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x0000059c) +#define HWIO_IPA_DPS_SEQ2UC_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x0000059c) +#define HWIO_IPA_DPS_SEQ2UC_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x000005a0) +#define HWIO_IPA_DPS_SEQ2UC_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000005a0) +#define HWIO_IPA_DPS_SEQ2UC_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000005a0) +#define HWIO_IPA_DPS_SEQ2UC_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x000005a4) +#define HWIO_IPA_DPS_SEQ2UC_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x000005a4) +#define HWIO_IPA_DPS_SEQ2UC_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x000005a4) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + 0x00000600) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000600) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000600) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_RMSK 0xff +#define HWIO_IPA_NTF_TX_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_IN in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR, \ + HWIO_IPA_NTF_TX_CMDQ_CMD_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_INM(m) in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR, \ + m) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_OUT(v) out_dword( \ + HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR, \ + v) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_NTF_TX_CMDQ_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_NTF_TX_CMDQ_CMD_IN) +#define HWIO_IPA_NTF_TX_CMDQ_CMD_RD_REQ_BMSK 0x80 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_RD_REQ_SHFT 0x7 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_CMD_CLIENT_BMSK 0x7c +#define HWIO_IPA_NTF_TX_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_CMD_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000604) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000604) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000604) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000608) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000608) +#define HWIO_IPA_NTF_TX_CMDQ_RELEASE_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000608) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + 0x0000060c) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000060c) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000060c) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + 0x00000610) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000610) +#define HWIO_IPA_NTF_TX_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000610) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000614) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000614) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_WR_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000614) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000618) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000618) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000618) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_RMSK 0xfffff +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ATTR 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_IN in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ADDR, \ + HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_INM(m) in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_ADDR, \ + m) +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_REP_F_BMSK 0x80000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_REP_F_SHFT 0x13 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_BMSK 0x60000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_OPCODE_F_SHFT 0x11 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_BMSK 0x1f000 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_SRC_PIPE_F_SHFT 0xc +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_BMSK 0xff0 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_SRC_ID_F_SHFT 0x4 +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_BMSK 0xf +#define HWIO_IPA_NTF_TX_CMDQ_DATA_RD_0_CMDQ_CTX_ID_F_SHFT 0x0 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + 0x0000061c) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000061c) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000061c) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_IN in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_STATUS_ADDR, \ + HWIO_IPA_NTF_TX_CMDQ_STATUS_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_STATUS_ADDR, \ + m) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000620) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000620) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000620) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_RMSK 0x7fffff +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_IN in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_ADDR, \ + HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_INM(m) in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_ADDR, \ + m) +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0x7fffff +#define HWIO_IPA_NTF_TX_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 +#define HWIO_IPA_NTF_TX_SNP_ADDR (IPA_DEBUG_REG_BASE + 0x00000624) +#define HWIO_IPA_NTF_TX_SNP_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000624) +#define HWIO_IPA_NTF_TX_SNP_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000624) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + 0x00000628) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000628) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000628) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_IN in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_COUNT_ADDR, \ + HWIO_IPA_NTF_TX_CMDQ_COUNT_RMSK) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_INM(m) in_dword_masked( \ + HWIO_IPA_NTF_TX_CMDQ_COUNT_ADDR, \ + m) +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_NTF_TX_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000700) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000700) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000700) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_RMSK 0xff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ATTR 0x3 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_IN in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR, \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_INM(m) in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR, \ + m) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_OUT(v) out_dword( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR, \ + v) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_ADDR, \ + m, \ + v, \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_IN) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_RD_REQ_BMSK 0x80 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_RD_REQ_SHFT 0x7 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_CMD_CLIENT_BMSK 0x7c +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_CMD_CLIENT_SHFT 0x2 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_POP_CMD_BMSK 0x2 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_POP_CMD_SHFT 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_WRITE_CMD_BMSK 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CMD_WRITE_CMD_SHFT 0x0 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_RELEASE_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000704) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_RELEASE_WR_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000704) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_RELEASE_WR_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000704) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_RELEASE_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000708) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_RELEASE_RD_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000708) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_RELEASE_RD_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000708) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CFG_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000070c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CFG_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000070c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CFG_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000070c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CFG_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000710) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CFG_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000710) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_CFG_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000710) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_WR_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000714) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_WR_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000714) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_WR_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000714) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000718) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000718) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000718) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_RMSK 0x7ffffff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ATTR 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_IN in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ADDR, \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_INM(m) in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_ADDR, \ + m) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_VALID_BMSK \ + 0x4000000 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_VALID_SHFT 0x1a +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SENT_BMSK 0x2000000 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SENT_SHFT 0x19 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_ORIGIN_BMSK 0x1000000 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_ORIGIN_SHFT 0x18 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_LENGTH_BMSK 0xffff00 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_LENGTH_SHFT 0x8 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_BMSK 0xff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_DATA_RD_CMDQ_SRC_ID_SHFT 0x0 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000071c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000071c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000071c) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_RMSK 0x1ff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ATTR 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_IN in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ADDR, \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_ADDR, \ + m) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_CMDQ_DEPTH_BMSK 0x1fc +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_CMDQ_DEPTH_SHFT 0x2 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_CMDQ_FULL_BMSK 0x2 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_CMDQ_FULL_SHFT 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_STATUS_BMSK 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_STATUS_SHFT 0x0 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000720) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000720) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000720) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_RMSK 0x7fffff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_ATTR 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_IN in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_ADDR, \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_INM(m) in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_ADDR, \ + m) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_BMSK 0x7fffff +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_STATUS_EMPTY_CMDQ_EMPTY_SHFT 0x0 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000724) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000724) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000724) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_RMSK 0x7f +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ATTR 0x1 +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_IN in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ADDR, \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_RMSK) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_INM(m) in_dword_masked( \ + HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_ADDR, \ + m) +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_FIFO_COUNT_BMSK 0x7f +#define HWIO_IPA_PROD_ACKMNGR_CMDQ_COUNT_FIFO_COUNT_SHFT 0x0 +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000728) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_0_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000728) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_0_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000728) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000072c) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000072c) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000072c) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000730) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000730) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000730) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000734) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_3_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000734) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_3_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000734) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_4_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000738) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_4_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000738) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_4_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000738) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_5_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000073c) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_5_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000073c) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_5_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000073c) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_6_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000740) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_6_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000740) +#define HWIO_IPA_ACKMNGR_CONTROL_CFG_6_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000740) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000744) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000744) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKINJ_CFG_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000744) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000748) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000748) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_ACKUPD_CFG_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000748) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000074c) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000074c) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000074c) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000750) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000750) +#define HWIO_IPA_ACKMNGR_SW_ACCESS_STATUS_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000750) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_0_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000754) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_0_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000754) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_0_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000754) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000758) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_1_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000758) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_1_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000758) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000075c) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_2_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x0000075c) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_2_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x0000075c) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000760) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_3_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000760) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_3_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000760) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_4_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000764) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_4_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000764) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_4_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000764) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_5_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000768) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_5_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000768) +#define HWIO_IPA_PROD_ACKMNGR_CONTROL_CFG_5_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000768) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x0000076c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000076c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKINJ_CFG_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000076c) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000770) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000770) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_ACKUPD_CFG_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000770) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000774) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_PHYS (IPA_DEBUG_REG_BASE_PHYS \ + + 0x00000774) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_CMD_OFFS (IPA_DEBUG_REG_BASE_OFFS \ + + 0x00000774) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000778) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000778) +#define HWIO_IPA_PROD_ACKMNGR_SW_ACCESS_STATUS_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000778) +#define HWIO_IPA_SPARE_REG_1_ADDR (IPA_DEBUG_REG_BASE + 0x00000780) +#define HWIO_IPA_SPARE_REG_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000780) +#define HWIO_IPA_SPARE_REG_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000780) +#define HWIO_IPA_SPARE_REG_1_RMSK 0xffffffff +#define HWIO_IPA_SPARE_REG_1_ATTR 0x3 +#define HWIO_IPA_SPARE_REG_1_IN in_dword_masked(HWIO_IPA_SPARE_REG_1_ADDR, \ + HWIO_IPA_SPARE_REG_1_RMSK) +#define HWIO_IPA_SPARE_REG_1_INM(m) in_dword_masked( \ + HWIO_IPA_SPARE_REG_1_ADDR, \ + m) +#define HWIO_IPA_SPARE_REG_1_OUT(v) out_dword(HWIO_IPA_SPARE_REG_1_ADDR, v) +#define HWIO_IPA_SPARE_REG_1_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_SPARE_REG_1_ADDR, \ + m, \ + v, \ + HWIO_IPA_SPARE_REG_1_IN) +#define HWIO_IPA_SPARE_REG_1_GENERAL_CONFIG_BMSK 0xffffffff +#define HWIO_IPA_SPARE_REG_1_GENERAL_CONFIG_SHFT 0x0 +#define HWIO_IPA_SPARE_REG_2_ADDR (IPA_DEBUG_REG_BASE + 0x00000784) +#define HWIO_IPA_SPARE_REG_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000784) +#define HWIO_IPA_SPARE_REG_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000784) +#define HWIO_IPA_SPARE_REG_2_RMSK 0xffffffff +#define HWIO_IPA_SPARE_REG_2_ATTR 0x3 +#define HWIO_IPA_SPARE_REG_2_IN in_dword_masked(HWIO_IPA_SPARE_REG_2_ADDR, \ + HWIO_IPA_SPARE_REG_2_RMSK) +#define HWIO_IPA_SPARE_REG_2_INM(m) in_dword_masked( \ + HWIO_IPA_SPARE_REG_2_ADDR, \ + m) +#define HWIO_IPA_SPARE_REG_2_OUT(v) out_dword(HWIO_IPA_SPARE_REG_2_ADDR, v) +#define HWIO_IPA_SPARE_REG_2_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_SPARE_REG_2_ADDR, \ + m, \ + v, \ + HWIO_IPA_SPARE_REG_2_IN) +#define HWIO_IPA_SPARE_REG_2_GENERAL_CONFIG_BMSK 0xffffffff +#define HWIO_IPA_SPARE_REG_2_GENERAL_CONFIG_SHFT 0x0 +#define HWIO_IPA_GSI_CONF_ADDR (IPA_DEBUG_REG_BASE + 0x00000790) +#define HWIO_IPA_GSI_CONF_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000790) +#define HWIO_IPA_GSI_CONF_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000790) +#define HWIO_IPA_GSI_CONF_RMSK 0x1 +#define HWIO_IPA_GSI_CONF_ATTR 0x3 +#define HWIO_IPA_GSI_CONF_IN in_dword_masked(HWIO_IPA_GSI_CONF_ADDR, \ + HWIO_IPA_GSI_CONF_RMSK) +#define HWIO_IPA_GSI_CONF_INM(m) in_dword_masked(HWIO_IPA_GSI_CONF_ADDR, m) +#define HWIO_IPA_GSI_CONF_OUT(v) out_dword(HWIO_IPA_GSI_CONF_ADDR, v) +#define HWIO_IPA_GSI_CONF_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_GSI_CONF_ADDR, \ + m, \ + v, \ + HWIO_IPA_GSI_CONF_IN) +#define HWIO_IPA_GSI_CONF_IPA_GSI_SELECT_BMSK 0x1 +#define HWIO_IPA_GSI_CONF_IPA_GSI_SELECT_SHFT 0x0 +#define HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x00000794 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG1_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000794 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG1_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000794 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG1_n_RMSK 0x11f0f +#define HWIO_IPA_ENDP_GSI_CFG1_n_MAXn 22 +#define HWIO_IPA_ENDP_GSI_CFG1_n_ATTR 0x3 +#define HWIO_IPA_ENDP_GSI_CFG1_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n), \ + HWIO_IPA_ENDP_GSI_CFG1_n_RMSK) +#define HWIO_IPA_ENDP_GSI_CFG1_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_GSI_CFG1_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_GSI_CFG1_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_GSI_CFG1_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_GSI_CFG1_n_INI(n)) +#define HWIO_IPA_ENDP_GSI_CFG1_n_ENDP_EN_BMSK 0x10000 +#define HWIO_IPA_ENDP_GSI_CFG1_n_ENDP_EN_SHFT 0x10 +#define HWIO_IPA_ENDP_GSI_CFG1_n_CHID_BMSK 0x1f00 +#define HWIO_IPA_ENDP_GSI_CFG1_n_CHID_SHFT 0x8 +#define HWIO_IPA_ENDP_GSI_CFG1_n_EE_BMSK 0xf +#define HWIO_IPA_ENDP_GSI_CFG1_n_EE_SHFT 0x0 +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000908) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000908) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_1_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000908) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000090c) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x0000090c) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_2_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x0000090c) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000910) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000910) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_3_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000910) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_ADDR ( \ + IPA_DEBUG_REG_BASE + 0x00000914) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_PHYS ( \ + IPA_DEBUG_REG_BASE_PHYS + 0x00000914) +#define HWIO_IPA_GSI_IPA_IF_TLV_OUT_GENERATOR_CTRL_OFFS ( \ + IPA_DEBUG_REG_BASE_OFFS + 0x00000914) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000918) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000918) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_RDY_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000918) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_ADDR (IPA_DEBUG_REG_BASE + \ + 0x0000091c) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x0000091c) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_1_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x0000091c) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_ADDR (IPA_DEBUG_REG_BASE + \ + 0x00000920) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_PHYS (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000920) +#define HWIO_IPA_GSI_IPA_IF_TLV_IN_DATA_2_OFFS (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000920) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x00000924 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000924 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000924 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_RMSK 0x1ff01ff +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_MAXn 22 +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_ATTR 0x3 +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n), \ + HWIO_IPA_ENDP_GSI_CFG_TLV_n_RMSK) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_GSI_CFG_TLV_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_GSI_CFG_TLV_n_INI(n)) +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_TLV_FIFO_SIZE_BMSK 0x1ff0000 +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_TLV_FIFO_SIZE_SHFT 0x10 +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_TLV_FIFO_START_ADDR_BMSK 0x1ff +#define HWIO_IPA_ENDP_GSI_CFG_TLV_n_TLV_FIFO_START_ADDR_SHFT 0x0 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x000009a8 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + \ + 0x000009a8 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + \ + 0x000009a8 + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_RMSK 0x1ff03ff +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_MAXn 22 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_ATTR 0x3 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n), \ + HWIO_IPA_ENDP_GSI_CFG_AOS_n_RMSK) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_GSI_CFG_AOS_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_GSI_CFG_AOS_n_INI(n)) +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_AOS_FIFO_SIZE_BMSK 0x1ff0000 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_AOS_FIFO_SIZE_SHFT 0x10 +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_AOS_FIFO_START_ADDR_BMSK 0x3ff +#define HWIO_IPA_ENDP_GSI_CFG_AOS_n_AOS_FIFO_START_ADDR_SHFT 0x0 +#define HWIO_IPA_ENDP_GSI_CFG2_n_ADDR(n) (IPA_DEBUG_REG_BASE + \ + 0x00000a2c + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG2_n_PHYS(n) (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000a2c + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG2_n_OFFS(n) (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000a2c + 0x4 * (n)) +#define HWIO_IPA_ENDP_GSI_CFG2_n_RMSK 0x8000ffff +#define HWIO_IPA_ENDP_GSI_CFG2_n_MAXn 22 +#define HWIO_IPA_ENDP_GSI_CFG2_n_ATTR 0x3 +#define HWIO_IPA_ENDP_GSI_CFG2_n_INI(n) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG2_n_ADDR(n), \ + HWIO_IPA_ENDP_GSI_CFG2_n_RMSK) +#define HWIO_IPA_ENDP_GSI_CFG2_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_ENDP_GSI_CFG2_n_ADDR(n), \ + mask) +#define HWIO_IPA_ENDP_GSI_CFG2_n_OUTI(n, val) out_dword( \ + HWIO_IPA_ENDP_GSI_CFG2_n_ADDR(n), \ + val) +#define HWIO_IPA_ENDP_GSI_CFG2_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_ENDP_GSI_CFG2_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_ENDP_GSI_CFG2_n_INI(n)) +#define HWIO_IPA_ENDP_GSI_CFG2_n_INIT_ENDP_BMSK 0x80000000 +#define HWIO_IPA_ENDP_GSI_CFG2_n_INIT_ENDP_SHFT 0x1f +#define HWIO_IPA_ENDP_GSI_CFG2_n_PUBLISH_THRESHOLD_BMSK 0xffff +#define HWIO_IPA_ENDP_GSI_CFG2_n_PUBLISH_THRESHOLD_SHFT 0x0 +#define HWIO_IPA_CTXH_CTRL_ADDR (IPA_DEBUG_REG_BASE + 0x00000afc) +#define HWIO_IPA_CTXH_CTRL_PHYS (IPA_DEBUG_REG_BASE_PHYS + 0x00000afc) +#define HWIO_IPA_CTXH_CTRL_OFFS (IPA_DEBUG_REG_BASE_OFFS + 0x00000afc) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_ADDR(m, n) (IPA_DEBUG_REG_BASE + \ + 0x00000b00 + 0x80 * (m) + \ + 0x4 * (n)) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_PHYS(m, n) (IPA_DEBUG_REG_BASE_PHYS + \ + 0x00000b00 + 0x80 * (m) + \ + 0x4 * (n)) +#define HWIO_IPA_CTX_ID_m_CTX_NUM_n_OFFS(m, n) (IPA_DEBUG_REG_BASE_OFFS + \ + 0x00000b00 + 0x80 * (m) + \ + 0x4 * (n)) +#define IPA_EE_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00043000) +#define IPA_EE_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + 0x00043000) +#define IPA_EE_REG_BASE_OFFS 0x00043000 +#define HWIO_IPA_IRQ_STTS_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000008 + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_STTS_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000008 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_STTS_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000008 + 0x1000 * (n)) +#define HWIO_IPA_IRQ_STTS_EE_n_RMSK 0x3fffffd +#define HWIO_IPA_IRQ_STTS_EE_n_MAXn 3 +#define HWIO_IPA_IRQ_STTS_EE_n_ATTR 0x1 +#define HWIO_IPA_IRQ_STTS_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_IRQ_STTS_EE_n_ADDR(n), \ + HWIO_IPA_IRQ_STTS_EE_n_RMSK) +#define HWIO_IPA_IRQ_STTS_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_IRQ_STTS_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_UC_IRQ_BMSK 0x2000000 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_UC_IRQ_SHFT 0x19 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_BMSK 0x1000000 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_SHFT 0x18 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_EE_IRQ_BMSK 0x800000 +#define HWIO_IPA_IRQ_STTS_EE_n_GSI_EE_IRQ_SHFT 0x17 +#define HWIO_IPA_IRQ_STTS_EE_n_DCMP_IRQ_BMSK 0x400000 +#define HWIO_IPA_IRQ_STTS_EE_n_DCMP_IRQ_SHFT 0x16 +#define HWIO_IPA_IRQ_STTS_EE_n_UCP_IRQ_BMSK 0x200000 +#define HWIO_IPA_IRQ_STTS_EE_n_UCP_IRQ_SHFT 0x15 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_BMSK 0x100000 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_SHFT 0x14 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_BMSK 0x80000 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_SHFT 0x13 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_RED_MARKER_BELOW_IRQ_BMSK 0x40000 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_RED_MARKER_BELOW_IRQ_SHFT 0x12 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_BMSK 0x20000 +#define HWIO_IPA_IRQ_STTS_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_SHFT 0x11 +#define HWIO_IPA_IRQ_STTS_EE_n_BAM_GSI_IDLE_IRQ_BMSK 0x10000 +#define HWIO_IPA_IRQ_STTS_EE_n_BAM_GSI_IDLE_IRQ_SHFT 0x10 +#define HWIO_IPA_IRQ_STTS_EE_n_TX_HOLB_DROP_IRQ_BMSK 0x8000 +#define HWIO_IPA_IRQ_STTS_EE_n_TX_HOLB_DROP_IRQ_SHFT 0xf +#define HWIO_IPA_IRQ_STTS_EE_n_TX_SUSPEND_IRQ_BMSK 0x4000 +#define HWIO_IPA_IRQ_STTS_EE_n_TX_SUSPEND_IRQ_SHFT 0xe +#define HWIO_IPA_IRQ_STTS_EE_n_PROC_ERR_IRQ_BMSK 0x2000 +#define HWIO_IPA_IRQ_STTS_EE_n_PROC_ERR_IRQ_SHFT 0xd +#define HWIO_IPA_IRQ_STTS_EE_n_STEP_MODE_IRQ_BMSK 0x1000 +#define HWIO_IPA_IRQ_STTS_EE_n_STEP_MODE_IRQ_SHFT 0xc +#define HWIO_IPA_IRQ_STTS_EE_n_TX_ERR_IRQ_BMSK 0x800 +#define HWIO_IPA_IRQ_STTS_EE_n_TX_ERR_IRQ_SHFT 0xb +#define HWIO_IPA_IRQ_STTS_EE_n_DEAGGR_ERR_IRQ_BMSK 0x400 +#define HWIO_IPA_IRQ_STTS_EE_n_DEAGGR_ERR_IRQ_SHFT 0xa +#define HWIO_IPA_IRQ_STTS_EE_n_RX_ERR_IRQ_BMSK 0x200 +#define HWIO_IPA_IRQ_STTS_EE_n_RX_ERR_IRQ_SHFT 0x9 +#define HWIO_IPA_IRQ_STTS_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_BMSK 0x100 +#define HWIO_IPA_IRQ_STTS_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_SHFT 0x8 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_BMSK 0x80 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_SHFT 0x7 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_BMSK 0x40 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_SHFT 0x6 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_3_BMSK 0x20 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_3_SHFT 0x5 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_2_BMSK 0x10 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_2_SHFT 0x4 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_1_BMSK 0x8 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_1_SHFT 0x3 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_0_BMSK 0x4 +#define HWIO_IPA_IRQ_STTS_EE_n_UC_IRQ_0_SHFT 0x2 +#define HWIO_IPA_IRQ_STTS_EE_n_BAD_SNOC_ACCESS_IRQ_BMSK 0x1 +#define HWIO_IPA_IRQ_STTS_EE_n_BAD_SNOC_ACCESS_IRQ_SHFT 0x0 +#define HWIO_IPA_IRQ_EN_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x0000000c + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x0000000c + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x0000000c + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EN_EE_n_RMSK 0x3fffffd +#define HWIO_IPA_IRQ_EN_EE_n_MAXn 3 +#define HWIO_IPA_IRQ_EN_EE_n_ATTR 0x3 +#define HWIO_IPA_IRQ_EN_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_IRQ_EN_EE_n_ADDR(n), \ + HWIO_IPA_IRQ_EN_EE_n_RMSK) +#define HWIO_IPA_IRQ_EN_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_IRQ_EN_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_IRQ_EN_EE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_IRQ_EN_EE_n_ADDR(n), \ + val) +#define HWIO_IPA_IRQ_EN_EE_n_OUTMI(n, mask, val) out_dword_masked_ns( \ + HWIO_IPA_IRQ_EN_EE_n_ADDR(n), \ + mask, \ + val, \ + HWIO_IPA_IRQ_EN_EE_n_INI(n)) +#define HWIO_IPA_IRQ_EN_EE_n_GSI_UC_IRQ_EN_BMSK 0x2000000 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_UC_IRQ_EN_SHFT 0x19 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_EN_BMSK 0x1000000 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_IPA_IF_TLV_RCVD_IRQ_EN_SHFT 0x18 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_EE_IRQ_EN_BMSK 0x800000 +#define HWIO_IPA_IRQ_EN_EE_n_GSI_EE_IRQ_EN_SHFT 0x17 +#define HWIO_IPA_IRQ_EN_EE_n_DCMP_IRQ_EN_BMSK 0x400000 +#define HWIO_IPA_IRQ_EN_EE_n_DCMP_IRQ_EN_SHFT 0x16 +#define HWIO_IPA_IRQ_EN_EE_n_UCP_IRQ_EN_BMSK 0x200000 +#define HWIO_IPA_IRQ_EN_EE_n_UCP_IRQ_EN_SHFT 0x15 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_EN_BMSK 0x100000 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_RED_MARKER_ABOVE_IRQ_EN_SHFT 0x14 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_EN_BMSK 0x80000 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_YELLOW_MARKER_ABOVE_IRQ_EN_SHFT 0x13 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_RED_MARKER_BELOW_IRQ_EN_BMSK 0x40000 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_RED_MARKER_BELOW_IRQ_EN_SHFT 0x12 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_EN_BMSK 0x20000 +#define HWIO_IPA_IRQ_EN_EE_n_PIPE_YELLOW_MARKER_BELOW_IRQ_EN_SHFT 0x11 +#define HWIO_IPA_IRQ_EN_EE_n_BAM_GSI_IDLE_IRQ_EN_BMSK 0x10000 +#define HWIO_IPA_IRQ_EN_EE_n_BAM_GSI_IDLE_IRQ_EN_SHFT 0x10 +#define HWIO_IPA_IRQ_EN_EE_n_TX_HOLB_DROP_IRQ_EN_BMSK 0x8000 +#define HWIO_IPA_IRQ_EN_EE_n_TX_HOLB_DROP_IRQ_EN_SHFT 0xf +#define HWIO_IPA_IRQ_EN_EE_n_TX_SUSPEND_IRQ_EN_BMSK 0x4000 +#define HWIO_IPA_IRQ_EN_EE_n_TX_SUSPEND_IRQ_EN_SHFT 0xe +#define HWIO_IPA_IRQ_EN_EE_n_PROC_ERR_IRQ_EN_BMSK 0x2000 +#define HWIO_IPA_IRQ_EN_EE_n_PROC_ERR_IRQ_EN_SHFT 0xd +#define HWIO_IPA_IRQ_EN_EE_n_STEP_MODE_IRQ_EN_BMSK 0x1000 +#define HWIO_IPA_IRQ_EN_EE_n_STEP_MODE_IRQ_EN_SHFT 0xc +#define HWIO_IPA_IRQ_EN_EE_n_TX_ERR_IRQ_EN_BMSK 0x800 +#define HWIO_IPA_IRQ_EN_EE_n_TX_ERR_IRQ_EN_SHFT 0xb +#define HWIO_IPA_IRQ_EN_EE_n_DEAGGR_ERR_IRQ_EN_BMSK 0x400 +#define HWIO_IPA_IRQ_EN_EE_n_DEAGGR_ERR_IRQ_EN_SHFT 0xa +#define HWIO_IPA_IRQ_EN_EE_n_RX_ERR_IRQ_EN_BMSK 0x200 +#define HWIO_IPA_IRQ_EN_EE_n_RX_ERR_IRQ_EN_SHFT 0x9 +#define HWIO_IPA_IRQ_EN_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_EN_BMSK 0x100 +#define HWIO_IPA_IRQ_EN_EE_n_PROC_TO_UC_ACK_Q_NOT_EMPTY_IRQ_EN_SHFT 0x8 +#define HWIO_IPA_IRQ_EN_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_EN_BMSK 0x80 +#define HWIO_IPA_IRQ_EN_EE_n_UC_RX_CMD_Q_NOT_FULL_IRQ_EN_SHFT 0x7 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_EN_BMSK 0x40 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IN_Q_NOT_EMPTY_IRQ_EN_SHFT 0x6 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_3_IRQ_EN_BMSK 0x20 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_3_IRQ_EN_SHFT 0x5 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_2_IRQ_EN_BMSK 0x10 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_2_IRQ_EN_SHFT 0x4 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_1_IRQ_EN_BMSK 0x8 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_1_IRQ_EN_SHFT 0x3 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_0_IRQ_EN_BMSK 0x4 +#define HWIO_IPA_IRQ_EN_EE_n_UC_IRQ_0_IRQ_EN_SHFT 0x2 +#define HWIO_IPA_IRQ_EN_EE_n_BAD_SNOC_ACCESS_IRQ_EN_BMSK 0x1 +#define HWIO_IPA_IRQ_EN_EE_n_BAD_SNOC_ACCESS_IRQ_EN_SHFT 0x0 +#define HWIO_IPA_IRQ_CLR_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000010 + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_CLR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x00000010 + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_CLR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x00000010 + \ + 0x1000 * (n)) +#define HWIO_IPA_SNOC_FEC_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000018 + \ + 0x1000 * (n)) +#define HWIO_IPA_SNOC_FEC_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000018 + 0x1000 * (n)) +#define HWIO_IPA_SNOC_FEC_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000018 + 0x1000 * (n)) +#define HWIO_IPA_SNOC_FEC_EE_n_RMSK 0x8000f1ff +#define HWIO_IPA_SNOC_FEC_EE_n_MAXn 3 +#define HWIO_IPA_SNOC_FEC_EE_n_ATTR 0x1 +#define HWIO_IPA_SNOC_FEC_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_SNOC_FEC_EE_n_ADDR(n), \ + HWIO_IPA_SNOC_FEC_EE_n_RMSK) +#define HWIO_IPA_SNOC_FEC_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_SNOC_FEC_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_SNOC_FEC_EE_n_READ_NOT_WRITE_BMSK 0x80000000 +#define HWIO_IPA_SNOC_FEC_EE_n_READ_NOT_WRITE_SHFT 0x1f +#define HWIO_IPA_SNOC_FEC_EE_n_TID_BMSK 0xf000 +#define HWIO_IPA_SNOC_FEC_EE_n_TID_SHFT 0xc +#define HWIO_IPA_SNOC_FEC_EE_n_QMB_INDEX_BMSK 0x100 +#define HWIO_IPA_SNOC_FEC_EE_n_QMB_INDEX_SHFT 0x8 +#define HWIO_IPA_SNOC_FEC_EE_n_CLIENT_BMSK 0xff +#define HWIO_IPA_SNOC_FEC_EE_n_CLIENT_SHFT 0x0 +#define HWIO_IPA_IRQ_EE_UC_n_ADDR(n) (IPA_EE_REG_BASE + 0x0000001c + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EE_UC_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + 0x0000001c + \ + 0x1000 * (n)) +#define HWIO_IPA_IRQ_EE_UC_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + 0x0000001c + \ + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000020 + \ + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000020 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000020 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_EE_n_RMSK 0xffffffff +#define HWIO_IPA_FEC_ADDR_EE_n_MAXn 3 +#define HWIO_IPA_FEC_ADDR_EE_n_ATTR 0x1 +#define HWIO_IPA_FEC_ADDR_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_FEC_ADDR_EE_n_ADDR(n), \ + HWIO_IPA_FEC_ADDR_EE_n_RMSK) +#define HWIO_IPA_FEC_ADDR_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_FEC_ADDR_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_FEC_ADDR_EE_n_ADDR_BMSK 0xffffffff +#define HWIO_IPA_FEC_ADDR_EE_n_ADDR_SHFT 0x0 +#define HWIO_IPA_FEC_ADDR_MSB_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000024 + \ + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_MSB_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000024 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ADDR_MSB_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000024 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ATTR_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00000028 + \ + 0x1000 * (n)) +#define HWIO_IPA_FEC_ATTR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000028 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ATTR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000028 + 0x1000 * (n)) +#define HWIO_IPA_FEC_ATTR_EE_n_RMSK 0xffffffff +#define HWIO_IPA_FEC_ATTR_EE_n_MAXn 3 +#define HWIO_IPA_FEC_ATTR_EE_n_ATTR 0x1 +#define HWIO_IPA_FEC_ATTR_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_FEC_ATTR_EE_n_ADDR(n), \ + HWIO_IPA_FEC_ATTR_EE_n_RMSK) +#define HWIO_IPA_FEC_ATTR_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_FEC_ATTR_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_FEC_ATTR_EE_n_MISC2_BMSK 0xffffe000 +#define HWIO_IPA_FEC_ATTR_EE_n_MISC2_SHFT 0xd +#define HWIO_IPA_FEC_ATTR_EE_n_PIPE_NUM_BMSK 0x1f00 +#define HWIO_IPA_FEC_ATTR_EE_n_PIPE_NUM_SHFT 0x8 +#define HWIO_IPA_FEC_ATTR_EE_n_MISC1_BMSK 0xc0 +#define HWIO_IPA_FEC_ATTR_EE_n_MISC1_SHFT 0x6 +#define HWIO_IPA_FEC_ATTR_EE_n_OPCODE_BMSK 0x3f +#define HWIO_IPA_FEC_ATTR_EE_n_OPCODE_SHFT 0x0 +#define HWIO_IPA_MBIM_DEAGGR_FEC_ATTR_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x00000028 + 0x1000 * \ + (n)) +#define HWIO_IPA_MBIM_DEAGGR_FEC_ATTR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000028 + 0x1000 * \ + (n)) +#define HWIO_IPA_MBIM_DEAGGR_FEC_ATTR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000028 + 0x1000 * \ + (n)) +#define HWIO_IPA_GEN_DEAGGR_FEC_ATTR_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x00000028 + 0x1000 * \ + (n)) +#define HWIO_IPA_GEN_DEAGGR_FEC_ATTR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000028 + 0x1000 * \ + (n)) +#define HWIO_IPA_GEN_DEAGGR_FEC_ATTR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000028 + 0x1000 * \ + (n)) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x00000030 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000030 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000030 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_RMSK 0x7fffff +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_MAXn 3 +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_ATTR 0x1 +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_ADDR(n), \ + HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_RMSK) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_ENDPOINTS_BMSK 0x7fffff +#define HWIO_IPA_SUSPEND_IRQ_INFO_EE_n_ENDPOINTS_SHFT 0x0 +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x00000034 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000034 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000034 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_RMSK 0x7fffff +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_MAXn 3 +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ATTR 0x3 +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ADDR(n), \ + HWIO_IPA_SUSPEND_IRQ_EN_EE_n_RMSK) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_OUTI(n, val) out_dword( \ + HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ADDR(n), \ + val) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_OUTMI(n, mask, \ + val) out_dword_masked_ns( \ + HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ADDR( \ + n), \ + mask, \ + val, \ + HWIO_IPA_SUSPEND_IRQ_EN_EE_n_INI(n)) +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ENDPOINTS_BMSK 0x7fffff +#define HWIO_IPA_SUSPEND_IRQ_EN_EE_n_ENDPOINTS_SHFT 0x0 +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x00000038 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000038 + 0x1000 * (n)) +#define HWIO_IPA_SUSPEND_IRQ_CLR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000038 + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x0000003c + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x0000003c + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x0000003c + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_RMSK 0x7fffff +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_MAXn 3 +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_ATTR 0x1 +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_INI(n) in_dword_masked( \ + HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_ADDR(n), \ + HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_RMSK) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_INMI(n, mask) in_dword_masked( \ + HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_ADDR(n), \ + mask) +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_ENDPOINTS_BMSK 0x7fffff +#define HWIO_IPA_HOLB_DROP_IRQ_INFO_EE_n_ENDPOINTS_SHFT 0x0 +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x00000040 + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000040 + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_EN_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000040 + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_ADDR(n) (IPA_EE_REG_BASE + \ + 0x00000044 + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00000044 + 0x1000 * (n)) +#define HWIO_IPA_HOLB_DROP_IRQ_CLR_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00000044 + 0x1000 * (n)) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_ADDR (IPA_EE_REG_BASE + 0x000010a0) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010a0) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010a0) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_ADDR, \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_RMSK) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_IN) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_START_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_START_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_ADDR (IPA_EE_REG_BASE + \ + 0x000010a4) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010a4) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010a4) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_ADDR, \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_RMSK) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_IN) +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_START_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_ADDR_MSB_START_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_ADDR (IPA_EE_REG_BASE + \ + 0x000010a8) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010a8) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010a8) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_ADDR, \ + HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_RMSK) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_WRITE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_WRITE_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_ADDR (IPA_EE_REG_BASE + \ + 0x000010ac) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010ac) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010ac) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_ADDR, \ + HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_RMSK) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_WRITE_ADDR_BMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_WRITE_PTR_MSB_WRITE_ADDR_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_STATUS_CFG_ADDR (IPA_EE_REG_BASE + 0x000010b0) +#define HWIO_IPA_LOG_BUF_STATUS_CFG_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010b0) +#define HWIO_IPA_LOG_BUF_STATUS_CFG_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010b0) +#define HWIO_IPA_LOG_BUF_STATUS_CFG_RMSK 0x1ffff +#define HWIO_IPA_LOG_BUF_STATUS_CFG_ATTR 0x3 +#define HWIO_IPA_LOG_BUF_STATUS_CFG_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_CFG_ADDR, \ + HWIO_IPA_LOG_BUF_STATUS_CFG_RMSK) +#define HWIO_IPA_LOG_BUF_STATUS_CFG_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_CFG_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_STATUS_CFG_OUT(v) out_dword( \ + HWIO_IPA_LOG_BUF_STATUS_CFG_ADDR, \ + v) +#define HWIO_IPA_LOG_BUF_STATUS_CFG_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_LOG_BUF_STATUS_CFG_ADDR, \ + m, \ + v, \ + HWIO_IPA_LOG_BUF_STATUS_CFG_IN) +#define HWIO_IPA_LOG_BUF_STATUS_CFG_ENABLE_BMSK 0x10000 +#define HWIO_IPA_LOG_BUF_STATUS_CFG_ENABLE_SHFT 0x10 +#define HWIO_IPA_LOG_BUF_STATUS_CFG_SIZE_BMSK 0xffff +#define HWIO_IPA_LOG_BUF_STATUS_CFG_SIZE_SHFT 0x0 +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_ADDR (IPA_EE_REG_BASE + 0x000010b4) +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010b4) +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010b4) +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_RMSK 0xffffffff +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_ATTR 0x1 +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_IN in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_ADDR, \ + HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_RMSK) +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_INM(m) in_dword_masked( \ + HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_ADDR, \ + m) +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_WRITE_PTR_BMSK 0xffff0000 +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_WRITE_PTR_SHFT 0x10 +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_READ_PTR_BMSK 0xffff +#define HWIO_IPA_LOG_BUF_STATUS_RAM_PTR_READ_PTR_SHFT 0x0 +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_0_ADDR (IPA_EE_REG_BASE + \ + 0x000010c0) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_0_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010c0) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_0_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010c0) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_1_ADDR (IPA_EE_REG_BASE + \ + 0x000010c4) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_1_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010c4) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_1_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010c4) +#define HWIO_IPA_SECURED_PIPES_ADDR (IPA_EE_REG_BASE + 0x000010d0) +#define HWIO_IPA_SECURED_PIPES_PHYS (IPA_EE_REG_BASE_PHYS + 0x000010d0) +#define HWIO_IPA_SECURED_PIPES_OFFS (IPA_EE_REG_BASE_OFFS + 0x000010d0) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_CFG_ADDR (IPA_EE_REG_BASE + \ + 0x000010d4) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_CFG_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000010d4) +#define HWIO_IPA_LTE_DECIPH_INIT_VALUES_CFG_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000010d4) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_ADDR (IPA_EE_REG_BASE + \ + 0x00001200) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x00001200) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__CONTROL_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x00001200) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_ADDR (IPA_EE_REG_BASE + \ + 0x00001204) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x00001204) +#define HWIO_IPA_UC_REGS_INSIDE_IPA__NMI_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x00001204) +#define HWIO_IPA_SET_UC_IRQ_EE_n_ADDR(n) (IPA_EE_REG_BASE + 0x00002048 + \ + 0x4 * (n)) +#define HWIO_IPA_SET_UC_IRQ_EE_n_PHYS(n) (IPA_EE_REG_BASE_PHYS + \ + 0x00002048 + 0x4 * (n)) +#define HWIO_IPA_SET_UC_IRQ_EE_n_OFFS(n) (IPA_EE_REG_BASE_OFFS + \ + 0x00002048 + 0x4 * (n)) +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_ADDR (IPA_EE_REG_BASE + 0x00002058) +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x00002058) +#define HWIO_IPA_SET_UC_IRQ_ALL_EES_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x00002058) +#define HWIO_IPA_UCP_RESUME_ADDR (IPA_EE_REG_BASE + 0x000030a0) +#define HWIO_IPA_UCP_RESUME_PHYS (IPA_EE_REG_BASE_PHYS + 0x000030a0) +#define HWIO_IPA_UCP_RESUME_OFFS (IPA_EE_REG_BASE_OFFS + 0x000030a0) +#define HWIO_IPA_PROC_UCP_CFG_ADDR (IPA_EE_REG_BASE + 0x000030a4) +#define HWIO_IPA_PROC_UCP_CFG_PHYS (IPA_EE_REG_BASE_PHYS + 0x000030a4) +#define HWIO_IPA_PROC_UCP_CFG_OFFS (IPA_EE_REG_BASE_OFFS + 0x000030a4) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_ADDR (IPA_EE_REG_BASE + \ + 0x000030a8) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000030a8) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_0_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000030a8) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_ADDR (IPA_EE_REG_BASE + \ + 0x000030ac) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000030ac) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_1_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000030ac) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_ADDR (IPA_EE_REG_BASE + \ + 0x000030b0) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_PHYS (IPA_EE_REG_BASE_PHYS + \ + 0x000030b0) +#define HWIO_IPA_UC_PKT_PROCESS_BASE_ADDR_2_OFFS (IPA_EE_REG_BASE_OFFS + \ + 0x000030b0) +#define IPA_UC_IPA_UC_PER_REG_BASE (IPA_0_IPA_WRAPPER_BASE + 0x00070000) +#define IPA_UC_IPA_UC_PER_REG_BASE_PHYS (IPA_0_IPA_WRAPPER_BASE_PHYS + \ + 0x00070000) +#define IPA_UC_IPA_UC_PER_REG_BASE_OFFS 0x00070000 +#define HWIO_IPA_UC_STATUS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000000) +#define HWIO_IPA_UC_STATUS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000000) +#define HWIO_IPA_UC_STATUS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000000) +#define HWIO_IPA_UC_CONTROL_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000004) +#define HWIO_IPA_UC_CONTROL_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000004) +#define HWIO_IPA_UC_CONTROL_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000004) +#define HWIO_IPA_UC_BASE_ADDR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000008) +#define HWIO_IPA_UC_BASE_ADDR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000008) +#define HWIO_IPA_UC_BASE_ADDR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000008) +#define HWIO_IPA_UC_BASE_ADDR_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x0000000c) +#define HWIO_IPA_UC_BASE_ADDR_MSB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x0000000c) +#define HWIO_IPA_UC_BASE_ADDR_MSB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x0000000c) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000010) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000010) +#define HWIO_IPA_UC_SYS_BUS_ATTRIB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000010) +#define HWIO_IPA_UC_PEND_IRQ_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000014) +#define HWIO_IPA_UC_PEND_IRQ_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000014) +#define HWIO_IPA_UC_PEND_IRQ_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000014) +#define HWIO_IPA_UC_TRACE_BUFFER_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000018) +#define HWIO_IPA_UC_TRACE_BUFFER_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000018) +#define HWIO_IPA_UC_TRACE_BUFFER_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000018) +#define HWIO_IPA_UC_PC_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x0000001c) +#define HWIO_IPA_UC_PC_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000001c) +#define HWIO_IPA_UC_PC_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000001c) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE \ + + 0x00000024) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_PHYS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000024) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_LSB_OFFS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000024) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE \ + + 0x00000028) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_PHYS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000028) +#define HWIO_IPA_UC_VUIC_INT_ADDRESS_MSB_OFFS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000028) +#define HWIO_IPA_UC_QMB_SYS_ADDR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000100) +#define HWIO_IPA_UC_QMB_SYS_ADDR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000100) +#define HWIO_IPA_UC_QMB_SYS_ADDR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000100) +#define HWIO_IPA_UC_QMB_SYS_ADDR_RMSK 0xffffffff +#define HWIO_IPA_UC_QMB_SYS_ADDR_ATTR 0x3 +#define HWIO_IPA_UC_QMB_SYS_ADDR_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_SYS_ADDR_ADDR, \ + HWIO_IPA_UC_QMB_SYS_ADDR_RMSK) +#define HWIO_IPA_UC_QMB_SYS_ADDR_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_SYS_ADDR_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_SYS_ADDR_OUT(v) out_dword( \ + HWIO_IPA_UC_QMB_SYS_ADDR_ADDR, \ + v) +#define HWIO_IPA_UC_QMB_SYS_ADDR_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_UC_QMB_SYS_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_UC_QMB_SYS_ADDR_IN) +#define HWIO_IPA_UC_QMB_SYS_ADDR_ADDR_BMSK 0xffffffff +#define HWIO_IPA_UC_QMB_SYS_ADDR_ADDR_SHFT 0x0 +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000104) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS \ + + 0x00000104) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS \ + + 0x00000104) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_RMSK 0xffffffff +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ATTR 0x3 +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR, \ + HWIO_IPA_UC_QMB_SYS_ADDR_MSB_RMSK) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_OUT(v) out_dword( \ + HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR, \ + v) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR, \ + m, \ + v, \ + HWIO_IPA_UC_QMB_SYS_ADDR_MSB_IN) +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR_MSB_BMSK 0xffffffff +#define HWIO_IPA_UC_QMB_SYS_ADDR_MSB_ADDR_MSB_SHFT 0x0 +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000108) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000108) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000108) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_RMSK 0x1ffff +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_ATTR 0x3 +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR, \ + HWIO_IPA_UC_QMB_LOCAL_ADDR_RMSK) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_OUT(v) out_dword( \ + HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR, \ + v) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR, \ + m, \ + v, \ + HWIO_IPA_UC_QMB_LOCAL_ADDR_IN) +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR_BMSK 0x1ffff +#define HWIO_IPA_UC_QMB_LOCAL_ADDR_ADDR_SHFT 0x0 +#define HWIO_IPA_UC_QMB_LENGTH_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x0000010c) +#define HWIO_IPA_UC_QMB_LENGTH_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x0000010c) +#define HWIO_IPA_UC_QMB_LENGTH_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x0000010c) +#define HWIO_IPA_UC_QMB_LENGTH_RMSK 0x7f +#define HWIO_IPA_UC_QMB_LENGTH_ATTR 0x3 +#define HWIO_IPA_UC_QMB_LENGTH_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_LENGTH_ADDR, \ + HWIO_IPA_UC_QMB_LENGTH_RMSK) +#define HWIO_IPA_UC_QMB_LENGTH_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_LENGTH_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_LENGTH_OUT(v) out_dword( \ + HWIO_IPA_UC_QMB_LENGTH_ADDR, \ + v) +#define HWIO_IPA_UC_QMB_LENGTH_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_UC_QMB_LENGTH_ADDR, \ + m, \ + v, \ + HWIO_IPA_UC_QMB_LENGTH_IN) +#define HWIO_IPA_UC_QMB_LENGTH_LENGTH_BMSK 0x7f +#define HWIO_IPA_UC_QMB_LENGTH_LENGTH_SHFT 0x0 +#define HWIO_IPA_UC_QMB_TRIGGER_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000110) +#define HWIO_IPA_UC_QMB_TRIGGER_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000110) +#define HWIO_IPA_UC_QMB_TRIGGER_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000110) +#define HWIO_IPA_UC_QMB_TRIGGER_RMSK 0x31 +#define HWIO_IPA_UC_QMB_TRIGGER_ATTR 0x3 +#define HWIO_IPA_UC_QMB_TRIGGER_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_TRIGGER_ADDR, \ + HWIO_IPA_UC_QMB_TRIGGER_RMSK) +#define HWIO_IPA_UC_QMB_TRIGGER_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_TRIGGER_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_TRIGGER_OUT(v) out_dword( \ + HWIO_IPA_UC_QMB_TRIGGER_ADDR, \ + v) +#define HWIO_IPA_UC_QMB_TRIGGER_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_UC_QMB_TRIGGER_ADDR, \ + m, \ + v, \ + HWIO_IPA_UC_QMB_TRIGGER_IN) +#define HWIO_IPA_UC_QMB_TRIGGER_POSTING_BMSK 0x30 +#define HWIO_IPA_UC_QMB_TRIGGER_POSTING_SHFT 0x4 +#define HWIO_IPA_UC_QMB_TRIGGER_POSTING_DATA_POSTED_FVAL 0x0 +#define HWIO_IPA_UC_QMB_TRIGGER_POSTING_RESP_POSTED_FVAL 0x1 +#define HWIO_IPA_UC_QMB_TRIGGER_POSTING_DATA_COMPLETE_FVAL 0x2 +#define HWIO_IPA_UC_QMB_TRIGGER_POSTING_RESP_COMPLETE_FVAL 0x3 +#define HWIO_IPA_UC_QMB_TRIGGER_DIRECTION_BMSK 0x1 +#define HWIO_IPA_UC_QMB_TRIGGER_DIRECTION_SHFT 0x0 +#define HWIO_IPA_UC_QMB_TRIGGER_DIRECTION_READ_FVAL 0x0 +#define HWIO_IPA_UC_QMB_TRIGGER_DIRECTION_WRITE_FVAL 0x1 +#define HWIO_IPA_UC_QMB_PENDING_TID_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000114) +#define HWIO_IPA_UC_QMB_PENDING_TID_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS \ + + 0x00000114) +#define HWIO_IPA_UC_QMB_PENDING_TID_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS \ + + 0x00000114) +#define HWIO_IPA_UC_QMB_PENDING_TID_RMSK 0x11113f +#define HWIO_IPA_UC_QMB_PENDING_TID_ATTR 0x1 +#define HWIO_IPA_UC_QMB_PENDING_TID_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_PENDING_TID_ADDR, \ + HWIO_IPA_UC_QMB_PENDING_TID_RMSK) +#define HWIO_IPA_UC_QMB_PENDING_TID_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_PENDING_TID_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_SECURITY_BMSK 0x100000 +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_SECURITY_SHFT 0x14 +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_MAX_COMP_BMSK 0x10000 +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_MAX_COMP_SHFT 0x10 +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_MAX_OS_BMSK 0x1000 +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_MAX_OS_SHFT 0xc +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_BUS_BMSK 0x100 +#define HWIO_IPA_UC_QMB_PENDING_TID_ERROR_BUS_SHFT 0x8 +#define HWIO_IPA_UC_QMB_PENDING_TID_TID_BMSK 0x3f +#define HWIO_IPA_UC_QMB_PENDING_TID_TID_SHFT 0x0 +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_ADDR (IPA_UC_IPA_UC_PER_REG_BASE \ + + 0x00000118) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PHYS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000118) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_OFFS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000118) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_ADDR ( \ + IPA_UC_IPA_UC_PER_REG_BASE + 0x0000011c) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_PHYS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x0000011c) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_OFFS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x0000011c) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_RMSK 0x113f +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_ATTR 0x1 +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_ADDR, \ + HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_RMSK) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_VALID_BMSK 0x1000 +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_VALID_SHFT 0xc +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_ERROR_BMSK 0x100 +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_ERROR_SHFT 0x8 +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_TID_BMSK 0x3f +#define HWIO_IPA_UC_QMB_COMPLETED_RD_FIFO_PEEK_TID_SHFT 0x0 +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_ADDR (IPA_UC_IPA_UC_PER_REG_BASE \ + + 0x00000120) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PHYS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000120) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_OFFS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000120) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_ADDR ( \ + IPA_UC_IPA_UC_PER_REG_BASE + 0x00000124) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_PHYS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000124) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_OFFS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000124) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_RMSK 0x113f +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_ATTR 0x1 +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_ADDR, \ + HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_RMSK) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_VALID_BMSK 0x1000 +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_VALID_SHFT 0xc +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_ERROR_BMSK 0x100 +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_ERROR_SHFT 0x8 +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_TID_BMSK 0x3f +#define HWIO_IPA_UC_QMB_COMPLETED_WR_FIFO_PEEK_TID_SHFT 0x0 +#define HWIO_IPA_UC_QMB_MISC_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000128) +#define HWIO_IPA_UC_QMB_MISC_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000128) +#define HWIO_IPA_UC_QMB_MISC_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000128) +#define HWIO_IPA_UC_QMB_MISC_RMSK 0xf11333ff +#define HWIO_IPA_UC_QMB_MISC_ATTR 0x3 +#define HWIO_IPA_UC_QMB_MISC_IN in_dword_masked(HWIO_IPA_UC_QMB_MISC_ADDR, \ + HWIO_IPA_UC_QMB_MISC_RMSK) +#define HWIO_IPA_UC_QMB_MISC_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_MISC_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_MISC_OUT(v) out_dword(HWIO_IPA_UC_QMB_MISC_ADDR, v) +#define HWIO_IPA_UC_QMB_MISC_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_UC_QMB_MISC_ADDR, \ + m, \ + v, \ + HWIO_IPA_UC_QMB_MISC_IN) +#define HWIO_IPA_UC_QMB_MISC_QMB_HREADY_BCR_BMSK 0x80000000 +#define HWIO_IPA_UC_QMB_MISC_QMB_HREADY_BCR_SHFT 0x1f +#define HWIO_IPA_UC_QMB_MISC_POSTED_STALL_BMSK 0x40000000 +#define HWIO_IPA_UC_QMB_MISC_POSTED_STALL_SHFT 0x1e +#define HWIO_IPA_UC_QMB_MISC_IRQ_COAL_BMSK 0x20000000 +#define HWIO_IPA_UC_QMB_MISC_IRQ_COAL_SHFT 0x1d +#define HWIO_IPA_UC_QMB_MISC_SWAP_BMSK 0x10000000 +#define HWIO_IPA_UC_QMB_MISC_SWAP_SHFT 0x1c +#define HWIO_IPA_UC_QMB_MISC_OOOWR_BMSK 0x1000000 +#define HWIO_IPA_UC_QMB_MISC_OOOWR_SHFT 0x18 +#define HWIO_IPA_UC_QMB_MISC_OOORD_BMSK 0x100000 +#define HWIO_IPA_UC_QMB_MISC_OOORD_SHFT 0x14 +#define HWIO_IPA_UC_QMB_MISC_WR_PRIORITY_BMSK 0x30000 +#define HWIO_IPA_UC_QMB_MISC_WR_PRIORITY_SHFT 0x10 +#define HWIO_IPA_UC_QMB_MISC_RD_PRIORITY_BMSK 0x3000 +#define HWIO_IPA_UC_QMB_MISC_RD_PRIORITY_SHFT 0xc +#define HWIO_IPA_UC_QMB_MISC_USER_BMSK 0x3ff +#define HWIO_IPA_UC_QMB_MISC_USER_SHFT 0x0 +#define HWIO_IPA_UC_QMB_STATUS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x0000012c) +#define HWIO_IPA_UC_QMB_STATUS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x0000012c) +#define HWIO_IPA_UC_QMB_STATUS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x0000012c) +#define HWIO_IPA_UC_QMB_STATUS_RMSK 0x1fff1fff +#define HWIO_IPA_UC_QMB_STATUS_ATTR 0x1 +#define HWIO_IPA_UC_QMB_STATUS_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_STATUS_ADDR, \ + HWIO_IPA_UC_QMB_STATUS_RMSK) +#define HWIO_IPA_UC_QMB_STATUS_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_STATUS_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_WR_FIFO_FULL_BMSK 0x10000000 +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_WR_FIFO_FULL_SHFT 0x1c +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_WR_CNT_BMSK 0xf000000 +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_WR_CNT_SHFT 0x18 +#define HWIO_IPA_UC_QMB_STATUS_OUTSTANDING_WR_CNT_BMSK 0xf00000 +#define HWIO_IPA_UC_QMB_STATUS_OUTSTANDING_WR_CNT_SHFT 0x14 +#define HWIO_IPA_UC_QMB_STATUS_MAX_OUTSTANDING_WR_BMSK 0xf0000 +#define HWIO_IPA_UC_QMB_STATUS_MAX_OUTSTANDING_WR_SHFT 0x10 +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_RD_FIFO_FULL_BMSK 0x1000 +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_RD_FIFO_FULL_SHFT 0xc +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_RD_CNT_BMSK 0xf00 +#define HWIO_IPA_UC_QMB_STATUS_COMPLETED_RD_CNT_SHFT 0x8 +#define HWIO_IPA_UC_QMB_STATUS_OUTSTANDING_RD_CNT_BMSK 0xf0 +#define HWIO_IPA_UC_QMB_STATUS_OUTSTANDING_RD_CNT_SHFT 0x4 +#define HWIO_IPA_UC_QMB_STATUS_MAX_OUTSTANDING_RD_BMSK 0xf +#define HWIO_IPA_UC_QMB_STATUS_MAX_OUTSTANDING_RD_SHFT 0x0 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000130) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000130) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000130) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_RMSK 0x1117 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_ATTR 0x3 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_IN in_dword_masked( \ + HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR, \ + HWIO_IPA_UC_QMB_BUS_ATTRIB_RMSK) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_INM(m) in_dword_masked( \ + HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR, \ + m) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_OUT(v) out_dword( \ + HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR, \ + v) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_OUTM(m, v) out_dword_masked_ns( \ + HWIO_IPA_UC_QMB_BUS_ATTRIB_ADDR, \ + m, \ + v, \ + HWIO_IPA_UC_QMB_BUS_ATTRIB_IN) +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_SHARED_BMSK 0x1000 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_SHARED_SHFT 0xc +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_INNERSHARED_BMSK 0x100 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_INNERSHARED_SHFT 0x8 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_NOALLOCATE_BMSK 0x10 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_NOALLOCATE_SHFT 0x4 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_BMSK 0x7 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_SHFT 0x0 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_STRONGLY_ORDERED_FVAL 0x0 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_DEVICE_FVAL 0x1 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_NON_CACHEABLE_FVAL 0x2 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_COPYBACK_WRITEALLOCATE_FVAL 0x3 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_WRITETHROUGH_NOALLOCATE_FVAL \ + 0x6 +#define HWIO_IPA_UC_QMB_BUS_ATTRIB_MEMTYPE_COPYBACK_NOALLOCATE_FVAL 0x7 +#define HWIO_IPA_UC_MBOX_INT_STTS_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000200 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_STTS_n_PHYS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000200 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_STTS_n_OFFS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000200 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_EN_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000204 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_EN_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS \ + + 0x00000204 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_EN_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS \ + + 0x00000204 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_CLR_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000208 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_CLR_n_PHYS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000208 + 0x10 * (n)) +#define HWIO_IPA_UC_MBOX_INT_CLR_n_OFFS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000208 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_STTS_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000300 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_STTS_n_PHYS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000300 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_STTS_n_OFFS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000300 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_EN_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000304 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_EN_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS \ + + 0x00000304 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_EN_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS \ + + 0x00000304 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_CLR_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000308 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_CLR_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS \ + + 0x00000308 + 0x10 * (n)) +#define HWIO_IPA_UC_IPA_INT_CLR_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS \ + + 0x00000308 + 0x10 * (n)) +#define HWIO_IPA_UC_HWEV_INT_STTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000400) +#define HWIO_IPA_UC_HWEV_INT_STTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000400) +#define HWIO_IPA_UC_HWEV_INT_STTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000400) +#define HWIO_IPA_UC_HWEV_INT_EN_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000404) +#define HWIO_IPA_UC_HWEV_INT_EN_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000404) +#define HWIO_IPA_UC_HWEV_INT_EN_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000404) +#define HWIO_IPA_UC_HWEV_INT_CLR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000408) +#define HWIO_IPA_UC_HWEV_INT_CLR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000408) +#define HWIO_IPA_UC_HWEV_INT_CLR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000408) +#define HWIO_IPA_UC_SWEV_INT_STTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000410) +#define HWIO_IPA_UC_SWEV_INT_STTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000410) +#define HWIO_IPA_UC_SWEV_INT_STTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000410) +#define HWIO_IPA_UC_SWEV_INT_EN_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000414) +#define HWIO_IPA_UC_SWEV_INT_EN_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000414) +#define HWIO_IPA_UC_SWEV_INT_EN_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000414) +#define HWIO_IPA_UC_SWEV_INT_CLR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000418) +#define HWIO_IPA_UC_SWEV_INT_CLR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000418) +#define HWIO_IPA_UC_SWEV_INT_CLR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000418) +#define HWIO_IPA_UC_VUIC_INT_STTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x0000041c) +#define HWIO_IPA_UC_VUIC_INT_STTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x0000041c) +#define HWIO_IPA_UC_VUIC_INT_STTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x0000041c) +#define HWIO_IPA_UC_VUIC_INT_CLR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000420) +#define HWIO_IPA_UC_VUIC_INT_CLR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000420) +#define HWIO_IPA_UC_VUIC_INT_CLR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000420) +#define HWIO_IPA_UC_TIMER_CTRL_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000500 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_CTRL_n_PHYS(n) (IPA_UC_IPA_UC_PER_REG_BASE_PHYS \ + + 0x00000500 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_CTRL_n_OFFS(n) (IPA_UC_IPA_UC_PER_REG_BASE_OFFS \ + + 0x00000500 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_CTRL_R_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000504 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_CTRL_R_n_PHYS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000504 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_CTRL_R_n_OFFS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000504 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_STATUS_n_ADDR(n) (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000508 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_STATUS_n_PHYS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000508 + 0x10 * (n)) +#define HWIO_IPA_UC_TIMER_STATUS_n_OFFS(n) ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000508 + 0x10 * (n)) +#define HWIO_IPA_UC_EVENTS_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00000600) +#define HWIO_IPA_UC_EVENTS_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000600) +#define HWIO_IPA_UC_EVENTS_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000600) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_ADDR ( \ + IPA_UC_IPA_UC_PER_REG_BASE + 0x00000710) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_PHYS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_PHYS + 0x00000710) +#define HWIO_IPA_UC_VUIC_BUS_ADDR_TRANSLATE_EN_OFFS ( \ + IPA_UC_IPA_UC_PER_REG_BASE_OFFS + 0x00000710) +#define HWIO_IPA_UC_SYS_ADDR_MSB_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000714) +#define HWIO_IPA_UC_SYS_ADDR_MSB_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000714) +#define HWIO_IPA_UC_SYS_ADDR_MSB_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000714) +#define HWIO_IPA_UC_PC_RESTORE_WR_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x00000718) +#define HWIO_IPA_UC_PC_RESTORE_WR_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00000718) +#define HWIO_IPA_UC_PC_RESTORE_WR_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00000718) +#define HWIO_IPA_UC_PC_RESTORE_RD_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + \ + 0x0000071c) +#define HWIO_IPA_UC_PC_RESTORE_RD_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x0000071c) +#define HWIO_IPA_UC_PC_RESTORE_RD_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x0000071c) +#define HWIO_IPA_UC_SPARE_ADDR (IPA_UC_IPA_UC_PER_REG_BASE + 0x00001ffc) +#define HWIO_IPA_UC_SPARE_PHYS (IPA_UC_IPA_UC_PER_REG_BASE_PHYS + \ + 0x00001ffc) +#define HWIO_IPA_UC_SPARE_OFFS (IPA_UC_IPA_UC_PER_REG_BASE_OFFS + \ + 0x00001ffc) +#endif diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_hwio_def.h b/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_hwio_def.h new file mode 100644 index 000000000000..6c1937728e62 --- /dev/null +++ b/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_hwio_def.h @@ -0,0 +1,2775 @@ +/* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#if !defined(_IPA_HWIO_DEF_H_) +#define _IPA_HWIO_DEF_H_ + +/* ***************************************************************************** + * + * HWIO register definitions + * + * ***************************************************************************** + */ + +struct ipa_hwio_def_ipa_gsi_top_gsi_cfg_s { + u32 gsi_enable : 1; + u32 mcs_enable : 1; + u32 double_mcs_clk_freq : 1; + u32 uc_is_mcs : 1; + u32 gsi_pwr_clps : 1; + u32 bp_mtrix_disable : 1; + u32 reserved0 : 26; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_cfg_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_ree_cfg_s { + u32 move_to_esc_clr_mode_trsh : 1; + u32 reserved0 : 7; + u32 max_burst_size : 8; + u32 reserved1 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_ree_cfg_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_ree_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_manager_ee_qos_n_s { + u32 ee_prio : 2; + u32 reserved0 : 6; + u32 max_ch_alloc : 5; + u32 reserved1 : 3; + u32 max_ev_alloc : 5; + u32 reserved2 : 11; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_manager_ee_qos_n_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_manager_ee_qos_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr_s { + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ch_cntxt_base_addr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr_s { + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ev_cntxt_base_addr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr_s { + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr_u { + struct + ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_storage_base_addr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr_s { + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr_u { + struct + ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_re_esc_buf_base_addr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr_s { + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr_u { + struct + ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_ee_scrach_base_addr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr_s { + u32 shram_ptr : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr_u { + struct + ipa_hwio_def_ipa_gsi_top_gsi_shram_ptr_func_stack_base_addr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_cmd_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_cmd_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ee_generic_cmd_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_db_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_db_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_db_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ev_db_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ev_db_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ev_db_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_new_re_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_new_re_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_new_re_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_dis_comp_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_dis_comp_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_dis_comp_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_empty_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_empty_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_ch_empty_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_event_gen_comp_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_event_gen_comp_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_event_gen_comp_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_timer_expired_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_timer_expired_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_timer_expired_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_write_eng_comp_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_write_eng_comp_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_write_eng_comp_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_read_eng_comp_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_read_eng_comp_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_read_eng_comp_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_uc_gp_int_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_uc_gp_int_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_uc_gp_int_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_int_mod_stopped_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_int_mod_stopped_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_iram_ptr_int_mod_stopped_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_inst_ram_n_s { + u32 inst_byte_0 : 8; + u32 inst_byte_1 : 8; + u32 inst_byte_2 : 8; + u32 inst_byte_3 : 8; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_inst_ram_n_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_inst_ram_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_shram_n_s { + u32 shram : 32; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_shram_n_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_shram_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_test_bus_sel_s { + u32 gsi_testbus_sel : 8; + u32 reserved0 : 8; + u32 gsi_hw_events_sel : 4; + u32 reserved1 : 12; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_test_bus_sel_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_test_bus_sel_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_test_bus_reg_s { + u32 gsi_testbus_reg : 32; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_test_bus_reg_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_test_bus_reg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_busy_reg_s { + u32 csr_busy : 1; + u32 ree_busy : 1; + u32 mcs_busy : 1; + u32 timer_busy : 1; + u32 rd_wr_busy : 1; + u32 ev_eng_busy : 1; + u32 int_eng_busy : 1; + u32 ree_pwr_clps_busy : 1; + u32 db_eng_busy : 1; + u32 dbg_cnt_busy : 1; + u32 uc_busy : 1; + u32 ic_busy : 1; + u32 sdma_busy : 1; + u32 reserved0 : 19; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_busy_reg_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_busy_reg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_event_pending_s { + u32 chid_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_event_pending_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_event_pending_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_timer_pending_s { + u32 chid_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_timer_pending_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_timer_pending_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_rd_wr_pending_s { + u32 chid_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_rd_wr_pending_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_rd_wr_pending_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_countern_s { + u32 counter_value : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_countern_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_countern_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_from_sw_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_from_sw_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_from_sw_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_stall_s { + u32 mcs_stall : 1; + u32 reserved0 : 31; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_stall_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_stall_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_for_debug_s { + u32 iram_ptr : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_for_debug_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_pc_for_debug_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_err_trns_id_s { + u32 err_write : 1; + u32 reserved0 : 7; + u32 err_tid : 8; + u32 err_mid : 8; + u32 err_saved : 1; + u32 reserved1 : 7; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_err_trns_id_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_err_trns_id_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_last_misc_idn_s { + u32 addr_20_0 : 21; + u32 write : 1; + u32 tid : 5; + u32 mid : 5; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_last_misc_idn_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_qsb_log_last_misc_idn_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_rf_n_read_s { + u32 rf_reg : 32; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_rf_n_read_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_sw_rf_n_read_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_ee_n_ch_k_vp_table_s { + u32 phy_ch : 5; + u32 valid : 1; + u32 reserved0 : 26; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_ee_n_ch_k_vp_table_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_ee_n_ch_k_vp_table_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_gsi_debug_ee_n_ev_k_vp_table_s { + u32 phy_ev_ch : 5; + u32 valid : 1; + u32 reserved0 : 26; +}; +union ipa_hwio_def_ipa_gsi_top_gsi_debug_ee_n_ev_k_vp_table_u { + struct ipa_hwio_def_ipa_gsi_top_gsi_debug_ee_n_ev_k_vp_table_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_0_s { + u32 chtype_protocol : 3; + u32 chtype_dir : 1; + u32 ee : 4; + u32 chid : 5; + u32 reserved0 : 1; + u32 erindex : 5; + u32 reserved1 : 1; + u32 chstate : 4; + u32 element_size : 8; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_0_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_1_s { + u32 r_length : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_1_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_2_s { + u32 r_base_addr_lsbs : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_2_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_3_s { + u32 r_base_addr_msbs : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_3_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_3_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_4_s { + u32 read_ptr_lsb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_4_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_4_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_5_s { + u32 read_ptr_msb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_5_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_5_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_6_s { + u32 write_ptr_lsb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_6_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_6_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_7_s { + u32 write_ptr_msb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_7_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_cntxt_7_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_read_ptr_s { + u32 read_ptr : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_read_ptr_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_read_ptr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_write_ptr_s { + u32 re_intr_db : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_write_ptr_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_re_fetch_write_ptr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_qos_s { + u32 wrr_weight : 4; + u32 reserved0 : 4; + u32 max_prefetch : 1; + u32 use_db_eng : 1; + u32 use_escape_buf_only : 1; + u32 reserved1 : 21; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_qos_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_qos_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_0_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_0_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_0_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_1_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_1_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_1_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_2_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_2_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_2_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_3_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_3_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_ch_k_scratch_3_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_0_s { + u32 chtype : 4; + u32 ee : 4; + u32 evchid : 8; + u32 intype : 1; + u32 reserved0 : 3; + u32 chstate : 4; + u32 element_size : 8; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_0_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_1_s { + u32 r_length : 16; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_1_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_2_s { + u32 r_base_addr_lsbs : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_2_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_3_s { + u32 r_base_addr_msbs : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_3_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_3_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_4_s { + u32 read_ptr_lsb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_4_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_4_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_5_s { + u32 read_ptr_msb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_5_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_5_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_6_s { + u32 write_ptr_lsb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_6_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_6_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_7_s { + u32 write_ptr_msb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_7_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_7_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_8_s { + u32 int_modt : 16; + u32 int_modc : 8; + u32 int_mod_cnt : 8; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_8_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_8_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_9_s { + u32 intvec : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_9_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_9_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_10_s { + u32 msi_addr_lsb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_10_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_10_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_11_s { + u32 msi_addr_msb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_11_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_11_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_12_s { + u32 rp_update_addr_lsb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_12_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_12_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_13_s { + u32 rp_update_addr_msb : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_13_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_cntxt_13_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_0_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_0_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_0_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_1_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_1_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_ev_ch_k_scratch_1_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_status_s { + u32 enabled : 1; + u32 reserved0 : 31; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_gsi_status_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_gsi_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_s { + u32 ch_ctrl : 1; + u32 ev_ctrl : 1; + u32 glob_ee : 1; + u32 ieob : 1; + u32 inter_ee_ch_ctrl : 1; + u32 inter_ee_ev_ctrl : 1; + u32 general : 1; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_msk_s { + u32 ch_ctrl : 1; + u32 ev_ctrl : 1; + u32 glob_ee : 1; + u32 ieob : 1; + u32 inter_ee_ch_ctrl : 1; + u32 inter_ee_ev_ctrl : 1; + u32 general : 1; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_msk_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_type_irq_msk_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_s { + u32 gsi_ch_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_s { + u32 ev_ch_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_msk_s { + u32 gsi_ch_bit_map_msk : 17; + u32 reserved0 : 15; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_msk_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_msk_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_msk_s { + u32 ev_ch_bit_map_msk : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_msk_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_msk_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_clr_s { + u32 gsi_ch_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_clr_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_gsi_ch_irq_clr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_clr_s { + u32 ev_ch_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_clr_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ev_ch_irq_clr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_s { + u32 ev_ch_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_msk_s { + u32 ev_ch_bit_map_msk : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_msk_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_msk_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_clr_s { + u32 ev_ch_bit_map : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_clr_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_src_ieob_irq_clr_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_glob_irq_stts_s { + u32 error_int : 1; + u32 gp_int1 : 1; + u32 gp_int2 : 1; + u32 gp_int3 : 1; + u32 reserved0 : 28; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_glob_irq_stts_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_glob_irq_stts_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_gsi_irq_stts_s { + u32 gsi_break_point : 1; + u32 gsi_bus_error : 1; + u32 gsi_cmd_fifo_ovrflow : 1; + u32 gsi_mcs_stack_ovrflow : 1; + u32 reserved0 : 28; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_gsi_irq_stts_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_gsi_irq_stts_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_error_log_s { + u32 error_log : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_error_log_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_error_log_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_error_log_clr_s { + u32 error_log_clr : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_error_log_clr_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_error_log_clr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_0_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_0_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_1_s { + u32 scratch : 32; +}; +union ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_1_u { + struct ipa_hwio_def_ipa_gsi_top_ee_n_cntxt_scratch_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_comp_hw_version_s { + u32 step : 16; + u32 minor : 12; + u32 major : 4; +}; +union ipa_hwio_def_ipa_comp_hw_version_u { + struct ipa_hwio_def_ipa_comp_hw_version_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_comp_cfg_s { + u32 enable : 1; + u32 gsi_snoc_bypass_dis : 1; + u32 gen_qmb_0_snoc_bypass_dis : 1; + u32 gen_qmb_1_snoc_bypass_dis : 1; + u32 ipa_dcmp_fast_clk_en : 1; + u32 ipa_qmb_select_by_address_cons_en : 1; + u32 ipa_qmb_select_by_address_prod_en : 1; + u32 gsi_multi_inorder_rd_dis : 1; + u32 gsi_multi_inorder_wr_dis : 1; + u32 gen_qmb_0_multi_inorder_rd_dis : 1; + u32 gen_qmb_1_multi_inorder_rd_dis : 1; + u32 gen_qmb_0_multi_inorder_wr_dis : 1; + u32 gen_qmb_1_multi_inorder_wr_dis : 1; + u32 gen_qmb_0_snoc_cnoc_loop_protection_disable : 1; + u32 gsi_snoc_cnoc_loop_protection_disable : 1; + u32 gsi_multi_axi_masters_dis : 1; + u32 ipa_qmb_select_by_address_global_en : 1; + u32 ipa_atomic_fetcher_arb_lock_dis : 4; + u32 reserved0 : 11; +}; +union ipa_hwio_def_ipa_comp_cfg_u { + struct ipa_hwio_def_ipa_comp_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_route_s { + u32 route_dis : 1; + u32 route_def_pipe : 5; + u32 route_def_hdr_table : 1; + u32 route_def_hdr_ofst : 10; + u32 route_frag_def_pipe : 5; + u32 reserved0 : 2; + u32 route_def_retain_hdr : 1; + u32 reserved1 : 7; +}; +union ipa_hwio_def_ipa_route_u { + struct ipa_hwio_def_ipa_route_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_tag_timer_s { + u32 tag_timer : 24; + u32 reserved0 : 8; +}; +union ipa_hwio_def_ipa_tag_timer_u { + struct ipa_hwio_def_ipa_tag_timer_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_proc_iph_cfg_s { + u32 iph_threshold : 2; + u32 iph_pipelining_disable : 1; + u32 iph_time_cnt_clk_src : 1; + u32 status_from_iph_frst_always : 1; + u32 iph_nat_blind_invalidate_tport_offset_disable : 1; + u32 pipestage_overlap_disable : 1; + u32 ftch_dcph_overlap_enable : 1; + u32 iph_pkt_parser_protocol_stop_enable : 1; + u32 iph_pkt_parser_protocol_stop_hop : 1; + u32 iph_pkt_parser_protocol_stop_dest : 1; + u32 iph_pkt_parser_ihl_to_2nd_frag_en : 1; + u32 reserved0 : 4; + u32 iph_pkt_parser_protocol_stop_value : 8; + u32 reserved1 : 8; +}; +union ipa_hwio_def_ipa_proc_iph_cfg_u { + struct ipa_hwio_def_ipa_proc_iph_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dpl_timer_lsb_s { + u32 tod_lsb : 32; +}; +union ipa_hwio_def_ipa_dpl_timer_lsb_u { + struct ipa_hwio_def_ipa_dpl_timer_lsb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dpl_timer_msb_s { + u32 tod_msb : 16; + u32 reserved0 : 15; + u32 timer_en : 1; +}; +union ipa_hwio_def_ipa_dpl_timer_msb_u { + struct ipa_hwio_def_ipa_dpl_timer_msb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_tx_wrapper_s { + u32 tx0_idle : 1; + u32 tx1_idle : 1; + u32 ipa_prod_ackmngr_db_empty : 1; + u32 ipa_prod_ackmngr_state_idle : 1; + u32 ipa_prod_bresp_empty : 1; + u32 ipa_prod_bresp_toggle_idle : 1; + u32 ipa_mbim_pkt_fms_idle : 1; + u32 mbim_expiry : 1; + u32 trnseq_force_valid : 1; + u32 pkt_drop_cnt_idle : 1; + u32 reserved0 : 22; +}; +union ipa_hwio_def_ipa_state_tx_wrapper_u { + struct ipa_hwio_def_ipa_state_tx_wrapper_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_tx1_s { + u32 last_arbit_type : 2; + u32 next_arbit_type : 2; + u32 pa_idle : 1; + u32 pa_ctx_idle : 1; + u32 pa_pub_cnt_empty : 1; + u32 tx_cmd_main_idle : 1; + u32 tx_cmd_trnseq_idle : 1; + u32 tx_cmd_snif_idle : 1; + u32 tx_cmd_bresp_aloc_idle : 1; + u32 tx_cmd_bresp_inj_idle : 1; + u32 ar_idle : 1; + u32 dmaw_idle : 1; + u32 dmaw_last_outsd_idle : 1; + u32 pf_idle : 1; + u32 pf_empty : 1; + u32 aligner_empty : 1; + u32 holb_idle : 1; + u32 holb_mask_idle : 1; + u32 rsrcrel_idle : 1; + u32 suspend_empty : 1; + u32 cs_snif_idle : 1; + u32 last_cmd_pipe : 5; + u32 reserved0 : 4; +}; +union ipa_hwio_def_ipa_state_tx1_u { + struct ipa_hwio_def_ipa_state_tx1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_fetcher_s { + u32 ipa_hps_ftch_state_idle : 1; + u32 ipa_hps_ftch_alloc_state_idle : 1; + u32 ipa_hps_ftch_pkt_state_idle : 1; + u32 ipa_hps_ftch_imm_state_idle : 1; + u32 ipa_hps_ftch_cmplt_state_idle : 1; + u32 ipa_hps_dmar_state_idle : 7; + u32 ipa_hps_dmar_rep_state_idle : 7; + u32 ipa_hps_dmar_slot_state_idle : 7; + u32 ipa_hps_imm_cmd_exec_state_idle : 1; + u32 reserved0 : 5; +}; +union ipa_hwio_def_ipa_state_fetcher_u { + struct ipa_hwio_def_ipa_state_fetcher_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_fetcher_mask_s { + u32 mask_queue_dmar_uses_queue : 4; + u32 mask_queue_imm_exec : 4; + u32 mask_queue_no_resources_context : 4; + u32 mask_queue_no_resources_hps_dmar : 4; + u32 mask_queue_no_resources_ack_entry : 4; + u32 mask_queue_arb_lock : 4; + u32 mask_queue_step_mode : 4; + u32 reserved0 : 4; +}; +union ipa_hwio_def_ipa_state_fetcher_mask_u { + struct ipa_hwio_def_ipa_state_fetcher_mask_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_dfetcher_s { + u32 ipa_dps_ftch_pkt_state_idle : 1; + u32 ipa_dps_ftch_cmplt_state_idle : 1; + u32 reserved0 : 2; + u32 ipa_dps_dmar_state_idle : 6; + u32 reserved1 : 2; + u32 ipa_dps_dmar_slot_state_idle : 6; + u32 reserved2 : 14; +}; +union ipa_hwio_def_ipa_state_dfetcher_u { + struct ipa_hwio_def_ipa_state_dfetcher_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_acl_s { + u32 ipa_hps_h_dcph_empty : 1; + u32 ipa_hps_h_dcph_active : 1; + u32 ipa_hps_pkt_parser_empty : 1; + u32 ipa_hps_pkt_parser_active : 1; + u32 ipa_hps_filter_nat_empty : 1; + u32 ipa_hps_filter_nat_active : 1; + u32 ipa_hps_router_empty : 1; + u32 ipa_hps_router_active : 1; + u32 ipa_hps_hdri_empty : 1; + u32 ipa_hps_hdri_active : 1; + u32 ipa_hps_ucp_empty : 1; + u32 ipa_hps_ucp_active : 1; + u32 ipa_hps_enqueuer_empty : 1; + u32 ipa_hps_enqueuer_active : 1; + u32 ipa_dps_d_dcph_empty : 1; + u32 ipa_dps_d_dcph_active : 1; + u32 ipa_dps_dcmp_empty : 1; + u32 ipa_dps_dcmp_active : 1; + u32 ipa_dps_dispatcher_empty : 1; + u32 ipa_dps_dispatcher_active : 1; + u32 ipa_dps_d_dcph_2_empty : 1; + u32 ipa_dps_d_dcph_2_active : 1; + u32 ipa_hps_sequencer_idle : 1; + u32 ipa_dps_sequencer_idle : 1; + u32 reserved0 : 8; +}; +union ipa_hwio_def_ipa_state_acl_u { + struct ipa_hwio_def_ipa_state_acl_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_gsi_tlv_s { + u32 ipa_gsi_toggle_fsm_idle : 10; + u32 reserved0 : 22; +}; +union ipa_hwio_def_ipa_state_gsi_tlv_u { + struct ipa_hwio_def_ipa_state_gsi_tlv_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_gsi_aos_s { + u32 ipa_gsi_aos_fsm_idle : 23; + u32 reserved0 : 9; +}; +union ipa_hwio_def_ipa_state_gsi_aos_u { + struct ipa_hwio_def_ipa_state_gsi_aos_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_gsi_if_s { + u32 ipa_gsi_prod_fsm_tx_0 : 2; + u32 ipa_gsi_prod_fsm_tx_1 : 2; + u32 reserved0 : 28; +}; +union ipa_hwio_def_ipa_state_gsi_if_u { + struct ipa_hwio_def_ipa_state_gsi_if_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_gsi_skip_s { + u32 ipa_gsi_skip_fsm : 26; + u32 reserved0 : 6; +}; +union ipa_hwio_def_ipa_state_gsi_skip_u { + struct ipa_hwio_def_ipa_state_gsi_skip_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_s { + u32 rx_wait : 1; + u32 rx_idle : 1; + u32 tx_idle : 1; + u32 reserved0 : 1; + u32 bam_gsi_idle : 1; + u32 ipa_status_sniffer_idle : 1; + u32 ipa_noc_idle : 1; + u32 aggr_idle : 1; + u32 mbim_aggr_idle : 1; + u32 ipa_rsrc_mngr_db_empty : 1; + u32 ipa_rsrc_state_idle : 1; + u32 ipa_ackmngr_db_empty : 1; + u32 ipa_ackmngr_state_idle : 1; + u32 ipa_tx_ackq_full : 1; + u32 ipa_prod_ackmngr_db_empty : 1; + u32 ipa_prod_ackmngr_state_idle : 1; + u32 ipa_prod_bresp_idle : 1; + u32 reserved1 : 1; + u32 ipa_ntf_tx_empty : 1; + u32 ipa_tx_ackq_empty : 1; + u32 ipa_uc_ackq_empty : 1; + u32 ipa_rx_ackq_empty : 1; + u32 ipa_tx_commander_cmdq_empty : 1; + u32 ipa_rx_splt_cmdq_0_empty : 1; + u32 ipa_rx_splt_cmdq_1_empty : 1; + u32 ipa_rx_splt_cmdq_2_empty : 1; + u32 reserved2 : 2; + u32 ipa_rx_hps_empty : 1; + u32 ipa_hps_dps_empty : 1; + u32 ipa_dps_tx_empty : 1; + u32 ipa_uc_rx_hnd_cmdq_empty : 1; +}; +union ipa_hwio_def_ipa_state_u { + struct ipa_hwio_def_ipa_state_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_rx_active_s { + u32 endpoints : 10; + u32 reserved0 : 22; +}; +union ipa_hwio_def_ipa_state_rx_active_u { + struct ipa_hwio_def_ipa_state_rx_active_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_tx0_s { + u32 last_arbit_type : 2; + u32 next_arbit_type : 2; + u32 pa_idle : 1; + u32 pa_ctx_idle : 1; + u32 pa_pub_cnt_empty : 1; + u32 tx_cmd_main_idle : 1; + u32 tx_cmd_trnseq_idle : 1; + u32 tx_cmd_snif_idle : 1; + u32 tx_cmd_bresp_aloc_idle : 1; + u32 tx_cmd_bresp_inj_idle : 1; + u32 ar_idle : 1; + u32 dmaw_idle : 1; + u32 dmaw_last_outsd_idle : 1; + u32 pf_idle : 1; + u32 pf_empty : 1; + u32 aligner_empty : 1; + u32 holb_idle : 1; + u32 holb_mask_idle : 1; + u32 rsrcrel_idle : 1; + u32 suspend_empty : 1; + u32 cs_snif_idle : 1; + u32 last_cmd_pipe : 5; + u32 reserved0 : 4; +}; +union ipa_hwio_def_ipa_state_tx0_u { + struct ipa_hwio_def_ipa_state_tx0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_state_aggr_active_s { + u32 endpoints : 23; + u32 reserved0 : 9; +}; +union ipa_hwio_def_ipa_state_aggr_active_u { + struct ipa_hwio_def_ipa_state_aggr_active_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_filt_rout_hash_en_s { + u32 ipv6_router_hash_en : 1; + u32 reserved0 : 3; + u32 ipv6_filter_hash_en : 1; + u32 reserved1 : 3; + u32 ipv4_router_hash_en : 1; + u32 reserved2 : 3; + u32 ipv4_filter_hash_en : 1; + u32 reserved3 : 19; +}; +union ipa_hwio_def_ipa_filt_rout_hash_en_u { + struct ipa_hwio_def_ipa_filt_rout_hash_en_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_filt_rout_hash_flush_s { + u32 ipv6_router_hash_flush : 1; + u32 reserved0 : 3; + u32 ipv6_filter_hash_flush : 1; + u32 reserved1 : 3; + u32 ipv4_router_hash_flush : 1; + u32 reserved2 : 3; + u32 ipv4_filter_hash_flush : 1; + u32 reserved3 : 19; +}; +union ipa_hwio_def_ipa_filt_rout_hash_flush_u { + struct ipa_hwio_def_ipa_filt_rout_hash_flush_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ipv4_filter_init_values_s { + u32 ip_v4_filter_init_hashed_addr : 16; + u32 ip_v4_filter_init_non_hashed_addr : 16; +}; +union ipa_hwio_def_ipa_ipv4_filter_init_values_u { + struct ipa_hwio_def_ipa_ipv4_filter_init_values_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ipv6_filter_init_values_s { + u32 ip_v6_filter_init_hashed_addr : 16; + u32 ip_v6_filter_init_non_hashed_addr : 16; +}; +union ipa_hwio_def_ipa_ipv6_filter_init_values_u { + struct ipa_hwio_def_ipa_ipv6_filter_init_values_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ipv4_route_init_values_s { + u32 ip_v4_route_init_hashed_addr : 16; + u32 ip_v4_route_init_non_hashed_addr : 16; +}; +union ipa_hwio_def_ipa_ipv4_route_init_values_u { + struct ipa_hwio_def_ipa_ipv4_route_init_values_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ipv6_route_init_values_s { + u32 ip_v6_route_init_hashed_addr : 16; + u32 ip_v6_route_init_non_hashed_addr : 16; +}; +union ipa_hwio_def_ipa_ipv6_route_init_values_u { + struct ipa_hwio_def_ipa_ipv6_route_init_values_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_bcr_s { + u32 bcr_cmdq_l_lack_one_entry : 1; + u32 bcr_tx_not_using_bresp : 1; + u32 bcr_tx_suspend_irq_only_assert_once_per_pkt : 1; + u32 bcr_suspend_l2_irq : 1; + u32 bcr_holb_drop_l2_irq : 1; + u32 bcr_dual_tx : 1; + u32 bcr_enable_filter_data_cache : 1; + u32 bcr_notif_priority_over_zlt : 1; + u32 bcr_filter_prefetch_en : 1; + u32 bcr_router_prefetch_en : 1; + u32 reserved0 : 22; +}; +union ipa_hwio_def_ipa_bcr_u { + struct ipa_hwio_def_ipa_bcr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_bam_activated_ports_s { + u32 endpoints : 23; + u32 reserved0 : 9; +}; +union ipa_hwio_def_ipa_bam_activated_ports_u { + struct ipa_hwio_def_ipa_bam_activated_ports_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_s { + u32 zero : 3; + u32 addr : 29; +}; +union ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_u { + struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_msb_s { + u32 addr : 32; +}; +union ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_msb_u { + struct ipa_hwio_def_ipa_sys_pkt_proc_cntxt_base_msb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_local_pkt_proc_cntxt_base_s { + u32 zero : 3; + u32 addr : 14; + u32 reserved0 : 15; +}; +union ipa_hwio_def_ipa_local_pkt_proc_cntxt_base_u { + struct ipa_hwio_def_ipa_local_pkt_proc_cntxt_base_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_src_rsrc_grp_01_rsrc_type_n_s { + u32 src_rsrc_grp_0_min_limit : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_0_max_limit : 6; + u32 reserved1 : 2; + u32 src_rsrc_grp_1_min_limit : 6; + u32 reserved2 : 2; + u32 src_rsrc_grp_1_max_limit : 6; + u32 reserved3 : 2; +}; +union ipa_hwio_def_ipa_src_rsrc_grp_01_rsrc_type_n_u { + struct ipa_hwio_def_ipa_src_rsrc_grp_01_rsrc_type_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_s { + u32 src_rsrc_grp_2_min_limit : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_2_max_limit : 6; + u32 reserved1 : 2; + u32 src_rsrc_grp_3_min_limit : 6; + u32 reserved2 : 2; + u32 src_rsrc_grp_3_max_limit : 6; + u32 reserved3 : 2; +}; +union ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_u { + struct ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_s { + u32 src_rsrc_grp_0_cnt : 6; + u32 reserved0 : 2; + u32 src_rsrc_grp_1_cnt : 6; + u32 reserved1 : 2; + u32 src_rsrc_grp_2_cnt : 6; + u32 reserved2 : 2; + u32 src_rsrc_grp_3_cnt : 6; + u32 reserved3 : 2; +}; +union ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_u { + struct ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_dst_rsrc_grp_01_rsrc_type_n_s { + u32 dst_rsrc_grp_0_min_limit : 6; + u32 reserved0 : 2; + u32 dst_rsrc_grp_0_max_limit : 6; + u32 reserved1 : 2; + u32 dst_rsrc_grp_1_min_limit : 6; + u32 reserved2 : 2; + u32 dst_rsrc_grp_1_max_limit : 6; + u32 reserved3 : 2; +}; +union ipa_hwio_def_ipa_dst_rsrc_grp_01_rsrc_type_n_u { + struct ipa_hwio_def_ipa_dst_rsrc_grp_01_rsrc_type_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_s { + u32 dst_rsrc_grp_2_min_limit : 6; + u32 reserved0 : 2; + u32 dst_rsrc_grp_2_max_limit : 6; + u32 reserved1 : 2; + u32 dst_rsrc_grp_3_min_limit : 6; + u32 reserved2 : 2; + u32 dst_rsrc_grp_3_max_limit : 6; + u32 reserved3 : 2; +}; +union ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_u { + struct ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_s { + u32 dst_rsrc_grp_0_cnt : 6; + u32 reserved0 : 2; + u32 dst_rsrc_grp_1_cnt : 6; + u32 reserved1 : 2; + u32 dst_rsrc_grp_2_cnt : 6; + u32 reserved2 : 2; + u32 dst_rsrc_grp_3_cnt : 6; + u32 reserved3 : 2; +}; +union ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_u { + struct ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_rsrc_grp_cfg_s { + u32 src_grp_special_valid : 1; + u32 reserved0 : 3; + u32 src_grp_special_index : 2; + u32 reserved1 : 2; + u32 dst_pipe_special_valid : 1; + u32 reserved2 : 3; + u32 dst_pipe_special_index : 5; + u32 reserved3 : 3; + u32 dst_grp_special_valid : 1; + u32 reserved4 : 3; + u32 dst_grp_special_index : 2; + u32 reserved5 : 6; +}; +union ipa_hwio_def_ipa_rsrc_grp_cfg_u { + struct ipa_hwio_def_ipa_rsrc_grp_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_ctrl_n_s { + u32 endp_suspend : 1; + u32 endp_delay : 1; + u32 reserved0 : 30; +}; +union ipa_hwio_def_ipa_endp_init_ctrl_n_u { + struct ipa_hwio_def_ipa_endp_init_ctrl_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_ctrl_scnd_n_s { + u32 reserved0 : 1; + u32 endp_delay : 1; + u32 reserved1 : 30; +}; +union ipa_hwio_def_ipa_endp_init_ctrl_scnd_n_u { + struct ipa_hwio_def_ipa_endp_init_ctrl_scnd_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_cfg_n_s { + u32 frag_offload_en : 1; + u32 cs_offload_en : 2; + u32 cs_metadata_hdr_offset : 4; + u32 reserved0 : 1; + u32 gen_qmb_master_sel : 1; + u32 reserved1 : 23; +}; +union ipa_hwio_def_ipa_endp_init_cfg_n_u { + struct ipa_hwio_def_ipa_endp_init_cfg_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_nat_n_s { + u32 nat_en : 2; + u32 reserved0 : 30; +}; +union ipa_hwio_def_ipa_endp_init_nat_n_u { + struct ipa_hwio_def_ipa_endp_init_nat_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_hdr_n_s { + u32 hdr_len : 6; + u32 hdr_ofst_metadata_valid : 1; + u32 hdr_ofst_metadata : 6; + u32 hdr_additional_const_len : 6; + u32 hdr_ofst_pkt_size_valid : 1; + u32 hdr_ofst_pkt_size : 6; + u32 hdr_a5_mux : 1; + u32 hdr_len_inc_deagg_hdr : 1; + u32 hdr_metadata_reg_valid : 1; + u32 reserved0 : 3; +}; +union ipa_hwio_def_ipa_endp_init_hdr_n_u { + struct ipa_hwio_def_ipa_endp_init_hdr_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_hdr_ext_n_s { + u32 hdr_endianness : 1; + u32 hdr_total_len_or_pad_valid : 1; + u32 hdr_total_len_or_pad : 1; + u32 hdr_payload_len_inc_padding : 1; + u32 hdr_total_len_or_pad_offset : 6; + u32 hdr_pad_to_alignment : 4; + u32 reserved0 : 18; +}; +union ipa_hwio_def_ipa_endp_init_hdr_ext_n_u { + struct ipa_hwio_def_ipa_endp_init_hdr_ext_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_hdr_metadata_mask_n_s { + u32 metadata_mask : 32; +}; +union ipa_hwio_def_ipa_endp_init_hdr_metadata_mask_n_u { + struct ipa_hwio_def_ipa_endp_init_hdr_metadata_mask_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_hdr_metadata_n_s { + u32 metadata : 32; +}; +union ipa_hwio_def_ipa_endp_init_hdr_metadata_n_u { + struct ipa_hwio_def_ipa_endp_init_hdr_metadata_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_mode_n_s { + u32 mode : 3; + u32 reserved0 : 1; + u32 dest_pipe_index : 5; + u32 reserved1 : 3; + u32 byte_threshold : 16; + u32 pipe_replicate_en : 1; + u32 pad_en : 1; + u32 hdr_ftch_disable : 1; + u32 reserved2 : 1; +}; +union ipa_hwio_def_ipa_endp_init_mode_n_u { + struct ipa_hwio_def_ipa_endp_init_mode_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_aggr_n_s { + u32 aggr_en : 2; + u32 aggr_type : 3; + u32 aggr_byte_limit : 5; + u32 aggr_time_limit : 5; + u32 aggr_pkt_limit : 6; + u32 aggr_sw_eof_active : 1; + u32 aggr_force_close : 1; + u32 reserved0 : 1; + u32 aggr_hard_byte_limit_enable : 1; + u32 reserved1 : 7; +}; +union ipa_hwio_def_ipa_endp_init_aggr_n_u { + struct ipa_hwio_def_ipa_endp_init_aggr_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_hol_block_en_n_s { + u32 en : 1; + u32 reserved0 : 31; +}; +union ipa_hwio_def_ipa_endp_init_hol_block_en_n_u { + struct ipa_hwio_def_ipa_endp_init_hol_block_en_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_hol_block_timer_n_s { + u32 timer : 32; +}; +union ipa_hwio_def_ipa_endp_init_hol_block_timer_n_u { + struct ipa_hwio_def_ipa_endp_init_hol_block_timer_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_deaggr_n_s { + u32 deaggr_hdr_len : 6; + u32 syspipe_err_detection : 1; + u32 packet_offset_valid : 1; + u32 packet_offset_location : 6; + u32 ignore_min_pkt_err : 1; + u32 reserved0 : 1; + u32 max_packet_len : 16; +}; +union ipa_hwio_def_ipa_endp_init_deaggr_n_u { + struct ipa_hwio_def_ipa_endp_init_deaggr_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_rsrc_grp_n_s { + u32 rsrc_grp : 2; + u32 reserved0 : 30; +}; +union ipa_hwio_def_ipa_endp_init_rsrc_grp_n_u { + struct ipa_hwio_def_ipa_endp_init_rsrc_grp_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_init_seq_n_s { + u32 hps_seq_type : 4; + u32 dps_seq_type : 4; + u32 hps_rep_seq_type : 4; + u32 dps_rep_seq_type : 4; + u32 reserved0 : 16; +}; +union ipa_hwio_def_ipa_endp_init_seq_n_u { + struct ipa_hwio_def_ipa_endp_init_seq_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_status_n_s { + u32 status_en : 1; + u32 status_endp : 5; + u32 reserved0 : 2; + u32 status_location : 1; + u32 status_pkt_suppress : 1; + u32 reserved1 : 22; +}; +union ipa_hwio_def_ipa_endp_status_n_u { + struct ipa_hwio_def_ipa_endp_status_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_filter_router_hsh_cfg_n_s { + u32 filter_hash_msk_src_id : 1; + u32 filter_hash_msk_src_ip_add : 1; + u32 filter_hash_msk_dst_ip_add : 1; + u32 filter_hash_msk_src_port : 1; + u32 filter_hash_msk_dst_port : 1; + u32 filter_hash_msk_protocol : 1; + u32 filter_hash_msk_metadata : 1; + u32 reserved0 : 9; + u32 router_hash_msk_src_id : 1; + u32 router_hash_msk_src_ip_add : 1; + u32 router_hash_msk_dst_ip_add : 1; + u32 router_hash_msk_src_port : 1; + u32 router_hash_msk_dst_port : 1; + u32 router_hash_msk_protocol : 1; + u32 router_hash_msk_metadata : 1; + u32 reserved1 : 9; +}; +union ipa_hwio_def_ipa_endp_filter_router_hsh_cfg_n_u { + struct ipa_hwio_def_ipa_endp_filter_router_hsh_cfg_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rsrc_mngr_db_cfg_s { + u32 rsrc_grp_sel : 2; + u32 reserved0 : 2; + u32 rsrc_type_sel : 3; + u32 reserved1 : 1; + u32 rsrc_id_sel : 6; + u32 reserved2 : 18; +}; +union ipa_hwio_def_ipa_rsrc_mngr_db_cfg_u { + struct ipa_hwio_def_ipa_rsrc_mngr_db_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_s { + u32 rsrc_occupied : 1; + u32 rsrc_next_valid : 1; + u32 reserved0 : 2; + u32 rsrc_next_index : 6; + u32 reserved1 : 22; +}; +union ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_u { + struct ipa_hwio_def_ipa_rsrc_mngr_db_rsrc_read_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rsrc_mngr_db_list_read_s { + u32 rsrc_list_valid : 1; + u32 rsrc_list_hold : 1; + u32 reserved0 : 2; + u32 rsrc_list_head_rsrc : 6; + u32 reserved1 : 2; + u32 rsrc_list_head_cnt : 7; + u32 reserved2 : 1; + u32 rsrc_list_entry_cnt : 7; + u32 reserved3 : 5; +}; +union ipa_hwio_def_ipa_rsrc_mngr_db_list_read_u { + struct ipa_hwio_def_ipa_rsrc_mngr_db_list_read_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_debug_data_sel_s { + u32 external_block_select : 8; + u32 internal_block_select : 8; + u32 pipe_select : 5; + u32 reserved0 : 3; + u32 uc_dap_en : 1; + u32 reserved1 : 7; +}; +union ipa_hwio_def_ipa_debug_data_sel_u { + struct ipa_hwio_def_ipa_debug_data_sel_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_debug_data_s { + u32 debug_data : 32; +}; +union ipa_hwio_def_ipa_debug_data_u { + struct ipa_hwio_def_ipa_debug_data_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_testbus_sel_s { + u32 testbus_en : 1; + u32 reserved0 : 3; + u32 external_block_select : 8; + u32 internal_block_select : 8; + u32 pipe_select : 5; + u32 reserved1 : 7; +}; +union ipa_hwio_def_ipa_testbus_sel_u { + struct ipa_hwio_def_ipa_testbus_sel_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_step_mode_status_s { + u32 hw_en : 32; +}; +union ipa_hwio_def_ipa_step_mode_status_u { + struct ipa_hwio_def_ipa_step_mode_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_s { + u32 reserved0 : 1; + u32 log_en : 1; + u32 reserved1 : 2; + u32 log_pipe : 5; + u32 reserved2 : 3; + u32 log_length : 8; + u32 log_reduction_en : 1; + u32 log_dpl_l2_remove_en : 1; + u32 reserved3 : 10; +}; +union ipa_hwio_def_ipa_log_u { + struct ipa_hwio_def_ipa_log_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_s { + u32 start_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_cmd_addr_u { + struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_msb_s { + u32 start_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_cmd_addr_msb_u { + struct ipa_hwio_def_ipa_log_buf_hw_cmd_addr_msb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_s { + u32 writr_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_u { + struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_msb_s { + u32 writr_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_msb_u { + struct ipa_hwio_def_ipa_log_buf_hw_cmd_write_ptr_msb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_cmd_cfg_s { + u32 size : 16; + u32 enable : 1; + u32 skip_ddr_dma : 1; + u32 reserved0 : 14; +}; +union ipa_hwio_def_ipa_log_buf_hw_cmd_cfg_u { + struct ipa_hwio_def_ipa_log_buf_hw_cmd_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_cmd_ram_ptr_s { + u32 read_ptr : 14; + u32 reserved0 : 2; + u32 write_ptr : 14; + u32 reserved1 : 1; + u32 skip_ddr_wrap_happened : 1; +}; +union ipa_hwio_def_ipa_log_buf_hw_cmd_ram_ptr_u { + struct ipa_hwio_def_ipa_log_buf_hw_cmd_ram_ptr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_cmd_n_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 release_rd_cmd : 1; + u32 release_wr_cmd : 1; + u32 release_rd_pkt : 1; + u32 release_wr_pkt : 1; + u32 release_rd_pkt_enhanced : 1; + u32 reserved0 : 25; +}; + +union ipa_hwio_def_ipa_rx_splt_cmdq_cmd_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_cmd_n_s def; + u32 value; +}; + +struct ipa_hwio_def_ipa_rx_splt_cmdq_cfg_n_s { + u32 block_rd : 1; + u32 block_wr : 1; + u32 reserved0 : 30; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_cfg_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_cfg_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_0_n_s { + u32 cmdq_packet_len_f : 16; + u32 cmdq_src_len_f : 16; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_0_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_0_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_1_n_s { + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_1_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_1_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_2_n_s { + u32 cmdq_addr_lsb_f : 32; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_2_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_2_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_3_n_s { + u32 cmdq_addr_msb_f : 32; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_3_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_wr_3_n_s def; + u32 value; +}; + +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_0_n_s { + u32 cmdq_packet_len_f : 16; + u32 cmdq_src_len_f : 16; +}; + +union ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_0_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_0_n_s def; + u32 value; +}; + +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_1_n_s { + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; + +union ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_1_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_1_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_2_n_s { + u32 cmdq_addr_lsb_f : 32; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_2_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_2_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_3_n_s { + u32 cmdq_addr_msb_f : 32; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_3_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_data_rd_3_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_splt_cmdq_status_n_s { + u32 status : 1; + u32 cmdq_empty : 1; + u32 cmdq_full : 1; + u32 cmdq_count : 2; + u32 cmdq_depth : 2; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_rx_splt_cmdq_status_n_u { + struct ipa_hwio_def_ipa_rx_splt_cmdq_status_n_s def; + u32 value; +}; + +struct ipa_hwio_def_ipa_tx_commander_cmdq_status_s { + u32 status : 1; + u32 cmdq_empty : 1; + u32 cmdq_full : 1; + u32 reserved0 : 29; +}; +union ipa_hwio_def_ipa_tx_commander_cmdq_status_u { + struct ipa_hwio_def_ipa_tx_commander_cmdq_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_cmd_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 2; + u32 reserved0 : 1; + u32 rd_req : 1; + u32 reserved1 : 26; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_cmd_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_s { + u32 block_wr : 4; + u32 reserved0 : 28; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_wr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_s { + u32 block_rd : 4; + u32 reserved0 : 28; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_cfg_rd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_s { + u32 cmdq_packet_len_f : 16; + u32 cmdq_dest_len_f : 16; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_1_s { + u32 cmdq_src_pipe_f : 8; + u32 cmdq_order_f : 2; + u32 cmdq_flags_f : 6; + u32 cmdq_opcode_f : 8; + u32 cmdq_metadata_f : 8; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_1_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_2_s { + u32 cmdq_addr_lsb_f : 32; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_2_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_3_s { + u32 cmdq_addr_msb_f : 32; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_3_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_data_rd_3_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_status_s { + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_status_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_status_empty_s { + u32 cmdq_empty : 4; + u32 reserved0 : 28; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_status_empty_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_status_empty_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_cmdq_count_s { + u32 fifo_count : 7; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_rx_hps_cmdq_count_u { + struct ipa_hwio_def_ipa_rx_hps_cmdq_count_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_clients_min_depth_0_s { + u32 client_0_min_depth : 4; + u32 reserved0 : 4; + u32 client_1_min_depth : 4; + u32 reserved1 : 4; + u32 client_2_min_depth : 4; + u32 reserved2 : 4; + u32 client_3_min_depth : 4; + u32 reserved3 : 4; +}; +union ipa_hwio_def_ipa_rx_hps_clients_min_depth_0_u { + struct ipa_hwio_def_ipa_rx_hps_clients_min_depth_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_rx_hps_clients_max_depth_0_s { + u32 client_0_max_depth : 4; + u32 reserved0 : 4; + u32 client_1_max_depth : 4; + u32 reserved1 : 4; + u32 client_2_max_depth : 4; + u32 reserved2 : 4; + u32 client_3_max_depth : 4; + u32 reserved3 : 4; +}; +union ipa_hwio_def_ipa_rx_hps_clients_max_depth_0_u { + struct ipa_hwio_def_ipa_rx_hps_clients_max_depth_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_hps_dps_cmdq_cmd_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 5; + u32 rd_req : 1; + u32 reserved0 : 24; +}; +union ipa_hwio_def_ipa_hps_dps_cmdq_cmd_u { + struct ipa_hwio_def_ipa_hps_dps_cmdq_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_hps_dps_cmdq_data_rd_0_s { + u32 cmdq_ctx_id_f : 4; + u32 cmdq_src_id_f : 8; + u32 cmdq_src_pipe_f : 5; + u32 cmdq_opcode_f : 2; + u32 cmdq_rep_f : 1; + u32 reserved0 : 12; +}; +union ipa_hwio_def_ipa_hps_dps_cmdq_data_rd_0_u { + struct ipa_hwio_def_ipa_hps_dps_cmdq_data_rd_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_hps_dps_cmdq_status_s { + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 5; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_hps_dps_cmdq_status_u { + struct ipa_hwio_def_ipa_hps_dps_cmdq_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_s { + u32 cmdq_empty : 23; + u32 reserved0 : 9; +}; +union ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_u { + struct ipa_hwio_def_ipa_hps_dps_cmdq_status_empty_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_hps_dps_cmdq_count_s { + u32 fifo_count : 5; + u32 reserved0 : 27; +}; +union ipa_hwio_def_ipa_hps_dps_cmdq_count_u { + struct ipa_hwio_def_ipa_hps_dps_cmdq_count_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dps_tx_cmdq_cmd_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 3; + u32 reserved0 : 2; + u32 rd_req : 1; + u32 reserved1 : 24; +}; +union ipa_hwio_def_ipa_dps_tx_cmdq_cmd_u { + struct ipa_hwio_def_ipa_dps_tx_cmdq_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dps_tx_cmdq_data_rd_0_s { + u32 cmdq_ctx_id_f : 4; + u32 cmdq_src_id_f : 8; + u32 cmdq_src_pipe_f : 5; + u32 cmdq_opcode_f : 2; + u32 cmdq_rep_f : 1; + u32 reserved0 : 12; +}; +union ipa_hwio_def_ipa_dps_tx_cmdq_data_rd_0_u { + struct ipa_hwio_def_ipa_dps_tx_cmdq_data_rd_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dps_tx_cmdq_status_s { + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; +union ipa_hwio_def_ipa_dps_tx_cmdq_status_u { + struct ipa_hwio_def_ipa_dps_tx_cmdq_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dps_tx_cmdq_status_empty_s { + u32 cmdq_empty : 8; + u32 reserved0 : 24; +}; +union ipa_hwio_def_ipa_dps_tx_cmdq_status_empty_u { + struct ipa_hwio_def_ipa_dps_tx_cmdq_status_empty_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_dps_tx_cmdq_count_s { + u32 fifo_count : 7; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_dps_tx_cmdq_count_u { + struct ipa_hwio_def_ipa_dps_tx_cmdq_count_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_en_s { + u32 bitmap : 3; + u32 reserved0 : 29; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_en_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_en_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_wr_n_rd_sel_s { + u32 bitmap : 3; + u32 reserved0 : 29; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_wr_n_rd_sel_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_wr_n_rd_sel_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_cli_mux_s { + u32 all_cli_mux_concat : 12; + u32 reserved0 : 20; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_cli_mux_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_cli_mux_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_0_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_0_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_0_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_1_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_1_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_1_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_2_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_2_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_2_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_3_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_3_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_comp_val_3_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_0_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_0_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_0_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_1_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_1_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_1_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_2_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_2_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_2_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_3_cli_n_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_3_cli_n_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_el_mask_val_3_cli_n_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_hw_snif_legacy_rx_s { + u32 src_group_sel : 2; + u32 reserved0 : 30; +}; +union ipa_hwio_def_ipa_log_buf_hw_snif_legacy_rx_u { + struct ipa_hwio_def_ipa_log_buf_hw_snif_legacy_rx_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ackmngr_cmdq_cmd_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 5; + u32 rd_req : 1; + u32 reserved0 : 24; +}; +union ipa_hwio_def_ipa_ackmngr_cmdq_cmd_u { + struct ipa_hwio_def_ipa_ackmngr_cmdq_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ackmngr_cmdq_data_rd_s { + u32 cmdq_src_id : 8; + u32 cmdq_length : 16; + u32 cmdq_origin : 1; + u32 cmdq_sent : 1; + u32 cmdq_src_id_valid : 1; + u32 reserved0 : 5; +}; +union ipa_hwio_def_ipa_ackmngr_cmdq_data_rd_u { + struct ipa_hwio_def_ipa_ackmngr_cmdq_data_rd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ackmngr_cmdq_status_s { + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; +union ipa_hwio_def_ipa_ackmngr_cmdq_status_u { + struct ipa_hwio_def_ipa_ackmngr_cmdq_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ackmngr_cmdq_status_empty_s { + u32 cmdq_empty : 10; + u32 reserved0 : 22; +}; +union ipa_hwio_def_ipa_ackmngr_cmdq_status_empty_u { + struct ipa_hwio_def_ipa_ackmngr_cmdq_status_empty_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ackmngr_cmdq_count_s { + u32 fifo_count : 7; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_ackmngr_cmdq_count_u { + struct ipa_hwio_def_ipa_ackmngr_cmdq_count_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_fifo_status_ctrl_s { + u32 ipa_gsi_fifo_status_port_sel : 5; + u32 ipa_gsi_fifo_status_en : 1; + u32 reserved0 : 26; +}; +union ipa_hwio_def_ipa_gsi_fifo_status_ctrl_u { + struct ipa_hwio_def_ipa_gsi_fifo_status_ctrl_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_tlv_fifo_status_s { + u32 rd_addr : 9; + u32 wr_addr : 9; + u32 empty : 1; + u32 reserved0 : 11; + u32 fsm_state : 2; +}; +union ipa_hwio_def_ipa_gsi_tlv_fifo_status_u { + struct ipa_hwio_def_ipa_gsi_tlv_fifo_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_tlv_pub_fifo_status_s { + u32 rd_addr_pub : 9; + u32 wr_addr : 9; + u32 empty_pub : 1; + u32 reserved0 : 11; + u32 fsm_state : 2; +}; +union ipa_hwio_def_ipa_gsi_tlv_pub_fifo_status_u { + struct ipa_hwio_def_ipa_gsi_tlv_pub_fifo_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_aos_fifo_status_s { + u32 rd_addr : 10; + u32 wr_addr : 10; + u32 empty : 1; + u32 reserved0 : 8; + u32 fsm_state : 3; +}; +union ipa_hwio_def_ipa_gsi_aos_fifo_status_u { + struct ipa_hwio_def_ipa_gsi_aos_fifo_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_0_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_0_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_1_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_1_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_2_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_2_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_3_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_3_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_3_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_4_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_4_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_4_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_5_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_5_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_5_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_6_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_6_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_6_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_comp_val_7_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_comp_val_7_u { + struct ipa_hwio_def_ipa_log_buf_sw_comp_val_7_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_0_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_0_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_1_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_1_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_2_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_2_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_3_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_3_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_3_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_4_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_4_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_4_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_5_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_5_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_5_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_6_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_6_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_6_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_sw_mask_val_7_s { + u32 value : 32; +}; +union ipa_hwio_def_ipa_log_buf_sw_mask_val_7_u { + struct ipa_hwio_def_ipa_log_buf_sw_mask_val_7_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 5; + u32 rd_req : 1; + u32 reserved0 : 24; +}; +union ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_u { + struct ipa_hwio_def_ipa_ntf_tx_cmdq_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ntf_tx_cmdq_data_rd_0_s { + u32 cmdq_ctx_id_f : 4; + u32 cmdq_src_id_f : 8; + u32 cmdq_src_pipe_f : 5; + u32 cmdq_opcode_f : 2; + u32 cmdq_rep_f : 1; + u32 reserved0 : 12; +}; +union ipa_hwio_def_ipa_ntf_tx_cmdq_data_rd_0_u { + struct ipa_hwio_def_ipa_ntf_tx_cmdq_data_rd_0_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_s { + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; +union ipa_hwio_def_ipa_ntf_tx_cmdq_status_u { + struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_empty_s { + u32 cmdq_empty : 23; + u32 reserved0 : 9; +}; +union ipa_hwio_def_ipa_ntf_tx_cmdq_status_empty_u { + struct ipa_hwio_def_ipa_ntf_tx_cmdq_status_empty_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ntf_tx_cmdq_count_s { + u32 fifo_count : 7; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_ntf_tx_cmdq_count_u { + struct ipa_hwio_def_ipa_ntf_tx_cmdq_count_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_s { + u32 write_cmd : 1; + u32 pop_cmd : 1; + u32 cmd_client : 5; + u32 rd_req : 1; + u32 reserved0 : 24; +}; +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_u { + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_cmd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_s { + u32 cmdq_src_id : 8; + u32 cmdq_length : 16; + u32 cmdq_origin : 1; + u32 cmdq_sent : 1; + u32 cmdq_src_id_valid : 1; + u32 reserved0 : 5; +}; +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_u { + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_data_rd_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_s { + u32 status : 1; + u32 cmdq_full : 1; + u32 cmdq_depth : 7; + u32 reserved0 : 23; +}; +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_u { + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_empty_s { + u32 cmdq_empty : 23; + u32 reserved0 : 9; +}; +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_empty_u { + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_status_empty_s + def; + u32 value; +}; +struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_count_s { + u32 fifo_count : 7; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_prod_ackmngr_cmdq_count_u { + struct ipa_hwio_def_ipa_prod_ackmngr_cmdq_count_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_spare_reg_1_s { + u32 general_config : 32; +}; +union ipa_hwio_def_ipa_spare_reg_1_u { + struct ipa_hwio_def_ipa_spare_reg_1_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_spare_reg_2_s { + u32 general_config : 32; +}; +union ipa_hwio_def_ipa_spare_reg_2_u { + struct ipa_hwio_def_ipa_spare_reg_2_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_gsi_conf_s { + u32 ipa_gsi_select : 1; + u32 reserved0 : 31; +}; +union ipa_hwio_def_ipa_gsi_conf_u { + struct ipa_hwio_def_ipa_gsi_conf_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_gsi_cfg1_n_s { + u32 ee : 4; + u32 reserved0 : 4; + u32 chid : 5; + u32 reserved1 : 3; + u32 endp_en : 1; + u32 reserved2 : 15; +}; +union ipa_hwio_def_ipa_endp_gsi_cfg1_n_u { + struct ipa_hwio_def_ipa_endp_gsi_cfg1_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_gsi_cfg_tlv_n_s { + u32 tlv_fifo_start_addr : 9; + u32 reserved0 : 7; + u32 tlv_fifo_size : 9; + u32 reserved1 : 7; +}; +union ipa_hwio_def_ipa_endp_gsi_cfg_tlv_n_u { + struct ipa_hwio_def_ipa_endp_gsi_cfg_tlv_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_gsi_cfg_aos_n_s { + u32 aos_fifo_start_addr : 10; + u32 reserved0 : 6; + u32 aos_fifo_size : 9; + u32 reserved1 : 7; +}; +union ipa_hwio_def_ipa_endp_gsi_cfg_aos_n_u { + struct ipa_hwio_def_ipa_endp_gsi_cfg_aos_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_endp_gsi_cfg2_n_s { + u32 publish_threshold : 16; + u32 reserved0 : 15; + u32 init_endp : 1; +}; +union ipa_hwio_def_ipa_endp_gsi_cfg2_n_u { + struct ipa_hwio_def_ipa_endp_gsi_cfg2_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_ctxh_ctrl_s { + u32 ctxh_lock_id : 4; + u32 reserved0 : 27; + u32 ctxh_lock : 1; +}; +union ipa_hwio_def_ipa_ctxh_ctrl_u { + struct ipa_hwio_def_ipa_ctxh_ctrl_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_irq_stts_ee_n_s { + u32 bad_snoc_access_irq : 1; + u32 reserved0 : 1; + u32 uc_irq_0 : 1; + u32 uc_irq_1 : 1; + u32 uc_irq_2 : 1; + u32 uc_irq_3 : 1; + u32 uc_in_q_not_empty_irq : 1; + u32 uc_rx_cmd_q_not_full_irq : 1; + u32 proc_to_uc_ack_q_not_empty_irq : 1; + u32 rx_err_irq : 1; + u32 deaggr_err_irq : 1; + u32 tx_err_irq : 1; + u32 step_mode_irq : 1; + u32 proc_err_irq : 1; + u32 tx_suspend_irq : 1; + u32 tx_holb_drop_irq : 1; + u32 bam_gsi_idle_irq : 1; + u32 pipe_yellow_marker_below_irq : 1; + u32 pipe_red_marker_below_irq : 1; + u32 pipe_yellow_marker_above_irq : 1; + u32 pipe_red_marker_above_irq : 1; + u32 ucp_irq : 1; + u32 dcmp_irq : 1; + u32 gsi_ee_irq : 1; + u32 gsi_ipa_if_tlv_rcvd_irq : 1; + u32 gsi_uc_irq : 1; + u32 reserved1 : 6; +}; +union ipa_hwio_def_ipa_irq_stts_ee_n_u { + struct ipa_hwio_def_ipa_irq_stts_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_irq_en_ee_n_s { + u32 bad_snoc_access_irq_en : 1; + u32 reserved0 : 1; + u32 uc_irq_0_irq_en : 1; + u32 uc_irq_1_irq_en : 1; + u32 uc_irq_2_irq_en : 1; + u32 uc_irq_3_irq_en : 1; + u32 uc_in_q_not_empty_irq_en : 1; + u32 uc_rx_cmd_q_not_full_irq_en : 1; + u32 proc_to_uc_ack_q_not_empty_irq_en : 1; + u32 rx_err_irq_en : 1; + u32 deaggr_err_irq_en : 1; + u32 tx_err_irq_en : 1; + u32 step_mode_irq_en : 1; + u32 proc_err_irq_en : 1; + u32 tx_suspend_irq_en : 1; + u32 tx_holb_drop_irq_en : 1; + u32 bam_gsi_idle_irq_en : 1; + u32 pipe_yellow_marker_below_irq_en : 1; + u32 pipe_red_marker_below_irq_en : 1; + u32 pipe_yellow_marker_above_irq_en : 1; + u32 pipe_red_marker_above_irq_en : 1; + u32 ucp_irq_en : 1; + u32 dcmp_irq_en : 1; + u32 gsi_ee_irq_en : 1; + u32 gsi_ipa_if_tlv_rcvd_irq_en : 1; + u32 gsi_uc_irq_en : 1; + u32 reserved1 : 6; +}; +union ipa_hwio_def_ipa_irq_en_ee_n_u { + struct ipa_hwio_def_ipa_irq_en_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_snoc_fec_ee_n_s { + u32 client : 8; + u32 qmb_index : 1; + u32 reserved0 : 3; + u32 tid : 4; + u32 reserved1 : 15; + u32 read_not_write : 1; +}; +union ipa_hwio_def_ipa_snoc_fec_ee_n_u { + struct ipa_hwio_def_ipa_snoc_fec_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_fec_addr_ee_n_s { + u32 addr : 32; +}; +union ipa_hwio_def_ipa_fec_addr_ee_n_u { + struct ipa_hwio_def_ipa_fec_addr_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_fec_attr_ee_n_s { + u32 opcode : 6; + u32 misc1 : 2; + u32 pipe_num : 5; + u32 misc2 : 19; +}; +union ipa_hwio_def_ipa_fec_attr_ee_n_u { + struct ipa_hwio_def_ipa_fec_attr_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_suspend_irq_info_ee_n_s { + u32 endpoints : 23; + u32 reserved0 : 9; +}; +union ipa_hwio_def_ipa_suspend_irq_info_ee_n_u { + struct ipa_hwio_def_ipa_suspend_irq_info_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_suspend_irq_en_ee_n_s { + u32 endpoints : 23; + u32 reserved0 : 9; +}; +union ipa_hwio_def_ipa_suspend_irq_en_ee_n_u { + struct ipa_hwio_def_ipa_suspend_irq_en_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_holb_drop_irq_info_ee_n_s { + u32 endpoints : 23; + u32 reserved0 : 9; +}; +union ipa_hwio_def_ipa_holb_drop_irq_info_ee_n_u { + struct ipa_hwio_def_ipa_holb_drop_irq_info_ee_n_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_status_addr_s { + u32 start_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_status_addr_u { + struct ipa_hwio_def_ipa_log_buf_status_addr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_status_addr_msb_s { + u32 start_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_status_addr_msb_u { + struct ipa_hwio_def_ipa_log_buf_status_addr_msb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_status_write_ptr_s { + u32 write_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_status_write_ptr_u { + struct ipa_hwio_def_ipa_log_buf_status_write_ptr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_status_write_ptr_msb_s { + u32 write_addr : 32; +}; +union ipa_hwio_def_ipa_log_buf_status_write_ptr_msb_u { + struct ipa_hwio_def_ipa_log_buf_status_write_ptr_msb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_status_cfg_s { + u32 size : 16; + u32 enable : 1; + u32 reserved0 : 15; +}; +union ipa_hwio_def_ipa_log_buf_status_cfg_u { + struct ipa_hwio_def_ipa_log_buf_status_cfg_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_log_buf_status_ram_ptr_s { + u32 read_ptr : 16; + u32 write_ptr : 16; +}; +union ipa_hwio_def_ipa_log_buf_status_ram_ptr_u { + struct ipa_hwio_def_ipa_log_buf_status_ram_ptr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_sys_addr_s { + u32 addr : 32; +}; +union ipa_hwio_def_ipa_uc_qmb_sys_addr_u { + struct ipa_hwio_def_ipa_uc_qmb_sys_addr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_sys_addr_msb_s { + u32 addr_msb : 32; +}; +union ipa_hwio_def_ipa_uc_qmb_sys_addr_msb_u { + struct ipa_hwio_def_ipa_uc_qmb_sys_addr_msb_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_local_addr_s { + u32 addr : 17; + u32 reserved0 : 15; +}; +union ipa_hwio_def_ipa_uc_qmb_local_addr_u { + struct ipa_hwio_def_ipa_uc_qmb_local_addr_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_length_s { + u32 length : 7; + u32 reserved0 : 25; +}; +union ipa_hwio_def_ipa_uc_qmb_length_u { + struct ipa_hwio_def_ipa_uc_qmb_length_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_trigger_s { + u32 direction : 1; + u32 reserved0 : 3; + u32 posting : 2; + u32 reserved1 : 26; +}; +union ipa_hwio_def_ipa_uc_qmb_trigger_u { + struct ipa_hwio_def_ipa_uc_qmb_trigger_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_pending_tid_s { + u32 tid : 6; + u32 reserved0 : 2; + u32 error_bus : 1; + u32 reserved1 : 3; + u32 error_max_os : 1; + u32 reserved2 : 3; + u32 error_max_comp : 1; + u32 reserved3 : 3; + u32 error_security : 1; + u32 reserved4 : 11; +}; +union ipa_hwio_def_ipa_uc_qmb_pending_tid_u { + struct ipa_hwio_def_ipa_uc_qmb_pending_tid_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_completed_rd_fifo_peek_s { + u32 tid : 6; + u32 reserved0 : 2; + u32 error : 1; + u32 reserved1 : 3; + u32 valid : 1; + u32 reserved2 : 19; +}; +union ipa_hwio_def_ipa_uc_qmb_completed_rd_fifo_peek_u { + struct ipa_hwio_def_ipa_uc_qmb_completed_rd_fifo_peek_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_completed_wr_fifo_peek_s { + u32 tid : 6; + u32 reserved0 : 2; + u32 error : 1; + u32 reserved1 : 3; + u32 valid : 1; + u32 reserved2 : 19; +}; +union ipa_hwio_def_ipa_uc_qmb_completed_wr_fifo_peek_u { + struct ipa_hwio_def_ipa_uc_qmb_completed_wr_fifo_peek_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_misc_s { + u32 user : 10; + u32 reserved0 : 2; + u32 rd_priority : 2; + u32 reserved1 : 2; + u32 wr_priority : 2; + u32 reserved2 : 2; + u32 ooord : 1; + u32 reserved3 : 3; + u32 ooowr : 1; + u32 reserved4 : 3; + u32 swap : 1; + u32 irq_coal : 1; + u32 posted_stall : 1; + u32 qmb_hready_bcr : 1; +}; +union ipa_hwio_def_ipa_uc_qmb_misc_u { + struct ipa_hwio_def_ipa_uc_qmb_misc_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_status_s { + u32 max_outstanding_rd : 4; + u32 outstanding_rd_cnt : 4; + u32 completed_rd_cnt : 4; + u32 completed_rd_fifo_full : 1; + u32 reserved0 : 3; + u32 max_outstanding_wr : 4; + u32 outstanding_wr_cnt : 4; + u32 completed_wr_cnt : 4; + u32 completed_wr_fifo_full : 1; + u32 reserved1 : 3; +}; +union ipa_hwio_def_ipa_uc_qmb_status_u { + struct ipa_hwio_def_ipa_uc_qmb_status_s def; + u32 value; +}; +struct ipa_hwio_def_ipa_uc_qmb_bus_attrib_s { + u32 memtype : 3; + u32 reserved0 : 1; + u32 noallocate : 1; + u32 reserved1 : 3; + u32 innershared : 1; + u32 reserved2 : 3; + u32 shared : 1; + u32 reserved3 : 19; +}; +union ipa_hwio_def_ipa_uc_qmb_bus_attrib_u { + struct ipa_hwio_def_ipa_uc_qmb_bus_attrib_s def; + u32 value; +}; +#endif diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_pkt_cntxt.h b/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_pkt_cntxt.h new file mode 100644 index 000000000000..38ee56d15a38 --- /dev/null +++ b/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_pkt_cntxt.h @@ -0,0 +1,190 @@ +/* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#if !defined(_IPA_PKT_CNTXT_H_) +#define _IPA_PKT_CNTXT_H_ + +#define IPA_HW_PKT_CTNTX_MAX 0x10 +#define IPA_HW_NUM_SAVE_PKT_CTNTX 0x8 +#define IPA_HW_PKT_CTNTX_START_ADDR 0xE434CA00 +#define IPA_HW_PKT_CTNTX_SIZE (sizeof(ipa_pkt_ctntx_opcode_state_s) + \ + sizeof(ipa_pkt_ctntx_u)) + +/* + * Packet Context States + */ +enum ipa_hw_pkt_cntxt_state_e { + IPA_HW_PKT_CNTXT_STATE_HFETCHER_INIT = 1, + IPA_HW_PKT_CNTXT_STATE_HFETCHER_DMAR, + IPA_HW_PKT_CNTXT_STATE_HFETCHER_DMAR_REP, + IPA_HW_PKT_CNTXT_STATE_H_DCPH, + IPA_HW_PKT_CNTXT_STATE_PKT_PARSER, + IPA_HW_PKT_CNTXT_STATE_FILTER_NAT, + IPA_HW_PKT_CNTXT_STATE_ROUTER, + IPA_HW_PKT_CNTXT_STATE_HDRI, + IPA_HW_PKT_CNTXT_STATE_UCP, + IPA_HW_PKT_CNTXT_STATE_ENQUEUER, + IPA_HW_PKT_CNTXT_STATE_DFETCHER, + IPA_HW_PKT_CNTXT_STATE_D_DCPH, + IPA_HW_PKT_CNTXT_STATE_DISPATCHER, + IPA_HW_PKT_CNTXT_STATE_TX, + IPA_HW_PKT_CNTXT_STATE_TX_ZLT, + IPA_HW_PKT_CNTXT_STATE_DFETCHER_DMAR, + IPA_HW_PKT_CNTXT_STATE_DCMP, +}; + +/* + * Packet Context fields as received from VI/Design + */ +struct ipa_pkt_ctntx_s { + u64 opcode : 8; + u64 state : 5; + u64 not_used_1 : 2; + u64 tx_pkt_dma_done : 1; + u64 exc_deagg : 1; + u64 exc_pkt_version : 1; + u64 exc_pkt_len : 1; + u64 exc_threshold : 1; + u64 exc_sw : 1; + u64 exc_nat : 1; + u64 exc_frag_miss : 1; + u64 filter_bypass : 1; + u64 router_bypass : 1; + u64 nat_bypass : 1; + u64 hdri_bypass : 1; + u64 dcph_bypass : 1; + u64 security_credentials_select : 1; + u64 pkt_2nd_pass : 1; + u64 xlat_bypass : 1; + u64 dcph_valid : 1; + u64 ucp_on : 1; + u64 replication : 1; + u64 src_status_en : 1; + u64 dest_status_en : 1; + u64 frag_status_en : 1; + u64 eot_dest : 1; + u64 eot_notif : 1; + u64 prev_eot_dest : 1; + u64 src_hdr_len : 8; + u64 tx_valid_sectors : 8; + u64 rx_flags : 8; + u64 rx_packet_length : 16; + u64 revised_packet_length : 16; + u64 frag_en : 1; + u64 frag_bypass : 1; + u64 frag_process : 1; + u64 notif_pipe : 5; + u64 src_id : 8; + u64 tx_pkt_transferred : 1; + u64 src_pipe : 5; + u64 dest_pipe : 5; + u64 frag_pipe : 5; + u64 ihl_offset : 8; + u64 protocol : 8; + u64 tos : 8; + u64 id : 16; + u64 v6_reserved : 4; + u64 ff : 1; + u64 mf : 1; + u64 pkt_israg : 1; + u64 tx_holb_timer_overflow : 1; + u64 tx_holb_timer_running : 1; + u64 trnseq_0 : 3; + u64 trnseq_1 : 3; + u64 trnseq_2 : 3; + u64 trnseq_3 : 3; + u64 trnseq_4 : 3; + u64 trnseq_ex_length : 8; + u64 trnseq_4_length : 8; + u64 trnseq_4_offset : 8; + u64 dps_tx_pop_cnt : 2; + u64 dps_tx_push_cnt : 2; + u64 vol_ic_dcph_cfg : 1; + u64 vol_ic_tag_stts : 1; + u64 vol_ic_pxkt_init_e : 1; + u64 vol_ic_pkt_init : 1; + u64 tx_holb_counter : 32; + u64 trnseq_0_length : 8; + u64 trnseq_0_offset : 8; + u64 trnseq_1_length : 8; + u64 trnseq_1_offset : 8; + u64 trnseq_2_length : 8; + u64 trnseq_2_offset : 8; + u64 trnseq_3_length : 8; + u64 trnseq_3_offset : 8; + u64 dmar_valid_length : 16; + u64 dcph_valid_length : 16; + u64 frag_hdr_offset : 9; + u64 ip_payload_offset : 9; + u64 frag_rule : 4; + u64 frag_table : 1; + u64 frag_hit : 1; + u64 data_cmdq_ptr : 8; + u64 filter_result : 6; + u64 router_result : 6; + u64 nat_result : 6; + u64 hdri_result : 6; + u64 dcph_result : 6; + u64 dcph_result_valid : 1; + u32 not_used_2 : 4; + u64 tx_pkt_suspended : 1; + u64 tx_pkt_dropped : 1; + u32 not_used_3 : 3; + u64 metadata_valid : 1; + u64 metadata_type : 4; + u64 ul_cs_start_diff : 9; + u64 cs_disable_trlr_vld_bit : 1; + u64 cs_required : 1; + u64 dest_hdr_len : 8; + u64 fr_l : 1; + u64 fl_h : 1; + u64 fr_g : 1; + u64 fr_ret : 1; + u64 fr_rule_id : 10; + u64 rt_l : 1; + u64 rt_h : 1; + u64 rtng_tbl_index : 5; + u64 rt_match : 1; + u64 rt_rule_id : 10; + u64 nat_tbl_index : 13; + u64 nat_type : 2; + u64 hdr_l : 1; + u64 header_offset : 10; + u64 not_used_4 : 1; + u64 filter_result_valid : 1; + u64 router_result_valid : 1; + u64 nat_result_valid : 1; + u64 hdri_result_valid : 1; + u64 not_used_5 : 1; + u64 stream_id : 8; + u64 not_used_6 : 6; + u64 dcph_context_index : 2; + u64 dcph_cfg_size : 16; + u64 dcph_cfg_count : 32; + u64 tag_info : 48; + u64 ucp_cmd_id : 16; + u64 metadata : 32; + u64 ucp_cmd_params : 32; + u64 nat_ip_address : 32; + u64 nat_ip_cs_diff : 16; + u64 frag_dest_pipe : 5; + u64 frag_nat_type : 2; + u64 fragr_ret : 1; + u64 frag_protocol : 8; + u64 src_ip_address : 32; + u64 dest_ip_address : 32; + u64 not_used_7 : 37; + u64 frag_hdr_l : 1; + u64 frag_header_offset : 10; + u64 frag_id : 16; +} __packed; + +#endif /* #if !defined(_IPA_PKT_CNTXT_H_) */ diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_hw_common_ex.h b/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_hw_common_ex.h index 9fdc926cb0d7..dfd95f7c2d5b 100644 --- a/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_hw_common_ex.h +++ b/drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_hw_common_ex.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. */ #if !defined(_IPA_HW_COMMON_EX_H_) #define _IPA_HW_COMMON_EX_H_ @@ -505,6 +505,107 @@ enum ipa_hw_irq_srcs_e { #define IPA_GSI_ADDR 0x00006000 #define IPA_GSI_SIZE round_up(5376, sizeof(u32)) +#define IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(reg_name, var_name) \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \ + (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_A7_EE].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \ + (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_Q6_EE].var_name }, \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE), \ + (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_REG_SAVE_HWP_GSI_EE].\ + var_name } + +/* + * Macro to define a particular register cfg entry for all GSI EE + * register + */ +#define IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(reg_name, var_name) \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[0].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[1].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[2].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[3].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[4].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[5].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[6].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[7].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[8].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[9].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[10].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[11].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[12].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[13].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[14].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 15), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[15].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 16), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[16].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 17), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[17].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[18].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 19), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[19].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[0].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name } + +#define IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(reg_name, var_name) \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[0].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[1].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[2].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[3].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[4].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[5].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[6].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[7].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[8].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[9].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[10].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[11].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[12].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[13].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[14].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 15), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[15].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 16), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[16].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 17), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[17].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[18].var_name }, \ + { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \ + (u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name } + /* * Macro to define a particular register cfg entry for all pipe * indexed register diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.c b/drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.c index 22f1d3a723a8..d531b024b83d 100644 --- a/drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.c +++ b/drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. */ #include "ipa_reg_dump.h" #include "ipa_access_control.h" @@ -52,12 +52,18 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = { GEN_SRC_DST_ADDR_MAP(IPA_STATE_DFETCHER, ipa.gen, ipa_state_dfetcher), +#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5) GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER_MASK_0, ipa.gen, ipa_state_fetcher_mask_0), GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER_MASK_1, ipa.gen, ipa_state_fetcher_mask_1), +#else + GEN_SRC_DST_ADDR_MAP(IPA_STATE_FETCHER_MASK, + ipa.gen, + ipa_state_fetcher_mask), +#endif GEN_SRC_DST_ADDR_MAP(IPA_STATE_GSI_AOS, ipa.gen, ipa_state_gsi_aos), @@ -115,9 +121,6 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = { GEN_SRC_DST_ADDR_MAP(IPA_LOG_BUF_HW_CMD_RAM_PTR, ipa.gen, ipa_log_buf_hw_cmd_ram_ptr), - GEN_SRC_DST_ADDR_MAP(IPA_STATE_DPL_FIFO, - ipa.gen, - ipa_state_dpl_fifo), GEN_SRC_DST_ADDR_MAP(IPA_COMP_HW_VERSION, ipa.gen, ipa_comp_hw_version), @@ -172,12 +175,26 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = { GEN_SRC_DST_ADDR_MAP(IPA_RSRC_GRP_CFG, ipa.gen, ipa_rsrc_grp_cfg), - GEN_SRC_DST_ADDR_MAP(IPA_PIPELINE_DISABLE, - ipa.gen, - ipa_pipeline_disable), GEN_SRC_DST_ADDR_MAP(IPA_COMP_CFG, ipa.gen, ipa_comp_cfg), +#if defined(CONFIG_IPA3_REGDUMP_IPA_4_1) + GEN_SRC_DST_ADDR_MAP(IPA_GSI_CONF, + ipa.gen, + ipa_gsi_conf), + GEN_SRC_DST_ADDR_MAP(IPA_TAG_TIMER, + ipa.gen, + ipa_tag_timer), + GEN_SRC_DST_ADDR_MAP(IPA_BCR, + ipa.gen, + ipa_bcr), +#else + GEN_SRC_DST_ADDR_MAP(IPA_STATE_DPL_FIFO, + ipa.gen, + ipa_state_dpl_fifo), + GEN_SRC_DST_ADDR_MAP(IPA_PIPELINE_DISABLE, + ipa.gen, + ipa_pipeline_disable), GEN_SRC_DST_ADDR_MAP(IPA_STATE_NLO_AGGR, ipa.gen, ipa_state_nlo_aggr), @@ -213,12 +230,13 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = { ipa_nlo_vp_qbap_open), /* Debug Registers */ - GEN_SRC_DST_ADDR_MAP(IPA_DEBUG_DATA, - ipa.dbg, - ipa_debug_data), GEN_SRC_DST_ADDR_MAP(IPA_STEP_MODE_BREAKPOINTS, ipa.dbg, ipa_step_mode_breakpoints), +#endif + GEN_SRC_DST_ADDR_MAP(IPA_DEBUG_DATA, + ipa.dbg, + ipa_debug_data), GEN_SRC_DST_ADDR_MAP(IPA_STEP_MODE_STATUS, ipa.dbg, ipa_step_mode_status), @@ -352,33 +370,38 @@ static struct map_src_dst_addr_s ipa_regs_to_save_array[] = { ipa_src_rsrc_grp_01_rsrc_type_n), IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_23_RSRC_TYPE_n, ipa_src_rsrc_grp_23_rsrc_type_n), +#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5) IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(IPA_SRC_RSRC_GRP_45_RSRC_TYPE_n, ipa_src_rsrc_grp_45_rsrc_type_n), +#endif /* Destination Resource Group Config Registers */ IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_01_RSRC_TYPE_n, ipa_dst_rsrc_grp_01_rsrc_type_n), IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_23_RSRC_TYPE_n, ipa_dst_rsrc_grp_23_rsrc_type_n), +#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5) IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(IPA_DST_RSRC_GRP_45_RSRC_TYPE_n, ipa_dst_rsrc_grp_45_rsrc_type_n), - +#endif /* Source Resource Group Count Registers */ IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP( IPA_SRC_RSRC_GRP_0123_RSRC_TYPE_CNT_n, ipa_src_rsrc_grp_0123_rsrc_type_cnt_n), +#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5) IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP( IPA_SRC_RSRC_GRP_4567_RSRC_TYPE_CNT_n, ipa_src_rsrc_grp_4567_rsrc_type_cnt_n), - +#endif /* Destination Resource Group Count Registers */ IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP( IPA_DST_RSRC_GRP_0123_RSRC_TYPE_CNT_n, ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n), +#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5) IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP( IPA_DST_RSRC_GRP_4567_RSRC_TYPE_CNT_n, ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n), - +#endif /* * ===================================================================== * GSI register definitions begin here... @@ -968,6 +991,7 @@ void ipa_save_registers(void) } } +#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5) if (ipa3_ctx->do_ram_collection_on_crash) { for (i = 0; i < IPA_IU_SIZE / sizeof(u32); i++) { ipa_reg_save.ipa.ipa_iu_ptr[i] = @@ -1000,7 +1024,7 @@ void ipa_save_registers(void) IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_seq_ptr); IPALOG_VnP_ADDRS(ipa_reg_save.ipa.ipa_gsi_ptr); } - +#endif ipa_reg_save_anomaly_check(); IPAERR("Completed\n"); @@ -1493,13 +1517,15 @@ int ipa_reg_save_init(u32 value) i++) *(ipa_regs_to_save_array[num_regs + i].dst_addr) = 0x0; +#if defined(CONFIG_IPA3_REGDUMP_IPA_4_1) + return 0; +#else ipa_reg_save.ipa.ipa_gsi_ptr = NULL; ipa_reg_save.ipa.ipa_seq_ptr = NULL; ipa_reg_save.ipa.ipa_hram_ptr = NULL; ipa_reg_save.ipa.ipa_mbox_ptr = NULL; ipa_reg_save.ipa.ipa_sram_ptr = NULL; ipa_reg_save.ipa.ipa_iu_ptr = NULL; - if (ipa3_ctx->do_ram_collection_on_crash) { ipa_reg_save.ipa.ipa_iu_ptr = alloc_and_init(IPA_IU_SIZE, value); @@ -1543,7 +1569,6 @@ int ipa_reg_save_init(u32 value) goto alloc_fail2; } } - return 0; alloc_fail2: @@ -1553,6 +1578,7 @@ alloc_fail2: kfree(ipa_reg_save.ipa.ipa_sram_ptr); kfree(ipa_reg_save.ipa.ipa_iu_ptr); iounmap(ipa3_ctx->reg_collection_base); +#endif alloc_fail1: return -ENOMEM; } diff --git a/drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.h b/drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.h index 50f8052b17fd..377931ecf6f3 100644 --- a/drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.h +++ b/drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. */ #if !defined(_IPA_REG_DUMP_H_) #define _IPA_REG_DUMP_H_ @@ -247,12 +247,12 @@ struct map_src_dst_addr_s { * indexed register */ #define IPA_REG_SAVE_CFG_ENTRY_GEN_EE(reg_name, var_name) \ - ({ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \ + { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \ (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_Q6_EE].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \ (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_A7_EE].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_HWP_EE), \ - (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_HWP_EE].var_name }) + (u32 *)&ipa_reg_save.ipa.gen_ee[IPA_HW_HWP_EE].var_name } #define IPA_REG_SAVE_CFG_ENTRY_GSI_FIFO(reg_name, var_name, index) \ { GEN_SCALER_REG_OFST(reg_name), \ @@ -270,7 +270,7 @@ struct map_src_dst_addr_s { * group register */ #define IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_GRP(reg_name, var_name) \ - ({ GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[0].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[1].var_name }, \ @@ -279,24 +279,24 @@ struct map_src_dst_addr_s { { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[3].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ - (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[4].var_name }) + (u32 *)&ipa_reg_save.ipa.src_rsrc_grp[4].var_name } /* * Macro to define a particular register cfg entry for all resource * group register */ #define IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_GRP(reg_name, var_name) \ - ({ GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ (u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[0].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ - (u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[1].var_name }) + (u32 *)&ipa_reg_save.ipa.dst_rsrc_grp[1].var_name } /* * Macro to define a particular register cfg entry for all source * resource group count register */ #define IPA_REG_SAVE_CFG_ENTRY_SRC_RSRC_CNT_GRP(reg_name, var_name) \ - ({ GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[0].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[1].var_name }, \ @@ -305,142 +305,41 @@ struct map_src_dst_addr_s { { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[3].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 4), \ - (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[4].var_name }) + (u32 *)&ipa_reg_save.ipa.src_rsrc_cnt[4].var_name } /* * Macro to define a particular register cfg entry for all dest * resource group count register */ #define IPA_REG_SAVE_CFG_ENTRY_DST_RSRC_CNT_GRP(reg_name, var_name) \ - ({ GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[0].var_name }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ - (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[1].var_name }) - -#define IPA_REG_SAVE_CFG_ENTRY_GSI_GENERAL_EE(reg_name, var_name) \ - ({ GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE), \ - (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_A7_EE].var_name }, \ - { GEN_1xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE), \ - (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_HW_Q6_EE].var_name }, \ - { GEN_1xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE), \ - (u32 *)&ipa_reg_save.gsi.gen_ee[IPA_REG_SAVE_HWP_GSI_EE].\ - var_name }) - -/* - * Macro to define a particular register cfg entry for all GSI EE - * register - */ -#define IPA_REG_SAVE_CFG_ENTRY_GSI_CH_CNTXT(reg_name, var_name) \ - ({ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[0].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[1].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[2].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[3].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[4].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[5].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[6].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[7].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[8].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[9].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[10].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[11].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[12].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[13].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[14].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 15), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[15].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 16), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[16].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 17), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[17].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[18].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 19), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[19].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[0].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \ - (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name }) - -#define IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(reg_name, var_name) \ - ({ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \ - (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[0].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 1), \ - (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[1].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 2), \ - (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[2].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 3), \ - (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[3].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 4), \ - (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[4].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 5), \ - (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[5].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 6), \ - (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[6].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 7), \ - (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[7].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 8), \ - (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[8].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 9), \ - (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[9].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 10), \ - (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[10].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 11), \ - (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[11].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 12), \ - (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[12].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 13), \ - (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[13].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 14), \ - (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[14].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 15), \ - (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[15].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 16), \ - (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[16].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 17), \ - (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[17].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \ - (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[18].var_name }, \ - { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \ - (u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name }) + (u32 *)&ipa_reg_save.ipa.dst_rsrc_cnt[1].var_name } /* * Macro to define a particular register cfg entry for GSI QSB debug * registers */ #define IPA_REG_SAVE_CFG_ENTRY_GSI_QSB_DEBUG(reg_name, var_name) \ - ({ GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ (u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[0] }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ (u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[1] }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ (u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[2] }, \ { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ - (u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[3] }) + (u32 *)&ipa_reg_save.gsi.debug.gsi_qsb_debug.var_name[3] } #define IPA_REG_SAVE_RX_SPLT_CMDQ(reg_name, var_name) \ - ({ GEN_1xVECTOR_REG_OFST(reg_name, 0), \ + { GEN_1xVECTOR_REG_OFST(reg_name, 0), \ (u32 *)&ipa_reg_save.ipa.dbg.var_name[0]}, \ { GEN_1xVECTOR_REG_OFST(reg_name, 1), \ (u32 *)&ipa_reg_save.ipa.dbg.var_name[1]}, \ { GEN_1xVECTOR_REG_OFST(reg_name, 2), \ (u32 *)&ipa_reg_save.ipa.dbg.var_name[2]}, \ { GEN_1xVECTOR_REG_OFST(reg_name, 3), \ - (u32 *)&ipa_reg_save.ipa.dbg.var_name[3]}) + (u32 *)&ipa_reg_save.ipa.dbg.var_name[3]} /* * IPA HW Platform Type @@ -448,6 +347,7 @@ struct map_src_dst_addr_s { enum ipa_hw_ee_e { IPA_HW_A7_EE = 0, /* A7's execution environment */ IPA_HW_Q6_EE = 1, /* Q6's execution environment */ + IPA_HW_UC_EE = 2, /* UC's execution environment */ IPA_HW_HWP_EE = 3, /* HWP's execution environment */ IPA_HW_EE_MAX, /* Max EE to support */ }; @@ -471,10 +371,21 @@ struct ipa_gen_regs_s { ipa_state_aggr_active; struct ipa_hwio_def_ipa_state_dfetcher_s ipa_state_dfetcher; +#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5) struct ipa_hwio_def_ipa_state_fetcher_mask_0_s ipa_state_fetcher_mask_0; struct ipa_hwio_def_ipa_state_fetcher_mask_1_s ipa_state_fetcher_mask_1; +#else + struct ipa_hwio_def_ipa_gsi_conf_s + ipa_gsi_conf; + struct ipa_hwio_def_ipa_state_fetcher_mask_s + ipa_state_fetcher_mask; + struct ipa_hwio_def_ipa_tag_timer_s + ipa_tag_timer; + struct ipa_hwio_def_ipa_bcr_s + ipa_bcr; +#endif struct ipa_hwio_def_ipa_state_gsi_aos_s ipa_state_gsi_aos; struct ipa_hwio_def_ipa_state_gsi_if_s @@ -551,6 +462,7 @@ struct ipa_gen_regs_s { ipa_rsrc_grp_cfg; struct ipa_hwio_def_ipa_comp_cfg_s ipa_comp_cfg; +#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5) struct ipa_hwio_def_ipa_state_dpl_fifo_s ipa_state_dpl_fifo; struct ipa_hwio_def_ipa_pipeline_disable_s @@ -577,6 +489,7 @@ struct ipa_gen_regs_s { ipa_nlo_vp_dsm_open; struct ipa_hwio_def_ipa_nlo_vp_qbap_open_s ipa_nlo_vp_qbap_open; +#endif }; /* @@ -726,8 +639,10 @@ struct ipa_reg_save_dbg_s { ipa_debug_data; struct ipa_hwio_def_ipa_step_mode_status_s ipa_step_mode_status; +#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5) struct ipa_hwio_def_ipa_step_mode_breakpoints_s ipa_step_mode_breakpoints; +#endif struct ipa_hwio_def_ipa_rx_splt_cmdq_cmd_n_s ipa_rx_splt_cmdq_cmd_n[IPA_RX_SPLT_CMDQ_MAX]; struct ipa_hwio_def_ipa_rx_splt_cmdq_cfg_n_s @@ -854,8 +769,10 @@ struct ipa_reg_save_src_rsrc_grp_s { ipa_src_rsrc_grp_01_rsrc_type_n; struct ipa_hwio_def_ipa_src_rsrc_grp_23_rsrc_type_n_s ipa_src_rsrc_grp_23_rsrc_type_n; +#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5) struct ipa_hwio_def_ipa_src_rsrc_grp_45_rsrc_type_n_s ipa_src_rsrc_grp_45_rsrc_type_n; +#endif }; /* Source Resource Group IPA register save data struct */ @@ -864,24 +781,30 @@ struct ipa_reg_save_dst_rsrc_grp_s { ipa_dst_rsrc_grp_01_rsrc_type_n; struct ipa_hwio_def_ipa_dst_rsrc_grp_23_rsrc_type_n_s ipa_dst_rsrc_grp_23_rsrc_type_n; +#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5) struct ipa_hwio_def_ipa_dst_rsrc_grp_45_rsrc_type_n_s ipa_dst_rsrc_grp_45_rsrc_type_n; +#endif }; /* Source Resource Group Count IPA register save data struct */ struct ipa_reg_save_src_rsrc_cnt_s { struct ipa_hwio_def_ipa_src_rsrc_grp_0123_rsrc_type_cnt_n_s ipa_src_rsrc_grp_0123_rsrc_type_cnt_n; +#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5) struct ipa_hwio_def_ipa_src_rsrc_grp_4567_rsrc_type_cnt_n_s ipa_src_rsrc_grp_4567_rsrc_type_cnt_n; +#endif }; /* Destination Resource Group Count IPA register save data struct */ struct ipa_reg_save_dst_rsrc_cnt_s { struct ipa_hwio_def_ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n_s ipa_dst_rsrc_grp_0123_rsrc_type_cnt_n; +#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5) struct ipa_hwio_def_ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n_s ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n; +#endif }; /* GSI General register save data struct */ @@ -984,6 +907,7 @@ static u32 ipa_reg_save_gsi_ch_test_bus_selector_array[] = { HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR, HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_0, HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_SDMA_1, +#if defined(CONFIG_IPA3_REGDUMP_IPA_4_5) HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_IE_2, HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_1, HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_2, @@ -992,6 +916,7 @@ static u32 ipa_reg_save_gsi_ch_test_bus_selector_array[] = { HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_CSR_3, HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_TLV_0, HWIO_GSI_DEBUG_TEST_BUS_SELECTOR_REE_8, +#endif }; /* From 0393a19b6db07e9abcbc90186a94098c159cd6a5 Mon Sep 17 00:00:00 2001 From: Praveen Kurapati Date: Thu, 11 Mar 2021 15:43:01 +0530 Subject: [PATCH 05/11] msm: ipa3: Add smp2p changes for modem load FW Add changes wrt SMP2P for modem loading the IPA FW. Change-Id: I41d42b044d7f9020c4ff9932406bf8fb6f55db6b Signed-off-by: Praveen Kurapati --- drivers/platform/msm/ipa/ipa_v3/ipa.c | 48 +++++++++++++++++++++++++ drivers/platform/msm/ipa/ipa_v3/ipa_i.h | 3 ++ 2 files changed, 51 insertions(+) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c index b7c78df17e3d..93d2c9d75940 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c @@ -7577,6 +7577,8 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p, } } + ipa3_ctx->modem_load_ipa_fw = resource_p->modem_load_ipa_fw; + cdev = &ipa3_ctx->cdev.cdev; cdev_init(cdev, &ipa3_drv_fops); cdev->owner = THIS_MODULE; @@ -7949,6 +7951,7 @@ static int get_ipa_dts_configuration(struct platform_device *pdev, ipa_drv_res->ipa_endp_delay_wa_v2 = false; ipa_drv_res->is_eth_bridging_supported = false; ipa_drv_res->is_bw_monitor_supported = false; + ipa_drv_res->modem_load_ipa_fw = false; /* Get IPA HW Version */ result = of_property_read_u32(pdev->dev.of_node, "qcom,ipa-hw-ver", @@ -8236,6 +8239,13 @@ static int get_ipa_dts_configuration(struct platform_device *pdev, IPADBG(": gsi wdi db polling = %s\n", ipa_drv_res->gsi_wdi_db_polling ? "True" : "False"); + ipa_drv_res->modem_load_ipa_fw = + of_property_read_bool(pdev->dev.of_node, + "qcom,modem-load-ipa-fw"); + IPADBG(": Load IPA_FW by modem = %s\n", + ipa_drv_res->modem_load_ipa_fw + ? "True" : "False"); + result = of_property_read_string(pdev->dev.of_node, "qcom,use-gsi-ipa-fw", &ipa_drv_res->gsi_fw_file_name); if (!result) @@ -8964,6 +8974,27 @@ static int ipa3_attach_to_smmu(void) return 0; } +static irqreturn_t ipa_smp2p_modem_fw_load_ready_isr(int irq, void *ctxt) +{ + int result; + + if (!ipa3_ctx->smp2p_info.disabled) { + result = ipa3_attach_to_smmu(); + if (result) { + IPAERR("IPA attach to smmu failed %d\n", result); + goto bail; + } + result = ipa3_post_init(&ipa3_res, ipa3_ctx->cdev.dev); + if (result) { + IPAERR("IPA post init failed %d\n", result); + goto bail; + } + ipa3_ctx->smp2p_info.disabled = true; + } + +bail: + return IRQ_HANDLED; +} static irqreturn_t ipa3_smp2p_modem_clk_query_isr(int irq, void *ctxt) { ipa3_freeze_clock_vote_and_notify_modem(); @@ -9016,6 +9047,23 @@ static int ipa3_smp2p_probe(struct device *dev) IPAERR("fail to register smp2p irq=%d\n", irq); return -ENODEV; } + + if (ipa3_ctx->modem_load_ipa_fw) { + res = irq = of_irq_get_byname(node, "ipa-fw-load-ready"); + if (res < 0) { + IPADBG("of_irq_get_byname returned %d\n", irq); + return res; + } + + res = devm_request_threaded_irq(dev, irq, NULL, + (irq_handler_t)ipa_smp2p_modem_fw_load_ready_isr, + IRQF_TRIGGER_RISING | IRQF_ONESHOT, + "ipa_fw_load_ready", dev); + if (res) { + IPAERR("fail to register smp2p irq=%d\n", irq); + return -ENODEV; + } + } } return 0; } diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h index c8653426a0a3..3bf3fa267327 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h @@ -1704,6 +1704,7 @@ struct ipa3_smp2p_info { u32 in_base_id; bool ipa_clk_on; bool res_sent; + bool disabled; unsigned int smem_bit; struct qcom_smem_state *smem_state; }; @@ -2151,6 +2152,7 @@ struct ipa3_context { bool ipa_endp_delay_wa_v2; bool is_eth_bridging_supported; bool is_bw_monitor_supported; + bool modem_load_ipa_fw; }; struct ipa3_plat_drv_res { @@ -2222,6 +2224,7 @@ struct ipa3_plat_drv_res { bool ipa_endp_delay_wa_v2; bool is_eth_bridging_supported; bool is_bw_monitor_supported; + bool modem_load_ipa_fw; }; /** From 9d8b6ff21bd89a5d6fca2e311b0ccfda32de43c9 Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Wed, 28 Apr 2021 01:23:57 +0530 Subject: [PATCH 06/11] msm: ipa3: Adding chnages to update event RP from DDR In suspend scenario while checking channel empty scenario updating the event ring RP pointer from direct register, it may cause mismatch in reading in polling context. To avoid discrepancy reading RP pointer DDR location. Change-Id: Ie198ea9ace033e31463acd974f10dccdcac45c55 Signed-off-by: Ashok Vuyyuru --- drivers/platform/msm/gsi/gsi.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/platform/msm/gsi/gsi.c b/drivers/platform/msm/gsi/gsi.c index 2c55c0711c75..79617afbd9be 100644 --- a/drivers/platform/msm/gsi/gsi.c +++ b/drivers/platform/msm/gsi/gsi.c @@ -3652,6 +3652,7 @@ EXPORT_SYMBOL(gsi_query_channel_info); int gsi_is_channel_empty(unsigned long chan_hdl, bool *is_empty) { struct gsi_chan_ctx *ctx; + struct gsi_evt_ctx *ev_ctx; spinlock_t *slock; unsigned long flags; uint64_t rp; @@ -3687,8 +3688,11 @@ int gsi_is_channel_empty(unsigned long chan_hdl, bool *is_empty) spin_lock_irqsave(slock, flags); if (ctx->props.dir == GSI_CHAN_DIR_FROM_GSI && ctx->evtr) { - rp = gsi_readl(gsi_ctx->base + - GSI_EE_n_EV_CH_k_CNTXT_4_OFFS(ctx->evtr->id, ee)); + ev_ctx = &gsi_ctx->evtr[ctx->evtr->id]; + /* Read the event ring rp from DDR to avoid mismatch */ + rp = ev_ctx->props.gsi_read_event_ring_rp(&ev_ctx->props, + ev_ctx->id, ee); + rp |= ctx->evtr->ring.rp & 0xFFFFFFFF00000000; ctx->evtr->ring.rp = rp; From 613398d2aef80a378ceb447a8f873d34447b990f Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Thu, 8 Apr 2021 18:55:39 +0530 Subject: [PATCH 07/11] msm: ipa3: Changes to read the halt command return code after some delay In some cases for updating the return code in SCRATCH register taking time after raising the global interrupt. Adding changes to wait for some time read the SCRATCH register again and also printing the test bus registers and Q6 channel state in failed scenario. Change-Id: I4112a2290739daa79629f718d9725258518aba4c Signed-off-by: Ashok Vuyyuru --- drivers/platform/msm/gsi/gsi.c | 52 +++++++++++++++++++++++++-- drivers/platform/msm/gsi/gsi_reg_v1.h | 9 +++++ drivers/platform/msm/gsi/gsi_reg_v2.h | 9 +++++ 3 files changed, 68 insertions(+), 2 deletions(-) diff --git a/drivers/platform/msm/gsi/gsi.c b/drivers/platform/msm/gsi/gsi.c index 2c55c0711c75..552873bcb462 100644 --- a/drivers/platform/msm/gsi/gsi.c +++ b/drivers/platform/msm/gsi/gsi.c @@ -4490,6 +4490,45 @@ void gsi_get_inst_ram_offset_and_size(unsigned long *base_offset, } EXPORT_SYMBOL(gsi_get_inst_ram_offset_and_size); +/* + * Dumping the Debug registers for halt issue debugging. + */ +static void gsi_dump_halt_debug_reg(unsigned int chan_idx, unsigned int ee) +{ + uint32_t val; + enum gsi_chan_state curr_state = GSI_CHAN_STATE_NOT_ALLOCATED; + + GSIERR("DEBUG_PC_FOR_DEBUG = 0x%x\n", gsi_readl(gsi_ctx->base + + GSI_EE_n_GSI_DEBUG_PC_FOR_DEBUG_OFFS)); + + GSIERR("GSI_DEBUG_BUSY_REG 0x%x\n", + gsi_readl(gsi_ctx->base + GSI_EE_n_GSI_DEBUG_BUSY_REG_OFFS)); + + GSIERR("GSI_EE_n_CNTXT_GLOB_IRQ_EN_OFFS = 0x%x\n", + gsi_readl(gsi_ctx->base + + GSI_EE_n_CNTXT_GLOB_IRQ_EN_OFFS(gsi_ctx->per.ee))); + + GSIERR("GSI_EE_n_CNTXT_GLOB_IRQ_STTS_OFFS IRQ type = 0x%x\n", + gsi_readl(gsi_ctx->base + + GSI_EE_n_CNTXT_GLOB_IRQ_STTS_OFFS(gsi_ctx->per.ee))); + + GSIERR("GSI_EE_n_CNTXT_SCRATCH_0_OFFS = 0x%x\n", + gsi_readl(gsi_ctx->base + + GSI_EE_n_CNTXT_SCRATCH_0_OFFS(gsi_ctx->per.ee))); + + if (gsi_ctx->per.ver >= GSI_VER_2_9) + GSIERR("GSI_EE_n_GSI_CH_k_SCRATCH_4_OFFS = 0x%x\n", + gsi_readl(gsi_ctx->base + + GSI_EE_n_GSI_CH_k_SCRATCH_4_OFFS(chan_idx, ee))); + + val = gsi_readl(gsi_ctx->base + + GSI_EE_n_GSI_CH_k_CNTXT_0_OFFS(chan_idx, ee)); + curr_state = (val & + GSI_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_BMSK) >> + GSI_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_SHFT; + GSIERR("Q6 channel [%d] state = %d\n", chan_idx, curr_state); +} + int gsi_halt_channel_ee(unsigned int chan_idx, unsigned int ee, int *code) { enum gsi_generic_ee_cmd_opcode op = GSI_GEN_EE_CMD_HALT_CHANNEL; @@ -4544,8 +4583,17 @@ int gsi_halt_channel_ee(unsigned int chan_idx, unsigned int ee, int *code) } if (gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code == 0) { GSIERR("No response received\n"); - res = -GSI_STATUS_ERROR; - goto free_lock; + gsi_dump_halt_debug_reg(chan_idx, ee); + usleep_range(GSI_RESET_WA_MIN_SLEEP, GSI_RESET_WA_MAX_SLEEP); + GSIERR("Reading after usleep scratch 0 reg\n"); + gsi_ctx->scratch.word0.val = gsi_readl(gsi_ctx->base + + GSI_EE_n_CNTXT_SCRATCH_0_OFFS(gsi_ctx->per.ee)); + if (gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code == 0) { + GSIERR("No response received second attempt\n"); + gsi_dump_halt_debug_reg(chan_idx, ee); + res = -GSI_STATUS_ERROR; + goto free_lock; + } } res = GSI_STATUS_SUCCESS; diff --git a/drivers/platform/msm/gsi/gsi_reg_v1.h b/drivers/platform/msm/gsi/gsi_reg_v1.h index b331863911e4..dc4403f0f9c4 100644 --- a/drivers/platform/msm/gsi/gsi_reg_v1.h +++ b/drivers/platform/msm/gsi/gsi_reg_v1.h @@ -1242,4 +1242,13 @@ #define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_THREE_N_HALF_KB_FVAL 0x4 #define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_FOUR_KB_FVAL 0x5 +#define GSI_EE_n_GSI_DEBUG_PC_FOR_DEBUG_OFFS \ + (GSI_GSI_REG_BASE_OFFS + 0x00001048) + +#define GSI_EE_n_GSI_DEBUG_BUSY_REG_OFFS \ + (GSI_GSI_REG_BASE_OFFS + 0x00001010) + +#define GSI_EE_n_GSI_CH_k_SCRATCH_4_OFFS(k, n) \ + (GSI_GSI_REG_BASE_OFFS + 0x0000f040 + 0x4000 * (n) + 0x80 * (k)) + #endif /* __GSI_REG_V1_H__ */ diff --git a/drivers/platform/msm/gsi/gsi_reg_v2.h b/drivers/platform/msm/gsi/gsi_reg_v2.h index defe28fac99c..11ce1c435969 100644 --- a/drivers/platform/msm/gsi/gsi_reg_v2.h +++ b/drivers/platform/msm/gsi/gsi_reg_v2.h @@ -1252,4 +1252,13 @@ #define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_RMSK 0xffffffff #define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_SHFT 0x0 +#define GSI_EE_n_GSI_DEBUG_PC_FOR_DEBUG_OFFS \ + (GSI_GSI_REG_BASE_OFFS + 0x00001048) + +#define GSI_EE_n_GSI_DEBUG_BUSY_REG_OFFS \ + (GSI_GSI_REG_BASE_OFFS + 0x00001010) + +#define GSI_EE_n_GSI_CH_k_SCRATCH_4_OFFS(k, n) \ + (GSI_GSI_REG_BASE_OFFS + 0x0000f040 + 0x4000 * (n) + 0x80 * (k)) + #endif /* __GSI_REG_V2_H__ */ From b1e7c45a8cf310a774d406f5bc99cbdedfcdb749 Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Wed, 28 Apr 2021 22:29:59 +0530 Subject: [PATCH 08/11] msm: ipa3: Changes to check disconnect in progress while sending data In SSR scenario while teardown the pipe there could be possibility to receive the UL data to avoid queuing the data checking for disconnect InProgress flag. Signed-off-by: Ashok Vuyyuru Change-Id: I73397e51e6e7affae71313d08356f809788db484 --- drivers/platform/msm/ipa/ipa_v3/ipa_dp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c b/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c index b2b1903f7ac9..67269292536f 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c @@ -431,6 +431,12 @@ int ipa3_send(struct ipa3_sys_context *sys, spin_lock_bh(&sys->spinlock); + if (unlikely(atomic_read(&sys->ep->disconnect_in_progress))) { + IPAERR("Pipe disconnect in progress dropping the packet\n"); + spin_unlock_bh(&sys->spinlock); + return -EFAULT; + } + for (i = 0; i < num_desc; i++) { if (!list_empty(&sys->avail_tx_wrapper_list)) { tx_pkt = list_first_entry(&sys->avail_tx_wrapper_list, @@ -1445,6 +1451,7 @@ int ipa3_teardown_sys_pipe(u32 clnt_hdl) if (IPA_CLIENT_IS_PROD(ep->client)) { do { spin_lock_bh(&ep->sys->spinlock); + atomic_set(&ep->disconnect_in_progress, 1); empty = list_empty(&ep->sys->head_desc_list); spin_unlock_bh(&ep->sys->spinlock); if (!empty) From e2030525a30f9ff7721c0d4a0813330f38ca7dea Mon Sep 17 00:00:00 2001 From: Sivan Reinstein Date: Mon, 3 May 2021 08:03:46 +0300 Subject: [PATCH 09/11] msm: gsi: add gsi profiling stats registers Add GSI profiling stats register addresses Change-Id: I38f5a27e97430e7597ab1bdc2141303add59dbb0 Acked-by: Nadav Levintov Signed-off-by: Sivan Reinstein --- drivers/platform/msm/gsi/gsi_reg_v1.h | 41 +++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/platform/msm/gsi/gsi_reg_v1.h b/drivers/platform/msm/gsi/gsi_reg_v1.h index dc4403f0f9c4..ee3de12fa3f8 100644 --- a/drivers/platform/msm/gsi/gsi_reg_v1.h +++ b/drivers/platform/msm/gsi/gsi_reg_v1.h @@ -1251,4 +1251,45 @@ #define GSI_EE_n_GSI_CH_k_SCRATCH_4_OFFS(k, n) \ (GSI_GSI_REG_BASE_OFFS + 0x0000f040 + 0x4000 * (n) + 0x80 * (k)) + +#define GSI_GSI_MCS_PROFILING_BP_CNT_LSB_OFFS \ + (GSI_GSI_REG_BASE_OFFS + 0x0000185c) +#define GSI_GSI_MCS_PROFILING_BP_CNT_LSB_RMSK 0xffffffff +#define GSI_GSI_MCS_PROFILING_BP_CNT_LSB_SHFT 0x0 + +#define GSI_GSI_MCS_PROFILING_BP_CNT_MSB_OFFS \ + (GSI_GSI_REG_BASE_OFFS + 0x00001860) +#define GSI_GSI_MCS_PROFILING_BP_CNT_MSB_RMSK 0xffffffff +#define GSI_GSI_MCS_PROFILING_BP_CNT_MSB_SHFT 0x0 + +#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_OFFS \ + (GSI_GSI_REG_BASE_OFFS + 0x00001864) +#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_RMSK 0xffffffff +#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_LSB_SHFT 0x0 + +#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_OFFS \ + (GSI_GSI_REG_BASE_OFFS + 0x00001868) +#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_RMSK 0xffffffff +#define GSI_GSI_MCS_PROFILING_BP_AND_PENDING_CNT_MSB_SHFT 0x0 + +#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_OFFS \ + (GSI_GSI_REG_BASE_OFFS + 0x0000186c) +#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_RMSK 0xffffffff +#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_LSB_SHFT 0x0 + +#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_OFFS \ + (GSI_GSI_REG_BASE_OFFS + 0x00001870) +#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_RMSK 0xffffffff +#define GSI_GSI_MCS_PROFILING_MCS_BUSY_CNT_MSB_SHFT 0x0 + +#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_OFFS \ + (GSI_GSI_REG_BASE_OFFS + 0x00001874) +#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_RMSK 0xffffffff +#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_LSB_SHFT 0x0 + +#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_OFFS \ + (GSI_GSI_REG_BASE_OFFS + 0x00001878) +#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_RMSK 0xffffffff +#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_SHFT 0x0 + #endif /* __GSI_REG_V1_H__ */ From 5a14f85c0fa1f8ccf0a814a2a8f7ce5f70096aa4 Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Thu, 6 May 2021 18:22:58 +0530 Subject: [PATCH 10/11] msm: ipa3: Changes to keep IPA clock voted in panic notifier Adding changes to avoid unclocked access in panic notifier. Increasing the IPA clock vote before saving the IPA registers. Change-Id: Ie055ffa844df45b8a65603190495bc2d1cc3f84a Signed-off-by: Ashok Vuyyuru --- drivers/platform/msm/ipa/ipa_v3/ipa.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c index 93d2c9d75940..eee1a7ecaaa2 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c @@ -6023,6 +6023,7 @@ static int ipa3_panic_notifier(struct notifier_block *this, unsigned long event, void *ptr) { int res; + struct ipa_active_client_logging_info log_info; ipa3_freeze_clock_vote_and_notify_modem(); @@ -6031,7 +6032,12 @@ static int ipa3_panic_notifier(struct notifier_block *this, if (res) IPAERR("uC panic handler failed %d\n", res); - if (atomic_read(&ipa3_ctx->ipa_clk_vote)) { + /* Make sure IPA clock voted when collecting the reg dump */ + IPA_ACTIVE_CLIENTS_PREP_SPECIAL(log_info, "PANIC_VOTE"); + res = ipa3_inc_client_enable_clks_no_block(&log_info); + if (res) { + IPAERR("IPA clk off not saving the IPA registers\n"); + } else { ipahal_print_all_regs(false); ipa_save_registers(); ipa_wigig_save_regs(); From 9a4b400adb75c34c8c81331c3baee40e1a80ec01 Mon Sep 17 00:00:00 2001 From: Sivakanth Vaka Date: Mon, 17 May 2021 11:05:43 +0530 Subject: [PATCH 11/11] ipa3: Changes to keep IPA clock voted in shutdown notifier Adding changes to avoid unclocked access in shutdown notifier. Increasing the IPA clock vote before saving the IPA registers. Signed-off-by: Sivakanth vaka --- drivers/platform/msm/ipa/ipa_v3/ipa.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c index eee1a7ecaaa2..50f571cd8320 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c @@ -9098,9 +9098,22 @@ static void ipa_smmu_update_fw_loader(void) void ipa3_plat_drv_shutdown(struct platform_device *pdev_p) { + int res; + struct ipa_active_client_logging_info log_info; + pr_debug("ipa: driver shutdown invoked for %s\n", pdev_p->dev.of_node->name); - if (ipa3_ctx && atomic_read(&ipa3_ctx->ipa_clk_vote)) { + if(unlikely(!ipa3_ctx)) + { + IPAERR("IPA driver not initialized\n"); + return; + } + /* Make sure IPA clock voted when collecting the reg dump */ + IPA_ACTIVE_CLIENTS_PREP_SPECIAL(log_info, "SHUTDOWN_VOTE"); + res = ipa3_inc_client_enable_clks_no_block(&log_info); + if (res) { + IPAERR("IPA clk off not saving the IPA registers\n"); + } else { ipahal_print_all_regs(false); ipa_save_registers(); }