mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 02:32:09 -04:00
Less anger inducing pull request for 4.11
-----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJYr5aeAAoJEAx081l5xIa+ZK4P/RD3XUsduYqziVFCRQ2n0X8r +D92F4peTnSeSq7ZcZvprv+fezUGAHbfsWFs8feYCI5quUO6pEQSPwN+wyGazUi0 4hUVB/K9Iq7U/Bj7Z/SmsU3NuWJnkNqbmvSFvUdqYK9D/kl+Tnllzap2N4cTzjwu GZOObz4n85cx94NqC3qw+7/ptL1X2MhXa+z0MzbkKyas84Bko1LwCSHRHsDKUnJc IcSpOcYZ6pSRMIsKH4Kd79Go4vWm7djXT9XL3PwDk2NcXXUOuR+cfdHqYchYaM/O iD2hvaSywBcflxSAml5x6vlXraoRd91ZZulgOObXtFfnUXdZB81TVq4uv6LU4Bx3 jLFixUZuk/TJT+W/8N10l7M6yMIFaTpNoNMc5n4IF5RNNyWba4BKnrI+f+lQiOpY mmjIaidb0t5BICnJzCD264RhCEXmP0HaDV+iQQV6y6jJRXfd1bgnOXLKP73JekzB TsbDshCoE7UO0dJ7n0LFpXSTQDTYzlazoEp14f2kFBxir5/l7r67nUlnDTvUQfuN tSRvpN/s0wqvH3o7zhmpHxyJ/ZasPMQjNCFAuUEbx8L5SKXsua0FubIzN4aVpilb XvfdFRWM/lkOT/q+8cGI/TcE3YTqEmALmGxdV/akbdNCiCg6aClyCLRE/DZhgmSQ UMFjr9wlHl5Qo/OqLKj0 =Yjfg -----END PGP SIGNATURE----- Merge tag 'drm-for-v4.11-less-shouty' of git://people.freedesktop.org/~airlied/linux Pull drm updates from Dave Airlie: "This is the main drm pull request for v4.11. Nothing too major, the tinydrm and mmu-less support should make writing smaller drivers easier for some of the simpler platforms, and there are a bunch of documentation updates. Intel grew displayport MST audio support which is hopefully useful to people, and FBC is on by default for GEN9+ (so people know where to look for regressions). AMDGPU has a lot of fixes that would like new firmware files installed for some GPUs. Other than that it's pretty scattered all over. I may have a follow up pull request as I know BenH has a bunch of AST rework and fixes and I'd like to get those in once they've been tested by AST, and I've got at least one pull request I'm just trying to get the author to fix up. Core: - drm_mm reworked - Connector list locking and iterators - Documentation updates - Format handling rework - MMU-less support for fbdev helpers - drm_crtc_from_index helper - Core CRC API - Remove drm_framebuffer_unregister_private - Debugfs cleanup - EDID/Infoframe fixes - Release callback - Tinydrm support (smaller drivers for simple hw) panel: - Add support for some new simple panels i915: - FBC by default for gen9+ - Shared dpll cleanups and docs - GEN8 powerdomain cleanup - DMC support on GLK - DP MST audio support - HuC loading support - GVT init ordering fixes - GVT IOMMU workaround fix amdgpu/radeon: - Power/clockgating improvements - Preliminary SR-IOV support - TTM buffer priority and eviction fixes - SI DPM quirks removed due to firmware fixes - Powerplay improvements - VCE/UVD powergating fixes - Cleanup SI GFX code to match CI/VI - Support for > 2 displays on 3/5 crtc asics - SI headless fixes nouveau: - Rework securre boot code in prep for GP10x secure boot - Channel recovery improvements - Initial power budget code - MMU rework preperation vmwgfx: - Bunch of fixes and cleanups exynos: - Runtime PM support for MIC driver - Cleanups to use atomic helpers - UHD Support for TM2/TM2E boards - Trigger mode fix for Rinato board etnaviv: - Shader performance fix - Command stream validator fixes - Command buffer suballocator rockchip: - CDN DisplayPort support - IOMMU support for arm64 platform imx-drm: - Fix i.MX5 TV encoder probing - Remove lower fb size limits msm: - Support for HW cursor on MDP5 devices - DSI encoder cleanup - GPU DT bindings cleanup sti: - stih410 cleanups - Create fbdev at binding - HQVDP fixes - Remove stih416 chip functionality - DVI/HDMI mode selection fixes - FPS statistic reporting omapdrm: - IRQ code cleanup dwi-hdmi bridge: - Cleanups and fixes adv-bridge: - Updates for nexus sii8520 bridge: - Add interlace mode support - Rework HDMI and lots of fixes qxl: - probing/teardown cleanups ZTE drm: - HDMI audio via SPDIF interface - Video Layer overlay plane support - Add TV encoder output device atmel-hlcdc: - Rework fbdev creation logic tegra: - OF node fix fsl-dcu: - Minor fixes mali-dp: - Assorted fixes sunxi: - Minor fix" [ This was the "fixed" pull, that still had build warnings due to people not even having build tested the result. I'm not a happy camper I've fixed the things I noticed up in this merge. - Linus ] * tag 'drm-for-v4.11-less-shouty' of git://people.freedesktop.org/~airlied/linux: (1177 commits) lib/Kconfig: make PRIME_NUMBERS not user selectable drm/tinydrm: helpers: Properly fix backlight dependency drm/tinydrm: mipi-dbi: Fix field width specifier warning drm/tinydrm: mipi-dbi: Silence: ‘cmd’ may be used uninitialized drm/sti: fix build warnings in sti_drv.c and sti_vtg.c files drm/amd/powerplay: fix PSI feature on Polars12 drm/amdgpu: refuse to reserve io mem for split VRAM buffers drm/ttm: fix use-after-free races in vm fault handling drm/tinydrm: Add support for Multi-Inno MI0283QT display dt-bindings: Add Multi-Inno MI0283QT binding dt-bindings: display/panel: Add common rotation property of: Add vendor prefix for Multi-Inno drm/tinydrm: Add MIPI DBI support drm/tinydrm: Add helper functions drm: Add DRM support for tiny LCD displays drm/amd/amdgpu: post card if there is real hw resetting performed drm/nouveau/tmr: provide backtrace when a timeout is hit drm/nouveau/pci/g92: Fix rearm drm/nouveau/drm/therm/fan: add a fallback if no fan control is specified in the vbios drm/nouveau/hwmon: expose power_max and power_crit ..
This commit is contained in:
Linus Torvalds
commit
ef96152e6a
923 changed files with 46348 additions and 22490 deletions
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@ -56,6 +56,18 @@ Required properties for V3D:
|
|||
- interrupts: The interrupt number
|
||||
See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
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||||
|
||||
Required properties for DSI:
|
||||
- compatible: Should be "brcm,bcm2835-dsi0" or "brcm,bcm2835-dsi1"
|
||||
- reg: Physical base address and length of the DSI block's registers
|
||||
- interrupts: The interrupt number
|
||||
See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
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- clocks: a) phy: The DSI PLL clock feeding the DSI analog PHY
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b) escape: The DSI ESC clock from CPRMAN
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c) pixel: The DSI pixel clock from CPRMAN
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- clock-output-names:
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The 3 clocks output from the DSI analog PHY: dsi[01]_byte,
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dsi[01]_ddr2, and dsi[01]_ddr
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[1] Documentation/devicetree/bindings/media/video-interfaces.txt
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|
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Example:
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@ -99,6 +111,29 @@ dpi: dpi@7e208000 {
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};
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};
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dsi1: dsi@7e700000 {
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compatible = "brcm,bcm2835-dsi1";
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reg = <0x7e700000 0x8c>;
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interrupts = <2 12>;
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <1>;
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clocks = <&clocks BCM2835_PLLD_DSI1>,
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<&clocks BCM2835_CLOCK_DSI1E>,
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<&clocks BCM2835_CLOCK_DSI1P>;
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clock-names = "phy", "escape", "pixel";
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clock-output-names = "dsi1_byte", "dsi1_ddr2", "dsi1_ddr";
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pitouchscreen: panel@0 {
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compatible = "raspberrypi,touchscreen";
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reg = <0>;
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<...>
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};
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};
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vec: vec@7e806000 {
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compatible = "brcm,bcm2835-vec";
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reg = <0x7e806000 0x1000>;
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|
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@ -38,10 +38,22 @@ The following input format properties are required except in "rgb 1x" and
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- adi,input-justification: The input bit justification ("left", "evenly",
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"right").
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- avdd-supply: A 1.8V supply that powers up the AVDD pin on the chip.
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- dvdd-supply: A 1.8V supply that powers up the DVDD pin on the chip.
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- pvdd-supply: A 1.8V supply that powers up the PVDD pin on the chip.
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- dvdd-3v-supply: A 3.3V supply that powers up the pin called DVDD_3V
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on the chip.
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- bgvdd-supply: A 1.8V supply that powers up the BGVDD pin. This is
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needed only for ADV7511.
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The following properties are required for ADV7533:
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- adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should
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be one of 1, 2, 3 or 4.
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- a2vdd-supply: 1.8V supply that powers up the A2VDD pin on the chip.
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- v3p3-supply: A 3.3V supply that powers up the V3P3 pin on the chip.
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- v1p2-supply: A supply that powers up the V1P2 pin on the chip. It can be
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either 1.2V or 1.8V.
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Optional properties:
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|
|
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|
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@ -1,52 +1,33 @@
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DesignWare HDMI bridge bindings
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Synopsys DesignWare HDMI TX Encoder
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===================================
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Required properties:
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- compatible: platform specific such as:
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* "snps,dw-hdmi-tx"
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* "fsl,imx6q-hdmi"
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* "fsl,imx6dl-hdmi"
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* "rockchip,rk3288-dw-hdmi"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The HDMI interrupt number
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- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,
|
||||
as described in Documentation/devicetree/bindings/clock/clock-bindings.txt,
|
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the clocks are soc specific, the clock-names should be "iahb", "isfr"
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-port@[X]: SoC specific port nodes with endpoint definitions as defined
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||||
in Documentation/devicetree/bindings/media/video-interfaces.txt,
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||||
please refer to the SoC specific binding document:
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||||
* Documentation/devicetree/bindings/display/imx/hdmi.txt
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* Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
|
||||
This document defines device tree properties for the Synopsys DesignWare HDMI
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TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
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specification by itself but is meant to be referenced by platform-specific
|
||||
device tree bindings.
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|
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Optional properties
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- reg-io-width: the width of the reg:1,4, default set to 1 if not present
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- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing,
|
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if the property is omitted, a functionally reduced I2C bus
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||||
controller on DW HDMI is probed
|
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- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"
|
||||
When referenced from platform device tree bindings the properties defined in
|
||||
this document are defined as follows. The platform device tree bindings are
|
||||
responsible for defining whether each property is required or optional.
|
||||
|
||||
Example:
|
||||
hdmi: hdmi@0120000 {
|
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compatible = "fsl,imx6q-hdmi";
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reg = <0x00120000 0x9000>;
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interrupts = <0 115 0x04>;
|
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gpr = <&gpr>;
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clocks = <&clks 123>, <&clks 124>;
|
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clock-names = "iahb", "isfr";
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ddc-i2c-bus = <&i2c2>;
|
||||
- reg: Memory mapped base address and length of the DWC HDMI TX registers.
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
- reg-io-width: Width of the registers specified by the reg property. The
|
||||
value is expressed in bytes and must be equal to 1 or 4 if specified. The
|
||||
register width defaults to 1 if the property is not present.
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||||
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hdmi_mux_0: endpoint {
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remote-endpoint = <&ipu1_di0_hdmi>;
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||||
};
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||||
};
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- interrupts: Reference to the DWC HDMI TX interrupt.
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||||
port@1 {
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reg = <1>;
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||||
- clocks: References to all the clocks specified in the clock-names property
|
||||
as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt.
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||||
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||||
hdmi_mux_1: endpoint {
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remote-endpoint = <&ipu1_di1_hdmi>;
|
||||
};
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};
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};
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- clock-names: The DWC HDMI TX uses the following clocks.
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||||
- "iahb" is the bus clock for either AHB and APB (mandatory).
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- "isfr" is the internal register configuration clock (mandatory).
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- "cec" is the HDMI CEC controller main clock (optional).
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- ports: The connectivity of the DWC HDMI TX with the rest of the system is
|
||||
expressed in using ports as specified in the device graph bindings defined
|
||||
in Documentation/devicetree/bindings/graph.txt. The numbering of the ports
|
||||
is platform-specific.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,46 @@
|
|||
THS8135 Video DAC
|
||||
-----------------
|
||||
|
||||
This is the binding for Texas Instruments THS8135 Video DAC bridge.
|
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|
||||
Required properties:
|
||||
|
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- compatible: Must be "ti,ths8135"
|
||||
|
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Required nodes:
|
||||
|
||||
This device has two video ports. Their connections are modelled using the OF
|
||||
graph bindings specified in Documentation/devicetree/bindings/graph.txt.
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||||
|
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- Video port 0 for RGB input
|
||||
- Video port 1 for VGA output
|
||||
|
||||
Example
|
||||
-------
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||||
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||||
vga-bridge {
|
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compatible = "ti,ths8135";
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||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
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||||
#address-cells = <1>;
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||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
vga_bridge_in: endpoint {
|
||||
remote-endpoint = <&lcdc_out_vga>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
vga_bridge_out: endpoint {
|
||||
remote-endpoint = <&vga_con_in>;
|
||||
};
|
||||
};
|
||||
};
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||||
};
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|
|
@ -16,7 +16,7 @@ Required properties:
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|||
"clk_ade_core" for the ADE core clock.
|
||||
"clk_codec_jpeg" for the media NOC QoS clock, which use the same clock with
|
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jpeg codec.
|
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"clk_ade_pix" for the ADE pixel clok.
|
||||
"clk_ade_pix" for the ADE pixel clock.
|
||||
- assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
|
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phandle + clock-specifier pairs.
|
||||
- assigned-clock-rates: clock rates, one for each entry in assigned-clocks.
|
||||
|
|
|
|||
|
|
@ -1,29 +1,36 @@
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|||
Device-Tree bindings for HDMI Transmitter
|
||||
Freescale i.MX6 DWC HDMI TX Encoder
|
||||
===================================
|
||||
|
||||
HDMI Transmitter
|
||||
================
|
||||
The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
|
||||
with a companion PHY IP.
|
||||
|
||||
These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
|
||||
Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
|
||||
following device-specific properties.
|
||||
|
||||
The HDMI Transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
|
||||
with accompanying PHY IP.
|
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Required properties:
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||||
- #address-cells : should be <1>
|
||||
- #size-cells : should be <0>
|
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- compatible : should be "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
|
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- gpr : should be <&gpr>.
|
||||
The phandle points to the iomuxc-gpr region containing the HDMI
|
||||
multiplexer control register.
|
||||
- clocks, clock-names : phandles to the HDMI iahb and isrf clocks, as described
|
||||
in Documentation/devicetree/bindings/clock/clock-bindings.txt and
|
||||
Documentation/devicetree/bindings/clock/imx6q-clock.txt.
|
||||
- port@[0-4]: Up to four port nodes with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt,
|
||||
corresponding to the four inputs to the HDMI multiplexer.
|
||||
|
||||
Optional properties:
|
||||
- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
|
||||
- compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
|
||||
- reg: See dw_hdmi.txt.
|
||||
- interrupts: HDMI interrupt number
|
||||
- clocks: See dw_hdmi.txt.
|
||||
- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
|
||||
- ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,
|
||||
numbered 0 to 3, corresponding to the four inputs of the HDMI multiplexer.
|
||||
Each port shall have a single endpoint.
|
||||
- gpr : Shall contain a phandle to the iomuxc-gpr region containing the HDMI
|
||||
multiplexer control register.
|
||||
|
||||
example:
|
||||
Optional properties
|
||||
|
||||
- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
|
||||
or the functionally-reduced I2C master contained in the DWC HDMI. When
|
||||
connected to a system I2C master this property contains a phandle to that
|
||||
I2C master controller.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
gpr: iomuxc-gpr@020e0000 {
|
||||
/* ... */
|
||||
|
|
|
|||
|
|
@ -1,23 +1,19 @@
|
|||
Qualcomm adreno/snapdragon GPU
|
||||
|
||||
Required properties:
|
||||
- compatible: "qcom,adreno-3xx"
|
||||
- compatible: "qcom,adreno-XYZ.W", "qcom,adreno"
|
||||
for example: "qcom,adreno-306.0", "qcom,adreno"
|
||||
Note that you need to list the less specific "qcom,adreno" (since this
|
||||
is what the device is matched on), in addition to the more specific
|
||||
with the chip-id.
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt signal from the gpu.
|
||||
- clocks: device clocks
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: the following clocks are required:
|
||||
* "core_clk"
|
||||
* "iface_clk"
|
||||
* "mem_iface_clk"
|
||||
- qcom,chipid: gpu chip-id. Note this may become optional for future
|
||||
devices if we can reliably read the chipid from hw
|
||||
- qcom,gpu-pwrlevels: list of operating points
|
||||
- compatible: "qcom,gpu-pwrlevels"
|
||||
- for each qcom,gpu-pwrlevel:
|
||||
- qcom,gpu-freq: requested gpu clock speed
|
||||
- NOTE: downstream android driver defines additional parameters to
|
||||
configure memory bandwidth scaling per OPP.
|
||||
* "core"
|
||||
* "iface"
|
||||
* "mem_iface"
|
||||
|
||||
Example:
|
||||
|
||||
|
|
@ -25,28 +21,18 @@ Example:
|
|||
...
|
||||
|
||||
gpu: qcom,kgsl-3d0@4300000 {
|
||||
compatible = "qcom,adreno-3xx";
|
||||
compatible = "qcom,adreno-320.2", "qcom,adreno";
|
||||
reg = <0x04300000 0x20000>;
|
||||
reg-names = "kgsl_3d0_reg_memory";
|
||||
interrupts = <GIC_SPI 80 0>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"iface_clk",
|
||||
"mem_iface_clk";
|
||||
"core",
|
||||
"iface",
|
||||
"mem_iface";
|
||||
clocks =
|
||||
<&mmcc GFX3D_CLK>,
|
||||
<&mmcc GFX3D_AHB_CLK>,
|
||||
<&mmcc MMSS_IMEM_AHB_CLK>;
|
||||
qcom,chipid = <0x03020100>;
|
||||
qcom,gpu-pwrlevels {
|
||||
compatible = "qcom,gpu-pwrlevels";
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
qcom,gpu-freq = <450000000>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
qcom,gpu-freq = <27000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,27 @@
|
|||
Multi-Inno MI0283QT display panel
|
||||
|
||||
Required properties:
|
||||
- compatible: "multi-inno,mi0283qt".
|
||||
|
||||
The node for this driver must be a child node of a SPI controller, hence
|
||||
all mandatory properties described in ../spi/spi-bus.txt must be specified.
|
||||
|
||||
Optional properties:
|
||||
- dc-gpios: D/C pin. The presence/absence of this GPIO determines
|
||||
the panel interface mode (IM[3:0] pins):
|
||||
- present: IM=x110 4-wire 8-bit data serial interface
|
||||
- absent: IM=x101 3-wire 9-bit data serial interface
|
||||
- reset-gpios: Reset pin
|
||||
- power-supply: A regulator node for the supply voltage.
|
||||
- backlight: phandle of the backlight device attached to the panel
|
||||
- rotation: panel rotation in degrees counter clockwise (0,90,180,270)
|
||||
|
||||
Example:
|
||||
mi0283qt@0{
|
||||
compatible = "multi-inno,mi0283qt";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <32000000>;
|
||||
rotation = <90>;
|
||||
dc-gpios = <&gpio 25 0>;
|
||||
backlight = <&backlight>;
|
||||
};
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
BOE OPTOELECTRONICS TECHNOLOGY 10.1" WXGA TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "boe,nv101wxmn51"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
Netron-DY E231732 7.0" WSVGA TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "netron-dy,e231732"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
Common display properties
|
||||
-------------------------
|
||||
|
||||
- rotation: Display rotation in degrees counter clockwise (0,90,180,270)
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "tianma,tm070jdhg30"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
|
|
@ -1,24 +1,39 @@
|
|||
Rockchip specific extensions to the Synopsys Designware HDMI
|
||||
================================
|
||||
Rockchip DWC HDMI TX Encoder
|
||||
============================
|
||||
|
||||
The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
|
||||
with a companion PHY IP.
|
||||
|
||||
These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
|
||||
Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
|
||||
following device-specific properties.
|
||||
|
||||
|
||||
Required properties:
|
||||
- compatible: "rockchip,rk3288-dw-hdmi";
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- clocks: phandle to hdmi iahb and isfr clocks.
|
||||
- clock-names: should be "iahb" "isfr"
|
||||
- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
|
||||
|
||||
- compatible: Shall contain "rockchip,rk3288-dw-hdmi".
|
||||
- reg: See dw_hdmi.txt.
|
||||
- reg-io-width: See dw_hdmi.txt. Shall be 4.
|
||||
- interrupts: HDMI interrupt number
|
||||
- ports: contain a port node with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt. For
|
||||
vopb,set the reg = <0> and set the reg = <1> for vopl.
|
||||
- reg-io-width: the width of the reg:1,4, the value should be 4 on
|
||||
rk3288 platform
|
||||
- clocks: See dw_hdmi.txt.
|
||||
- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
|
||||
- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
|
||||
corresponding to the video input of the controller. The port shall have two
|
||||
endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
|
||||
- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
|
||||
|
||||
Optional properties
|
||||
- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
|
||||
- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"
|
||||
|
||||
- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
|
||||
or the functionally-reduced I2C master contained in the DWC HDMI. When
|
||||
connected to a system I2C master this property contains a phandle to that
|
||||
I2C master controller.
|
||||
- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
|
||||
- clock-names: May contain "cec" as defined in dw_hdmi.txt.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
hdmi: hdmi@ff980000 {
|
||||
compatible = "rockchip,rk3288-dw-hdmi";
|
||||
reg = <0xff980000 0x20000>;
|
||||
|
|
|
|||
|
|
@ -49,6 +49,15 @@ Required properties:
|
|||
"osc_clk"
|
||||
"xclk"
|
||||
|
||||
* TV Encoder output device
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "zte,zx296718-tvenc"
|
||||
- reg: Physical base address and length of the TVENC device IO region
|
||||
- zte,tvenc-power-control: the phandle to SYSCTRL block followed by two
|
||||
integer cells. The first cell is the offset of SYSCTRL register used
|
||||
to control TV Encoder DAC power, and the second cell is the bit mask.
|
||||
|
||||
Example:
|
||||
|
||||
vou: vou@1440000 {
|
||||
|
|
@ -81,4 +90,10 @@ vou: vou@1440000 {
|
|||
<&topcrm HDMI_XCLK>;
|
||||
clock-names = "osc_cec", "osc_clk", "xclk";
|
||||
};
|
||||
|
||||
tvenc: tvenc@2000 {
|
||||
compatible = "zte,zx296718-tvenc";
|
||||
reg = <0x2000 0x1000>;
|
||||
zte,tvenc-power-control = <&sysctrl 0x170 0x10>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -195,6 +195,7 @@ mpl MPL AG
|
|||
mqmaker mqmaker Inc.
|
||||
msi Micro-Star International Co. Ltd.
|
||||
mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.)
|
||||
multi-inno Multi-Inno Technology Co.,Ltd
|
||||
mundoreader Mundo Reader S.L.
|
||||
murata Murata Manufacturing Co., Ltd.
|
||||
mxicy Macronix International Co., Ltd.
|
||||
|
|
@ -204,6 +205,7 @@ nec NEC LCD Technologies, Ltd.
|
|||
neonode Neonode Inc.
|
||||
netgear NETGEAR
|
||||
netlogic Broadcom Corporation (formerly NetLogic Microsystems)
|
||||
netron-dy Netron DY
|
||||
netxeon Shenzhen Netxeon Technology CO., LTD
|
||||
nexbox Nexbox
|
||||
newhaven Newhaven Display International
|
||||
|
|
@ -305,6 +307,7 @@ technologic Technologic Systems
|
|||
terasic Terasic Inc.
|
||||
thine THine Electronics, Inc.
|
||||
ti Texas Instruments
|
||||
tianma Tianma Micro-electronics Co., Ltd.
|
||||
tlm Trusted Logic Mobility
|
||||
topeet Topeet
|
||||
toradex Toradex AG
|
||||
|
|
|
|||
Loading…
Reference in a new issue