diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c index c06c799503de..8e01c1c20224 100644 --- a/drivers/gpu/msm/adreno.c +++ b/drivers/gpu/msm/adreno.c @@ -1646,28 +1646,26 @@ int adreno_clear_pending_transactions(struct kgsl_device *device) if (adreno_has_gbif(adreno_dev)) { - /* This is taken care by GMU firmware if GMU is enabled */ - if (!gmu_core_gpmu_isenabled(device)) { - /* Halt GBIF GX traffic and poll for halt ack */ - if (adreno_is_a615_family(adreno_dev)) { - adreno_writereg(adreno_dev, - ADRENO_REG_RBBM_GPR0_CNTL, - GBIF_HALT_REQUEST); - ret = adreno_wait_for_halt_ack(device, - A6XX_RBBM_VBIF_GX_RESET_STATUS, - VBIF_RESET_ACK_MASK); - } else { - adreno_writereg(adreno_dev, - ADRENO_REG_RBBM_GBIF_HALT, - gpudev->gbif_gx_halt_mask); - ret = adreno_wait_for_halt_ack(device, - ADRENO_REG_RBBM_GBIF_HALT_ACK, - gpudev->gbif_gx_halt_mask); - } - if (ret) - return ret; + /* Halt GBIF GX traffic and poll for halt ack */ + if (adreno_is_a615_family(adreno_dev)) { + adreno_writereg(adreno_dev, + ADRENO_REG_RBBM_GPR0_CNTL, + GBIF_HALT_REQUEST); + ret = adreno_wait_for_halt_ack(device, + A6XX_RBBM_VBIF_GX_RESET_STATUS, + VBIF_RESET_ACK_MASK); + } else { + adreno_writereg(adreno_dev, + ADRENO_REG_RBBM_GBIF_HALT, + gpudev->gbif_gx_halt_mask); + ret = adreno_wait_for_halt_ack(device, + ADRENO_REG_RBBM_GBIF_HALT_ACK, + gpudev->gbif_gx_halt_mask); } + if (ret) + return ret; + /* Halt new client requests */ adreno_writereg(adreno_dev, ADRENO_REG_GBIF_HALT, gpudev->gbif_client_halt_mask); @@ -1734,10 +1732,6 @@ static int adreno_init(struct kgsl_device *device) return ret; } - ret = gmu_core_init(device); - if (ret) - return ret; - /* Put the GPU in a responsive state */ if (ADRENO_GPUREV(adreno_dev) < 600) { /* No need for newer generation architectures */ @@ -2120,20 +2114,7 @@ static int _adreno_start(struct adreno_device *adreno_dev) status = kgsl_mmu_start(device); if (status) - goto error_boot_oob_clear; - - /* Send OOB request to turn on the GX */ - status = gmu_core_dev_oob_set(device, oob_gpu); - if (status) { - gmu_core_snapshot(device); - goto error_oob_clear; - } - - status = gmu_core_dev_hfi_start_msg(device); - if (status) { - gmu_core_snapshot(device); - goto error_oob_clear; - } + goto error_pwr_off; adreno_get_bus_counters(adreno_dev); @@ -2157,7 +2138,7 @@ static int _adreno_start(struct adreno_device *adreno_dev) status = gpudev->rb_start(adreno_dev); if (status) - goto error_oob_clear; + goto error_pwr_off; /* * At this point it is safe to assume that we recovered. Setting @@ -2174,22 +2155,8 @@ static int _adreno_start(struct adreno_device *adreno_dev) set_bit(ADRENO_DEVICE_STARTED, &adreno_dev->priv); - /* Send OOB request to allow IFPC */ - gmu_core_dev_oob_clear(device, oob_gpu); - - /* If we made it this far, the BOOT OOB was sent to the GMU */ - if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_HFI_USE_REG)) - gmu_core_dev_oob_clear(device, oob_boot_slumber); - return 0; -error_oob_clear: - gmu_core_dev_oob_clear(device, oob_gpu); - -error_boot_oob_clear: - if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_HFI_USE_REG)) - gmu_core_dev_oob_clear(device, oob_boot_slumber); - error_pwr_off: /* set the state back to original state */ kgsl_pwrctrl_change_state(device, state); @@ -2231,14 +2198,6 @@ static int adreno_stop(struct kgsl_device *device) if (!test_bit(ADRENO_DEVICE_STARTED, &adreno_dev->priv)) return 0; - error = gmu_core_dev_oob_set(device, oob_gpu); - if (error) { - gmu_core_dev_oob_clear(device, oob_gpu); - gmu_core_snapshot(device); - error = -EINVAL; - goto no_gx_power; - } - kgsl_pwrscale_update_stats(device); adreno_irqctrl(adreno_dev, 0); @@ -2249,24 +2208,8 @@ static int adreno_stop(struct kgsl_device *device) /* Save physical performance counter values before GPU power down*/ adreno_perfcounter_save(adreno_dev); - gmu_core_dev_prepare_stop(device); - gmu_core_dev_oob_clear(device, oob_gpu); - - /* - * Saving perfcounters will use an OOB to put the GMU into - * active state. Before continuing, we should wait for the - * GMU to return to the lowest idle level. This is - * because some idle level transitions require VBIF and MMU. - */ - - if (!error && gmu_core_dev_wait_for_lowest_idle(device)) { - gmu_core_snapshot(device); - error = -EINVAL; - } - adreno_clear_pending_transactions(device); -no_gx_power: adreno_dispatcher_stop(adreno_dev); adreno_ringbuffer_stop(adreno_dev); @@ -2277,16 +2220,6 @@ no_gx_power: if (!IS_ERR_OR_NULL(adreno_dev->gpuhtw_llc_slice)) llcc_slice_deactivate(adreno_dev->gpuhtw_llc_slice); - /* - * The halt is not cleared in the above function if we have GBIF. - * Clear it here if GMU is enabled as GMU stop needs access to - * system memory to stop. For non-GMU targets, we don't need to - * clear it as it will get cleared automatically once headswitch - * goes OFF immediately after adreno_stop. - */ - if (gmu_core_gpmu_isenabled(device)) - adreno_deassert_gbif_halt(adreno_dev); - adreno_set_active_ctxs_null(adreno_dev); clear_bit(ADRENO_DEVICE_STARTED, &adreno_dev->priv); @@ -2887,15 +2820,7 @@ void adreno_spin_idle_debug(struct adreno_device *adreno_dev, dev_err(device->dev, " hwfault=%8.8X\n", hwfault); - /* - * If CP is stuck, gmu may not perform as expected. So force a gmu - * snapshot which captures entire state as well as sets the gmu fault - * because things need to be reset anyway. - */ - if (gmu_core_isenabled(device)) - gmu_core_snapshot(device); - else - kgsl_device_snapshot(device, NULL, false); + kgsl_device_snapshot(device, NULL, false); } /** @@ -3090,47 +3015,6 @@ static void adreno_regwrite(struct kgsl_device *device, __raw_writel(value, reg); } -/** - * adreno_gmu_clear_and_unmask_irqs() - Clear pending IRQs and Unmask IRQs - * @adreno_dev: Pointer to the Adreno device that owns the GMU - */ -void adreno_gmu_clear_and_unmask_irqs(struct adreno_device *adreno_dev) -{ - struct kgsl_device *device = KGSL_DEVICE(adreno_dev); - struct gmu_dev_ops *gmu_dev_ops = GMU_DEVICE_OPS(device); - - /* Clear any pending IRQs before unmasking on GMU */ - adreno_write_gmureg(adreno_dev, ADRENO_REG_GMU_GMU2HOST_INTR_CLR, - 0xFFFFFFFF); - adreno_write_gmureg(adreno_dev, ADRENO_REG_GMU_AO_HOST_INTERRUPT_CLR, - 0xFFFFFFFF); - - /* Unmask needed IRQs on GMU */ - adreno_write_gmureg(adreno_dev, ADRENO_REG_GMU_GMU2HOST_INTR_MASK, - (unsigned int) ~(gmu_dev_ops->gmu2host_intr_mask)); - adreno_write_gmureg(adreno_dev, ADRENO_REG_GMU_AO_HOST_INTERRUPT_MASK, - (unsigned int) ~(gmu_dev_ops->gmu_ao_intr_mask)); -} - -/** - * adreno_gmu_mask_and_clear_irqs() - Mask all IRQs and clear pending IRQs - * @adreno_dev: Pointer to the Adreno device that owns the GMU - */ -void adreno_gmu_mask_and_clear_irqs(struct adreno_device *adreno_dev) -{ - /* Mask all IRQs on GMU */ - adreno_write_gmureg(adreno_dev, ADRENO_REG_GMU_AO_HOST_INTERRUPT_MASK, - 0xFFFFFFFF); - adreno_write_gmureg(adreno_dev, ADRENO_REG_GMU_GMU2HOST_INTR_MASK, - 0xFFFFFFFF); - - /* Clear any pending IRQs before disabling */ - adreno_write_gmureg(adreno_dev, ADRENO_REG_GMU_AO_HOST_INTERRUPT_CLR, - 0xFFFFFFFF); - adreno_write_gmureg(adreno_dev, ADRENO_REG_GMU_GMU2HOST_INTR_CLR, - 0xFFFFFFFF); -} - /* * adreno_gmu_fenced_write() - Check if there is a GMU and it is enabled * @adreno_dev: Pointer to the Adreno device that owns the GMU diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h index 85b4aa908688..602164ef74e9 100644 --- a/drivers/gpu/msm/adreno.h +++ b/drivers/gpu/msm/adreno.h @@ -709,23 +709,9 @@ enum adreno_regs { ADRENO_REG_VBIF_VERSION, ADRENO_REG_GBIF_HALT, ADRENO_REG_GBIF_HALT_ACK, - ADRENO_REG_GMU_AO_INTERRUPT_EN, - ADRENO_REG_GMU_AO_HOST_INTERRUPT_CLR, ADRENO_REG_GMU_AO_HOST_INTERRUPT_MASK, - ADRENO_REG_GMU_PWR_COL_KEEPALIVE, ADRENO_REG_GMU_AHB_FENCE_STATUS, - ADRENO_REG_GMU_RPMH_POWER_STATE, - ADRENO_REG_GMU_HFI_CTRL_STATUS, - ADRENO_REG_GMU_HFI_VERSION_INFO, - ADRENO_REG_GMU_HFI_SFR_ADDR, - ADRENO_REG_GMU_GMU2HOST_INTR_CLR, - ADRENO_REG_GMU_GMU2HOST_INTR_INFO, ADRENO_REG_GMU_GMU2HOST_INTR_MASK, - ADRENO_REG_GMU_HOST2GMU_INTR_SET, - ADRENO_REG_GMU_HOST2GMU_INTR_CLR, - ADRENO_REG_GMU_HOST2GMU_INTR_RAW_INFO, - ADRENO_REG_GMU_NMI_CONTROL_STATUS, - ADRENO_REG_GMU_CM3_CFG, ADRENO_REG_GPMU_POWER_COUNTER_ENABLE, ADRENO_REG_REGISTER_MAX, }; @@ -1762,9 +1748,6 @@ static inline void adreno_reg_offset_init(u32 *reg_offsets) } } - -void adreno_gmu_clear_and_unmask_irqs(struct adreno_device *adreno_dev); -void adreno_gmu_mask_and_clear_irqs(struct adreno_device *adreno_dev); int adreno_gmu_fenced_write(struct adreno_device *adreno_dev, enum adreno_regs offset, unsigned int val, unsigned int fence_mask); diff --git a/drivers/gpu/msm/adreno_a6xx.c b/drivers/gpu/msm/adreno_a6xx.c index 3b7d0300a79f..18a245d5ea62 100644 --- a/drivers/gpu/msm/adreno_a6xx.c +++ b/drivers/gpu/msm/adreno_a6xx.c @@ -2479,40 +2479,12 @@ static unsigned int a6xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { A6XX_RBBM_GBIF_HALT_ACK), ADRENO_REG_DEFINE(ADRENO_REG_GBIF_HALT, A6XX_GBIF_HALT), ADRENO_REG_DEFINE(ADRENO_REG_GBIF_HALT_ACK, A6XX_GBIF_HALT_ACK), - ADRENO_REG_DEFINE(ADRENO_REG_GMU_AO_INTERRUPT_EN, - A6XX_GMU_AO_INTERRUPT_EN), - ADRENO_REG_DEFINE(ADRENO_REG_GMU_AO_HOST_INTERRUPT_CLR, - A6XX_GMU_AO_HOST_INTERRUPT_CLR), ADRENO_REG_DEFINE(ADRENO_REG_GMU_AO_HOST_INTERRUPT_MASK, A6XX_GMU_AO_HOST_INTERRUPT_MASK), - ADRENO_REG_DEFINE(ADRENO_REG_GMU_PWR_COL_KEEPALIVE, - A6XX_GMU_GMU_PWR_COL_KEEPALIVE), ADRENO_REG_DEFINE(ADRENO_REG_GMU_AHB_FENCE_STATUS, A6XX_GMU_AHB_FENCE_STATUS), - ADRENO_REG_DEFINE(ADRENO_REG_GMU_HFI_CTRL_STATUS, - A6XX_GMU_HFI_CTRL_STATUS), - ADRENO_REG_DEFINE(ADRENO_REG_GMU_HFI_VERSION_INFO, - A6XX_GMU_HFI_VERSION_INFO), - ADRENO_REG_DEFINE(ADRENO_REG_GMU_HFI_SFR_ADDR, - A6XX_GMU_HFI_SFR_ADDR), - ADRENO_REG_DEFINE(ADRENO_REG_GMU_RPMH_POWER_STATE, - A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE), - ADRENO_REG_DEFINE(ADRENO_REG_GMU_GMU2HOST_INTR_CLR, - A6XX_GMU_GMU2HOST_INTR_CLR), - ADRENO_REG_DEFINE(ADRENO_REG_GMU_GMU2HOST_INTR_INFO, - A6XX_GMU_GMU2HOST_INTR_INFO), ADRENO_REG_DEFINE(ADRENO_REG_GMU_GMU2HOST_INTR_MASK, A6XX_GMU_GMU2HOST_INTR_MASK), - ADRENO_REG_DEFINE(ADRENO_REG_GMU_HOST2GMU_INTR_SET, - A6XX_GMU_HOST2GMU_INTR_SET), - ADRENO_REG_DEFINE(ADRENO_REG_GMU_HOST2GMU_INTR_CLR, - A6XX_GMU_HOST2GMU_INTR_CLR), - ADRENO_REG_DEFINE(ADRENO_REG_GMU_HOST2GMU_INTR_RAW_INFO, - A6XX_GMU_HOST2GMU_INTR_RAW_INFO), - ADRENO_REG_DEFINE(ADRENO_REG_GMU_NMI_CONTROL_STATUS, - A6XX_GMU_NMI_CONTROL_STATUS), - ADRENO_REG_DEFINE(ADRENO_REG_GMU_CM3_CFG, - A6XX_GMU_CM3_CFG), }; static int cpu_gpu_lock(struct cpu_gpu_lock *lock) diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.c b/drivers/gpu/msm/adreno_a6xx_gmu.c index d0e6b03fa22a..1c75f673af23 100644 --- a/drivers/gpu/msm/adreno_a6xx_gmu.c +++ b/drivers/gpu/msm/adreno_a6xx_gmu.c @@ -779,11 +779,19 @@ static void a6xx_gmu_oob_clear(struct kgsl_device *device, static void a6xx_gmu_irq_enable(struct adreno_device *adreno_dev) { + struct kgsl_device *device = KGSL_DEVICE(adreno_dev); struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev); struct a6xx_hfi *hfi = &gmu->hfi; /* Clear pending IRQs and Unmask needed IRQs */ - adreno_gmu_clear_and_unmask_irqs(adreno_dev); + gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_CLR, 0xffffffff); + gmu_core_regwrite(device, A6XX_GMU_AO_HOST_INTERRUPT_CLR, 0xffffffff); + + gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_MASK, + (unsigned int)~HFI_IRQ_MASK); + gmu_core_regwrite(device, A6XX_GMU_AO_HOST_INTERRUPT_MASK, + (unsigned int)~GMU_AO_INT_MASK); + /* Enable all IRQs on host */ enable_irq(hfi->irq); @@ -792,6 +800,7 @@ static void a6xx_gmu_irq_enable(struct adreno_device *adreno_dev) static void a6xx_gmu_irq_disable(struct adreno_device *adreno_dev) { + struct kgsl_device *device = KGSL_DEVICE(adreno_dev); struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev); struct a6xx_hfi *hfi = &gmu->hfi; @@ -800,7 +809,12 @@ static void a6xx_gmu_irq_disable(struct adreno_device *adreno_dev) disable_irq(hfi->irq); /* Mask all IRQs and clear pending IRQs */ - adreno_gmu_mask_and_clear_irqs(adreno_dev); + gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_MASK, 0xffffffff); + gmu_core_regwrite(device, A6XX_GMU_AO_HOST_INTERRUPT_MASK, 0xffffffff); + + gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_CLR, 0xffffffff); + gmu_core_regwrite(device, A6XX_GMU_AO_HOST_INTERRUPT_CLR, 0xffffffff); + } static int a6xx_gmu_hfi_start_msg(struct adreno_device *adreno_dev) @@ -1864,11 +1878,6 @@ static bool a6xx_gmu_scales_bandwidth(struct kgsl_device *device) return (ADRENO_GPUREV(adreno_dev) >= ADRENO_REV_A640); } -static u64 a6xx_gmu_read_alwayson(struct kgsl_device *device) -{ - return a6xx_read_alwayson(ADRENO_DEVICE(device)); -} - static irqreturn_t a6xx_gmu_irq_handler(int irq, void *data) { struct kgsl_device *device = data; @@ -2239,9 +2248,6 @@ static struct gmu_dev_ops a6xx_gmudev = { .snapshot = a6xx_gmu_device_snapshot, .cooperative_reset = a6xx_gmu_cooperative_reset, .wait_for_active_transition = a6xx_gmu_wait_for_active_transition, - .read_alwayson = a6xx_gmu_read_alwayson, - .gmu2host_intr_mask = HFI_IRQ_MASK, - .gmu_ao_intr_mask = GMU_AO_INT_MASK, .scales_bandwidth = a6xx_gmu_scales_bandwidth, }; diff --git a/drivers/gpu/msm/adreno_a6xx_hfi.c b/drivers/gpu/msm/adreno_a6xx_hfi.c index de5fa2630801..4c18c7004516 100644 --- a/drivers/gpu/msm/adreno_a6xx_hfi.c +++ b/drivers/gpu/msm/adreno_a6xx_hfi.c @@ -160,8 +160,8 @@ static int a6xx_hfi_queue_write(struct adreno_device *adreno_dev, wmb(); /* Send interrupt to GMU to receive the message */ - adreno_write_gmureg(adreno_dev, - ADRENO_REG_GMU_HOST2GMU_INTR_SET, 0x1); + gmu_core_regwrite(KGSL_DEVICE(adreno_dev), A6XX_GMU_HOST2GMU_INTR_SET, + 0x1); return 0; } @@ -274,29 +274,29 @@ static int receive_ack_cmd(struct a6xx_gmu_device *gmu, void *rcvd, #define MSG_HDR_SET_SEQNUM(hdr, num) \ (((hdr) & 0xFFFFF) | ((num) << 20)) -static int poll_adreno_gmu_reg(struct adreno_device *adreno_dev, - enum adreno_regs offset_name, unsigned int expected_val, +static int poll_gmu_reg(struct adreno_device *adreno_dev, + u32 offsetdwords, unsigned int expected_val, unsigned int mask, unsigned int timeout_ms) { unsigned int val; - struct kgsl_device *device = KGSL_DEVICE(adreno_dev); struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev); + struct kgsl_device *device = KGSL_DEVICE(adreno_dev); unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); u64 ao_pre_poll, ao_post_poll; - ao_pre_poll = gmu_core_dev_read_alwayson(device); + ao_pre_poll = a6xx_read_alwayson(adreno_dev); while (time_is_after_jiffies(timeout)) { - adreno_read_gmureg(adreno_dev, offset_name, &val); + gmu_core_regread(device, offsetdwords, &val); if ((val & mask) == expected_val) return 0; usleep_range(10, 100); } - ao_post_poll = gmu_core_dev_read_alwayson(device); + ao_post_poll = a6xx_read_alwayson(adreno_dev); /* Check one last time */ - adreno_read_gmureg(adreno_dev, offset_name, &val); + gmu_core_regread(device, offsetdwords, &val); if ((val & mask) == expected_val) return 0; @@ -325,7 +325,7 @@ static int a6xx_hfi_send_cmd(struct adreno_device *adreno_dev, if (rc) return rc; - rc = poll_adreno_gmu_reg(adreno_dev, ADRENO_REG_GMU_GMU2HOST_INTR_INFO, + rc = poll_gmu_reg(adreno_dev, A6XX_GMU_GMU2HOST_INTR_INFO, HFI_IRQ_MSGQ_MASK, HFI_IRQ_MSGQ_MASK, HFI_RSP_TIMEOUT); if (rc) { @@ -337,7 +337,7 @@ static int a6xx_hfi_send_cmd(struct adreno_device *adreno_dev, } /* Clear the interrupt */ - adreno_write_gmureg(adreno_dev, ADRENO_REG_GMU_GMU2HOST_INTR_CLR, + gmu_core_regwrite(KGSL_DEVICE(adreno_dev), A6XX_GMU_GMU2HOST_INTR_CLR, HFI_IRQ_MSGQ_MASK); rc = a6xx_hfi_process_queue(gmu, HFI_MSG_ID, ret_cmd); @@ -841,14 +841,11 @@ int a6xx_hfi_send_req(struct adreno_device *adreno_dev, unsigned int id, irqreturn_t a6xx_hfi_irq_handler(int irq, void *data) { struct kgsl_device *device = data; - struct adreno_device *adreno_dev = ADRENO_DEVICE(device); - struct a6xx_gmu_device *gmu = to_a6xx_gmu(adreno_dev); + struct a6xx_gmu_device *gmu = to_a6xx_gmu(ADRENO_DEVICE(device)); unsigned int status = 0; - adreno_read_gmureg(adreno_dev, - ADRENO_REG_GMU_GMU2HOST_INTR_INFO, &status); - adreno_write_gmureg(adreno_dev, - ADRENO_REG_GMU_GMU2HOST_INTR_CLR, HFI_IRQ_MASK); + gmu_core_regread(device, A6XX_GMU_GMU2HOST_INTR_INFO, &status); + gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_CLR, HFI_IRQ_MASK); if (status & HFI_IRQ_DBGQ_MASK) a6xx_hfi_process_queue(gmu, HFI_DBG_ID, NULL); diff --git a/drivers/gpu/msm/adreno_a6xx_rgmu.c b/drivers/gpu/msm/adreno_a6xx_rgmu.c index 3d082cca5382..6ba17af3df98 100644 --- a/drivers/gpu/msm/adreno_a6xx_rgmu.c +++ b/drivers/gpu/msm/adreno_a6xx_rgmu.c @@ -218,9 +218,16 @@ static void a6xx_rgmu_bcl_config(struct kgsl_device *device, bool on) static void a6xx_rgmu_irq_enable(struct adreno_device *adreno_dev) { struct a6xx_rgmu_device *rgmu = to_a6xx_rgmu(adreno_dev); + struct kgsl_device *device = KGSL_DEVICE(adreno_dev); /* Clear pending IRQs and Unmask needed IRQs */ - adreno_gmu_clear_and_unmask_irqs(adreno_dev); + gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_CLR, 0xffffffff); + gmu_core_regwrite(device, A6XX_GMU_AO_HOST_INTERRUPT_CLR, 0xffffffff); + + gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_MASK, + ~((unsigned int)RGMU_OOB_IRQ_MASK)); + gmu_core_regwrite(device, A6XX_GMU_AO_HOST_INTERRUPT_MASK, + (unsigned int)~RGMU_AO_IRQ_MASK); /* Enable all IRQs on host */ enable_irq(rgmu->oob_interrupt_num); @@ -230,13 +237,18 @@ static void a6xx_rgmu_irq_enable(struct adreno_device *adreno_dev) static void a6xx_rgmu_irq_disable(struct adreno_device *adreno_dev) { struct a6xx_rgmu_device *rgmu = to_a6xx_rgmu(adreno_dev); + struct kgsl_device *device = KGSL_DEVICE(adreno_dev); /* Disable all IRQs on host */ disable_irq(rgmu->rgmu_interrupt_num); disable_irq(rgmu->oob_interrupt_num); /* Mask all IRQs and clear pending IRQs */ - adreno_gmu_mask_and_clear_irqs(adreno_dev); + gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_MASK, 0xffffffff); + gmu_core_regwrite(device, A6XX_GMU_AO_HOST_INTERRUPT_MASK, 0xffffffff); + + gmu_core_regwrite(device, A6XX_GMU_GMU2HOST_INTR_CLR, 0xffffffff); + gmu_core_regwrite(device, A6XX_GMU_AO_HOST_INTERRUPT_CLR, 0xffffffff); } static int a6xx_rgmu_ifpc_store(struct kgsl_device *device, @@ -1163,8 +1175,6 @@ static struct gmu_dev_ops a6xx_rgmudev = { .ifpc_store = a6xx_rgmu_ifpc_store, .ifpc_show = a6xx_rgmu_ifpc_show, .snapshot = a6xx_rgmu_device_snapshot, - .gmu2host_intr_mask = RGMU_OOB_IRQ_MASK, - .gmu_ao_intr_mask = RGMU_AO_IRQ_MASK, }; static struct gmu_core_ops a6xx_rgmu_ops = { diff --git a/drivers/gpu/msm/kgsl_device.h b/drivers/gpu/msm/kgsl_device.h index c401aa047cbb..256255dae52d 100644 --- a/drivers/gpu/msm/kgsl_device.h +++ b/drivers/gpu/msm/kgsl_device.h @@ -35,7 +35,6 @@ #define KGSL_STATE_SUSPEND 0x00000010 #define KGSL_STATE_AWARE 0x00000020 #define KGSL_STATE_SLUMBER 0x00000080 -#define KGSL_STATE_RESET 0x00000100 /** * enum kgsl_event_results - result codes passed to an event callback when the diff --git a/drivers/gpu/msm/kgsl_gmu_core.c b/drivers/gpu/msm/kgsl_gmu_core.c index 17336ba630a6..62b9a311f8a3 100644 --- a/drivers/gpu/msm/kgsl_gmu_core.c +++ b/drivers/gpu/msm/kgsl_gmu_core.c @@ -64,44 +64,6 @@ bool gmu_core_scales_bandwidth(struct kgsl_device *device) return false; } -int gmu_core_init(struct kgsl_device *device) -{ - struct gmu_core_ops *gmu_core_ops = GMU_CORE_OPS(device); - - if (gmu_core_ops && gmu_core_ops->init) - return gmu_core_ops->init(device); - - return 0; -} - -int gmu_core_start(struct kgsl_device *device) -{ - struct gmu_core_ops *gmu_core_ops = GMU_CORE_OPS(device); - - if (gmu_core_ops && gmu_core_ops->start) - return gmu_core_ops->start(device); - - return -EINVAL; -} - -void gmu_core_stop(struct kgsl_device *device) -{ - struct gmu_core_ops *gmu_core_ops = GMU_CORE_OPS(device); - - if (gmu_core_ops && gmu_core_ops->stop) - gmu_core_ops->stop(device); -} - -int gmu_core_suspend(struct kgsl_device *device) -{ - struct gmu_core_ops *gmu_core_ops = GMU_CORE_OPS(device); - - if (gmu_core_ops && gmu_core_ops->suspend) - return gmu_core_ops->suspend(device); - - return -EINVAL; -} - void gmu_core_snapshot(struct kgsl_device *device) { struct gmu_core_ops *gmu_core_ops = GMU_CORE_OPS(device); @@ -220,26 +182,6 @@ void gmu_core_dev_oob_clear(struct kgsl_device *device, enum oob_request req) ops->oob_clear(device, req); } -int gmu_core_dev_hfi_start_msg(struct kgsl_device *device) -{ - struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device); - - if (ops && ops->hfi_start_msg) - return ops->hfi_start_msg(device); - - return 0; -} - -int gmu_core_dev_wait_for_lowest_idle(struct kgsl_device *device) -{ - struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device); - - if (ops && ops->wait_for_lowest_idle) - return ops->wait_for_lowest_idle(device); - - return 0; -} - void gmu_core_dev_snapshot(struct kgsl_device *device, struct kgsl_snapshot *snapshot) { @@ -288,14 +230,6 @@ int gmu_core_dev_ifpc_store(struct kgsl_device *device, unsigned int val) return -EINVAL; } -void gmu_core_dev_prepare_stop(struct kgsl_device *device) -{ - struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device); - - if (ops && ops->prepare_stop) - ops->prepare_stop(device); -} - int gmu_core_dev_wait_for_active_transition(struct kgsl_device *device) { struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device); @@ -305,13 +239,3 @@ int gmu_core_dev_wait_for_active_transition(struct kgsl_device *device) return 0; } - -u64 gmu_core_dev_read_alwayson(struct kgsl_device *device) -{ - struct gmu_dev_ops *ops = GMU_DEVICE_OPS(device); - - if (ops && ops->read_alwayson) - return ops->read_alwayson(device); - - return 0; -} diff --git a/drivers/gpu/msm/kgsl_gmu_core.h b/drivers/gpu/msm/kgsl_gmu_core.h index 092d8e7d1e13..943b7a59909d 100644 --- a/drivers/gpu/msm/kgsl_gmu_core.h +++ b/drivers/gpu/msm/kgsl_gmu_core.h @@ -101,28 +101,14 @@ struct kgsl_device; struct kgsl_snapshot; struct gmu_core_ops { - int (*init)(struct kgsl_device *device); - int (*start)(struct kgsl_device *device); - void (*stop)(struct kgsl_device *device); void (*snapshot)(struct kgsl_device *device); - int (*suspend)(struct kgsl_device *device); int (*acd_set)(struct kgsl_device *device, bool val); }; struct gmu_dev_ops { - int (*load_firmware)(struct kgsl_device *device); int (*oob_set)(struct kgsl_device *device, enum oob_request req); void (*oob_clear)(struct kgsl_device *device, enum oob_request req); - void (*bcl_config)(struct kgsl_device *device, bool on); - void (*irq_enable)(struct kgsl_device *device); - void (*irq_disable)(struct kgsl_device *device); - int (*hfi_start_msg)(struct kgsl_device *device); - int (*rpmh_gpu_pwrctrl)(struct kgsl_device *device, unsigned int ops, - unsigned int arg1, unsigned int arg2); - int (*wait_for_lowest_idle)(struct kgsl_device *device); - int (*wait_for_gmu_idle)(struct kgsl_device *device); bool (*gx_is_on)(struct kgsl_device *device); - void (*prepare_stop)(struct kgsl_device *device); int (*ifpc_store)(struct kgsl_device *device, unsigned int val); unsigned int (*ifpc_show)(struct kgsl_device *device); void (*snapshot)(struct kgsl_device *device, @@ -131,9 +117,6 @@ struct gmu_dev_ops { void (*halt_execution)(struct kgsl_device *device); int (*wait_for_active_transition)(struct kgsl_device *device); bool (*scales_bandwidth)(struct kgsl_device *device); - u64 (*read_alwayson)(struct kgsl_device *device); - const unsigned int gmu2host_intr_mask; - const unsigned int gmu_ao_intr_mask; }; /** @@ -166,10 +149,6 @@ extern struct platform_driver a6xx_rgmu_driver; void __init gmu_core_register(void); void __exit gmu_core_unregister(void); -int gmu_core_init(struct kgsl_device *device); -int gmu_core_start(struct kgsl_device *device); -void gmu_core_stop(struct kgsl_device *device); -int gmu_core_suspend(struct kgsl_device *device); void gmu_core_snapshot(struct kgsl_device *device); bool gmu_core_gpmu_isenabled(struct kgsl_device *device); bool gmu_core_scales_bandwidth(struct kgsl_device *device); @@ -200,16 +179,12 @@ void gmu_core_regrmw(struct kgsl_device *device, unsigned int offsetwords, unsigned int mask, unsigned int bits); int gmu_core_dev_oob_set(struct kgsl_device *device, enum oob_request req); void gmu_core_dev_oob_clear(struct kgsl_device *device, enum oob_request req); -int gmu_core_dev_hfi_start_msg(struct kgsl_device *device); -int gmu_core_dev_wait_for_lowest_idle(struct kgsl_device *device); void gmu_core_dev_snapshot(struct kgsl_device *device, struct kgsl_snapshot *snapshot); bool gmu_core_dev_gx_is_on(struct kgsl_device *device); int gmu_core_dev_ifpc_show(struct kgsl_device *device); int gmu_core_dev_ifpc_store(struct kgsl_device *device, unsigned int val); -void gmu_core_dev_prepare_stop(struct kgsl_device *device); int gmu_core_dev_wait_for_active_transition(struct kgsl_device *device); void gmu_core_dev_cooperative_reset(struct kgsl_device *device); -u64 gmu_core_dev_read_alwayson(struct kgsl_device *device); #endif /* __KGSL_GMU_CORE_H */ diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c index fd03cecdabe4..2a7dec418778 100644 --- a/drivers/gpu/msm/kgsl_pwrctrl.c +++ b/drivers/gpu/msm/kgsl_pwrctrl.c @@ -174,10 +174,6 @@ void kgsl_pwrctrl_pwrlevel_change(struct kgsl_device *device, new_level = kgsl_pwrctrl_adjust_pwrlevel(device, new_level); - if (new_level == old_level && - !test_bit(GMU_DCVS_REPLAY, &device->gmu_core.flags)) - return; - kgsl_pwrscale_update_stats(device); /* @@ -1657,14 +1653,6 @@ static int kgsl_pwrctrl_enable(struct kgsl_device *device) kgsl_pwrctrl_pwrlevel_change(device, level); - if (gmu_core_gpmu_isenabled(device)) { - int ret = gmu_core_start(device); - - if (!ret) - kgsl_pwrctrl_axi(device, KGSL_PWRFLAGS_ON); - return ret; - } - /* Order pwrrail/clk sequence based upon platform */ status = kgsl_pwrctrl_pwrrail(device, KGSL_PWRFLAGS_ON); if (status) @@ -1685,11 +1673,6 @@ static void kgsl_pwrctrl_disable(struct kgsl_device *device) dev_err(device->dev, "Could not clear l3_vote: %d\n", status); - if (gmu_core_gpmu_isenabled(device)) { - kgsl_pwrctrl_axi(device, KGSL_PWRFLAGS_OFF); - return gmu_core_stop(device); - } - /* Order pwrrail/clk sequence based upon platform */ device->ftbl->regulator_disable(device); kgsl_pwrctrl_axi(device, KGSL_PWRFLAGS_OFF); @@ -1722,18 +1705,6 @@ static int _init(struct kgsl_device *device) int status = 0; switch (device->state) { - case KGSL_STATE_RESET: - if (gmu_core_isenabled(device)) { - /* - * If we fail a INIT -> AWARE transition, we will - * transition back to INIT. However, we must hard reset - * the GMU as we go back to INIT. This is done by - * forcing a RESET -> INIT transition. - */ - gmu_core_suspend(device); - kgsl_pwrctrl_set_state(device, KGSL_STATE_INIT); - } - break; case KGSL_STATE_NAP: /* Force power on to do the stop */ status = kgsl_pwrctrl_enable(device); @@ -1843,12 +1814,6 @@ _aware(struct kgsl_device *device) int status = 0; switch (device->state) { - case KGSL_STATE_RESET: - if (!gmu_core_gpmu_isenabled(device)) - break; - kgsl_pwrctrl_irq(device, KGSL_PWRFLAGS_OFF); - status = gmu_core_start(device); - break; case KGSL_STATE_INIT: status = kgsl_pwrctrl_enable(device); break; @@ -1868,18 +1833,7 @@ _aware(struct kgsl_device *device) status = -EINVAL; } - if (status && gmu_core_isenabled(device)) - /* - * If a SLUMBER/INIT -> AWARE fails, we transition back to - * SLUMBER/INIT state. We must hard reset the GMU while - * transitioning back to SLUMBER/INIT. A RESET -> AWARE - * transition is different. It happens when dispatcher is - * attempting reset/recovery as part of fault handling. If it - * fails, we should still transition back to RESET in case - * we want to attempt another reset/recovery. - */ - kgsl_pwrctrl_set_state(device, KGSL_STATE_RESET); - else + if (!status) kgsl_pwrctrl_set_state(device, KGSL_STATE_AWARE); return status; @@ -1911,8 +1865,6 @@ _nap(struct kgsl_device *device) kgsl_pwrctrl_set_state(device, KGSL_STATE_NAP); /* fallthrough */ case KGSL_STATE_SLUMBER: - case KGSL_STATE_RESET: - break; case KGSL_STATE_AWARE: dev_warn(device->dev, "transition AWARE -> NAP is not permitted\n"); @@ -1958,13 +1910,6 @@ _slumber(struct kgsl_device *device) kgsl_pwrctrl_disable(device); kgsl_pwrctrl_set_state(device, KGSL_STATE_SLUMBER); break; - case KGSL_STATE_RESET: - if (gmu_core_isenabled(device)) { - /* Reset the GMU if we failed to boot the GMU */ - gmu_core_suspend(device); - kgsl_pwrctrl_set_state(device, KGSL_STATE_SLUMBER); - } - break; default: kgsl_pwrctrl_request_state(device, KGSL_STATE_NONE); break; @@ -2053,9 +1998,6 @@ int kgsl_pwrctrl_change_state(struct kgsl_device *device, int state) case KGSL_STATE_SUSPEND: status = _suspend(device); break; - case KGSL_STATE_RESET: - kgsl_pwrctrl_set_state(device, KGSL_STATE_RESET); - break; default: dev_err(device->dev, "bad state request 0x%x\n", state); kgsl_pwrctrl_request_state(device, KGSL_STATE_NONE); @@ -2106,8 +2048,6 @@ const char *kgsl_pwrstate_to_str(unsigned int state) return "SUSPEND"; case KGSL_STATE_SLUMBER: return "SLUMBER"; - case KGSL_STATE_RESET: - return "RESET"; default: break; }