From c2fb8297f7de33ff2a91317b1b2e0b6767c1fda6 Mon Sep 17 00:00:00 2001 From: Himateja Reddy Date: Wed, 18 Mar 2020 18:21:07 -0700 Subject: [PATCH] ARM: dts: msm: use 'dma-coherent-hint-cached' for fastrpc nodes Use 'dma-coherent-hint-cached' instead of 'dma-coherent' for the fastrpc iommu context banks. Now, on a QGKI kernel, cached ION buffers will be DMA mapped as IOMMU cached for the fastrpc devices, all other buffers will be DMA mapped as IOMMU uncached and dma_alloc_attrs will always return memory with a cached CPU mapping as well as DMA mapping its memory as IOMMU cached. On a GKI kernel, all buffers for fastrpc devices will be DMA mapped as IOMMU uncached and dma_alloc_attrs will always return CPU uncached memory. Change-Id: I4c5b3e082dc057cb76bfd039b19c6211c729597f Acked-by: Thyagarajan Venkatanarayanan --- qcom/lahaina.dtsi | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 73da2475e3f1..0ca1751b1b38 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -1885,7 +1885,7 @@ <&apps_smmu 0x1181 0x0420>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; - dma-coherent; + dma-coherent-hint-cached; }; qcom,msm_fastrpc_compute_cb2 { @@ -1895,7 +1895,7 @@ <&apps_smmu 0x1182 0x0420>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; - dma-coherent; + dma-coherent-hint-cached; }; qcom,msm_fastrpc_compute_cb3 { @@ -1905,7 +1905,7 @@ <&apps_smmu 0x1183 0x0420>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; - dma-coherent; + dma-coherent-hint-cached; }; qcom,msm_fastrpc_compute_cb4 { @@ -1915,7 +1915,7 @@ <&apps_smmu 0x1184 0x0420>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; - dma-coherent; + dma-coherent-hint-cached; }; qcom,msm_fastrpc_compute_cb5 { @@ -1925,7 +1925,7 @@ <&apps_smmu 0x1185 0x0420>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; - dma-coherent; + dma-coherent-hint-cached; }; qcom,msm_fastrpc_compute_cb6 { @@ -1935,7 +1935,7 @@ <&apps_smmu 0x1186 0x0420>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; - dma-coherent; + dma-coherent-hint-cached; }; qcom,msm_fastrpc_compute_cb7 { @@ -1945,7 +1945,7 @@ <&apps_smmu 0x1187 0x0420>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; - dma-coherent; + dma-coherent-hint-cached; }; qcom,msm_fastrpc_compute_cb8 { @@ -1955,7 +1955,7 @@ <&apps_smmu 0x1188 0x0420>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; - dma-coherent; + dma-coherent-hint-cached; }; qcom,msm_fastrpc_compute_cb9 { @@ -1967,7 +1967,7 @@ qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>; qcom,iommu-faults = "stall-disable"; qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */ - dma-coherent; + dma-coherent-hint-cached; }; qcom,msm_fastrpc_compute_cb10 { @@ -1976,7 +1976,7 @@ iommus = <&apps_smmu 0x1803 0x0>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; - dma-coherent; + dma-coherent-hint-cached; }; qcom,msm_fastrpc_compute_cb11 { @@ -1985,7 +1985,7 @@ iommus = <&apps_smmu 0x1804 0x0>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; - dma-coherent; + dma-coherent-hint-cached; }; qcom,msm_fastrpc_compute_cb12 { @@ -1994,7 +1994,7 @@ iommus = <&apps_smmu 0x1805 0x0>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; - dma-coherent; + dma-coherent-hint-cached; }; qcom,msm_fastrpc_compute_cb13 { @@ -2003,7 +2003,7 @@ iommus = <&apps_smmu 0x0541 0x0>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; - dma-coherent; + dma-coherent-hint-cached; }; qcom,msm_fastrpc_compute_cb14 { @@ -2012,7 +2012,7 @@ iommus = <&apps_smmu 0x0542 0x0>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; - dma-coherent; + dma-coherent-hint-cached; }; qcom,msm_fastrpc_compute_cb15 { @@ -2022,7 +2022,7 @@ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; shared-cb = <4>; - dma-coherent; + dma-coherent-hint-cached; }; qcom,msm_fastrpc_compute_cb16 { @@ -2032,7 +2032,7 @@ <&apps_smmu 0x216B 0x0400>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; - dma-coherent; + dma-coherent-hint-cached; }; qcom,msm_fastrpc_compute_cb17 { @@ -2042,7 +2042,7 @@ <&apps_smmu 0x216C 0x0400>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; - dma-coherent; + dma-coherent-hint-cached; }; qcom,msm_fastrpc_compute_cb18 { @@ -2052,7 +2052,7 @@ <&apps_smmu 0x216D 0x0400>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; - dma-coherent; + dma-coherent-hint-cached; }; qcom,msm_fastrpc_compute_cb19 { @@ -2062,7 +2062,7 @@ <&apps_smmu 0x216E 0x0400>; qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; qcom,iommu-faults = "stall-disable"; - dma-coherent; + dma-coherent-hint-cached; }; };