From f070135ed54bcb805b0881c534e6b6a83e8ab96d Mon Sep 17 00:00:00 2001
From: wuwl10 <wuwl10@motorola.com>
Date: Thu, 3 Jun 2021 16:06:34 +0800
Subject: [PATCH] arm64/dt: cypfg: add nfc device node

Cypfg use ST21J nfc controller.
Add dts node to enable it.

Change-Id: I31a17bb1e98b827735b8561d5748a6e2f00ed75d
Signed-off-by: wuwl10 <wuwl10@motorola.com>
Reviewed-on: https://gerrit.mot.com/1968818
SME-Granted: SME Approvals Granted
SLTApproved: Slta Waiver
Tested-by: Jira Key
Reviewed-by: Huosheng Liao <liaohs@motorola.com>
Submit-Approved: Jira Key
---
 qcom/holi-cypfg-common-overlay.dtsi | 132 +++++++++++++++++++++++-----
 1 file changed, 110 insertions(+), 22 deletions(-)

diff --git a/qcom/holi-cypfg-common-overlay.dtsi b/qcom/holi-cypfg-common-overlay.dtsi
index 8e172ec518ee..eaff94c8d276 100644
--- a/qcom/holi-cypfg-common-overlay.dtsi
+++ b/qcom/holi-cypfg-common-overlay.dtsi
@@ -51,31 +51,96 @@
 		};
 	};
 
-	nfc_clk_active: nfc_clk_active {
-		/* active state */
-		mux {
-			pins = "gpio7", "gpio9";
-			function = "gpio";
+	nfc {
+		nfc_int_active: nfc_int_active {
+			/* active state */
+			mux {
+				/* GPIO 9: NFC Read Interrupt */
+				pins = "gpio9";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio9";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
 		};
 
-		config {
-			pins = "gpio7", "gpio9";
-			drive-strength = <2>; /* 2 MA */
-			output-low;
-		};
-	};
+		nfc_int_suspend: nfc_int_suspend {
+			/* sleep state */
+			mux {
+				/* GPIO 9: NFC Read Interrupt */
+				pins = "gpio9";
+				function = "gpio";
+			};
 
-	nfc_clk_suspend: nfc_clk_suspend {
-		/* sleep state */
-		mux {
-			pins = "gpio7", "gpio9";
-			function = "gpio";
+			config {
+				pins = "gpio9";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
 		};
 
-		config {
-			pins = "gpio7", "gpio9";
-			drive-strength = <2>; /* 2 MA */
-			output-low;
+		nfc_enable_active: nfc_enable_active {
+			mux {
+				/* 48: Enable, 8: Firmware*/
+				pins = "gpio48";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio48";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
+		};
+
+		nfc_enable_suspend: nfc_enable_suspend {
+			mux {
+				/* 48: Enable, 8: Firmware */
+				pins = "gpio48";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio48";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
+		};
+
+
+		nfc_clk_req_active: nfc_clk_req_active {
+			/* active state */
+			mux {
+				/* GPIO 7: NFC CLK Req*/
+				pins = "gpio7";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio7";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+				input-enable;
+			};
+		};
+
+		nfc_clk_req_suspend: nfc_clk_req_suspend {
+			/* sleep state */
+			mux {
+				/* GPIO 7: NFC CLK Req */
+				pins = "gpi7";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio7";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+				input-enable;
+			};
 		};
 	};
 };
@@ -94,6 +159,29 @@
 	};
 };
 
+&qupv3_se7_i2c {
+	status = "ok";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	st21nfc@8 {
+		compatible = "st,st21nfc";
+		mmi,status = "/chosen", "mmi,nfc", "st";
+		status = "ok";
+		reg = <0x08>;
+		st,irq_gpio = <&tlmm 9 0x00>;
+		st,reset_gpio = <&tlmm 48 0x00>;
+		st,clkreq_gpio = <&tlmm 7 0x00>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <9 0>;
+		interrupt-names = "nfc_irq";
+		pinctrl-names = "nfc_active", "nfc_suspend";
+		pinctrl-0 = <&nfc_int_active &nfc_enable_active
+				&nfc_clk_req_active>;
+		pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+				&nfc_clk_req_suspend>;
+	};
+};
+
 &qupv3_se10_i2c {
 	status = "ok";
 
@@ -326,8 +414,8 @@
 
 &sx937x {
 		pinctrl-names = "default","sleep";
-		pinctrl-0 = <&sar_int_default &nfc_clk_active>;
-		pinctrl-1 = <&sar_int_sleep &nfc_clk_suspend>;
+		pinctrl-0 = <&sar_int_default>;
+		pinctrl-1 = <&sar_int_sleep>;
 		/*use PH4/5/6 as the reference sensor
 		set it to 0xff if the ref-phases-x is not used*/
 		Semtech,ref-phases-a = <5>;