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fw-api: CL 26775343 - update fw common interface files

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Change-Id: Ia0a2abcd47fe682f7a8a47fec5293ac04cfae080
CRs-Fixed: 2262693
This commit is contained in:
Pragaspathi Thilagaraj 2024-05-29 02:57:34 -07:00 • committed by Ravindra Konda
commit f08b885f7e
1 changed files with 147 additions and 30 deletions
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177
fw/htt.h
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@ -5790,38 +5790,39 @@ enum htt_srng_ring_id {
*
* The message would appear as follows:
*
* |31 28|27|26|25|24|23|22|21 19|18 16|15 | 11| 10|9 8|7 0|
* |-----+--+--+--+--+-----------------+----+---+---+---+---------------|
* |rsvd1|DT|OV|PS|SS| ring_id | pdev_id | msg_type |
* |-----------------------+-----+-----+--------------------------------|
* |rsvd2|RX|RXHDL| CLD | CLC | CLM | ring_buffer_size |
* |--------------------------------------------------------------------|
* | packet_type_enable_flags_0 |
* |--------------------------------------------------------------------|
* | packet_type_enable_flags_1 |
* |--------------------------------------------------------------------|
* | packet_type_enable_flags_2 |
* |--------------------------------------------------------------------|
* | packet_type_enable_flags_3 |
* |--------------------------------------------------------------------|
* | tlv_filter_in_flags |
* |-----------------------------------+--------------------------------|
* | rx_header_offset | rx_packet_offset |
* |-----------------------------------+--------------------------------|
* | rx_mpdu_start_offset | rx_mpdu_end_offset |
* |-----------------------------------+--------------------------------|
* | rx_msdu_start_offset | rx_msdu_end_offset |
* |-----------------------------------+--------------------------------|
* | rsvd3 | rx_attention_offset |
* |--------------------------------------------------------------------|
* | rsvd4 | mo| fp| rx_drop_threshold |
* | |ndp|ndp| |
* |--------------------------------------------------------------------|
* |31 29|28|27|26|25|24|23|22|21 19|18 16|15 | 11| 10|9 8|7 0|
* |-----+--+--+--+--+--+-----------------+----+---+---+---+---------------|
* |rsvd1|ED|DT|OV|PS|SS| ring_id | pdev_id | msg_type |
* |--------------------------+-----+-----+--------------------------------|
* | rsvd2 |RX|RXHDL| CLD | CLC | CLM | ring_buffer_size |
* |-----------------------------------------------------------------------|
* | packet_type_enable_flags_0 |
* |-----------------------------------------------------------------------|
* | packet_type_enable_flags_1 |
* |-----------------------------------------------------------------------|
* | packet_type_enable_flags_2 |
* |-----------------------------------------------------------------------|
* | packet_type_enable_flags_3 |
* |-----------------------------------------------------------------------|
* | tlv_filter_in_flags |
* |--------------------------------------+--------------------------------|
* | rx_header_offset | rx_packet_offset |
* |--------------------------------------+--------------------------------|
* | rx_mpdu_start_offset | rx_mpdu_end_offset |
* |--------------------------------------+--------------------------------|
* | rx_msdu_start_offset | rx_msdu_end_offset |
* |--------------------------------------+--------------------------------|
* | rsvd3 | rx_attention_offset |
* |-----------------------------------------------------------------------|
* | rsvd4 | mo| fp| rx_drop_threshold |
* | |ndp|ndp| |
* |-----------------------------------------------------------------------|
* Where:
* PS = pkt_swap
* SS = status_swap
* OV = rx_offsets_valid
* DT = drop_thresh_valid
* ED = packet type enable data flags fields present / valid
* CLM = config_length_mgmt
* CLC = config_length_ctrl
* CLD = config_length_data
@ -5846,8 +5847,12 @@ enum htt_srng_ring_id {
* b'27 - drop_thresh_valid (DT): flag to indicate if the
* rx_drop_threshold field is valid
* b'28 - rx_mon_global_en: Enable/Disable global register
8 configuration in Rx monitor module.
* b'29:31 - rsvd1: reserved for future use
* configuration in Rx monitor module.
* b'29 - packet_type_enable_data: flag to indicate whether
* newer packet_type_enable_data_flags_* are valid or not
* If not set, will use pkt_type_enable_flags for both status
* and full pkt buffer configuration.
* b'30:31 - rsvd1: reserved for future use
* dword1 - b'0:15 - ring_buffer_size: size of bufferes referenced by rx ring,
* in byte units.
* Valid only for HW_TO_SW_RING and SW_TO_HW_RING
@ -6011,6 +6016,32 @@ enum htt_srng_ring_id {
* 1: RX_PKT TLV logging at specified offset for the
* subsequent buffer
* b`15:1 - rx_pkt_tlv_offset: Qword offset for rx_packet TLVs.
* dword18- b'0:19 - rx_mpdu_start_wmask_v2 - wmask address for rx mpdu start
* b'20-27 - rx_mpdu_end_wmask_v2 - wmask addr for rx mpdu end tlv addr
* b'28-31 - reserved
* dword19- b'0-19 - rx_msdu_end_wmask_v2
* b'20-31 - reserved
* dword20- b'0:19 - rx_ppdu_end_user_stats_wmask_v2
* offset for ppdu_end_user_stats tlv
* b'20-31 - reserved
* dword21- b'0-31 - packet_type_enable_fpmo_flags_0 - filter bmap for each
* mode mgmt/ctrl type/subtype for fpmo mode
* dword22- b'0-31 - packet_type_enable_fpmo_flags_1 - filter bmap for each
* mode ctrl/data type/subtype for fpmo mode
* dword23- b'0-31 - packet_type_enable_data_flags_0 - filter bmap for full
* pkt buffer each mode MGMT type/subtype
* dword24- b'0-31 - packet_type_enable_data_flags_0 - filter bmap for full
* pkt buffer each mode MGMT type/subtype
* dword25- b'0-31 - packet_type_enable_data_flags_0 - filter bmap for full
* pkt buffer each mode CTRL type/subtype
* dword26- b'0-31 - packet_type_enable_data_flags_0 - filter bmap for full
* pkt buffer each mode CTRL/DATA type/subtype
* dword27- b'0-31 - packet_type_enable_data_fpmo_flags_0 - filter bmap for
* full pkt buffer each mode mgmt/ctrl type/subtype for
* fpmo mode
* dword28- b'0-31 - packet_type_enable_data_fpmo_flags_1 - filter bmap for
* full pkt buffer each mode ctrl/data type/subtype for
* fpmo mode
*/
PREPACK struct htt_rx_ring_selection_cfg_t {
A_UINT32 msg_type: 8,
@ -6021,7 +6052,8 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
rx_offsets_valid: 1,
drop_thresh_valid: 1,
rx_mon_global_en: 1,
rsvd1: 3;
packet_type_enable_data: 1,
rsvd1: 2;
A_UINT32 ring_buffer_size: 16,
config_length_mgmt:3,
config_length_ctrl:3,
@ -6075,6 +6107,12 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
rsvd10: 12;
A_UINT32 packet_type_enable_fpmo_flags0;
A_UINT32 packet_type_enable_fpmo_flags1;
A_UINT32 packet_type_enable_data_flags_0;
A_UINT32 packet_type_enable_data_flags_1;
A_UINT32 packet_type_enable_data_flags_2;
A_UINT32 packet_type_enable_data_flags_3;
A_UINT32 packet_type_enable_data_fpmo_flags0;
A_UINT32 packet_type_enable_data_fpmo_flags1;
} POSTPACK;
#define HTT_RX_RING_SELECTION_CFG_SZ (sizeof(struct htt_rx_ring_selection_cfg_t))
@ -6156,6 +6194,17 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MON_GLOBAL_EN_S)); \
} while (0)
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_M 0x20000000
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_S 29
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_GET(_var) \
(((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_M) >> \
HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_S)
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA, _val); \
((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_S)); \
} while (0)
#define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_M 0x0000ffff
#define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S 0
#define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_GET(_var) \
@ -6644,6 +6693,74 @@ PREPACK struct htt_rx_ring_selection_cfg_t {
((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_FPMO_FLAGS1_S)); \
} while (0)
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0_M 0xffffffff
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0_S 0
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0_GET(_var) \
(((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0_M) >> \
HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0_S)
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0, _val); \
((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_0_S)); \
} while (0)
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1_M 0xffffffff
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1_S 0
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1_GET(_var) \
(((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1_M) >> \
HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1_S)
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1, _val); \
((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_1_S)); \
} while (0)
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2_M 0xffffffff
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2_S 0
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2_GET(_var) \
(((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2_M) >> \
HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2_S)
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2, _val); \
((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_2_S)); \
} while (0)
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3_M 0xffffffff
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3_S 0
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3_GET(_var) \
(((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3_M) >> \
HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3_S)
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3, _val); \
((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FLAG_3_S)); \
} while (0)
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0_M 0xFFFFFFFF
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0_S 0
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0_GET(_var) \
(((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0_M)>> \
HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0_S)
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0, _val); \
((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS0_S)); \
} while (0)
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1_M 0xFFFFFFFF
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1_S 0
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1_GET(_var) \
(((_var) & HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1_M)>> \
HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1_S)
#define HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1_SET(_var, _val) \
do { \
HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1, _val); \
((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PACKET_TYPE_ENABLE_DATA_FPMO_FLAGS1_S)); \
} while (0)
/*
* Subtype based MGMT frames enable bits.
* FP: Filter_Pass, MD: Monitor_Direct MO: Monitor_Other